board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <malloc.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <linux/errno.h>
  19 #include <asm/gpio.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/mach-imx/mxc_i2c.h>
  22 #include <asm/mach-imx/sata.h>
  23 #include <asm/mach-imx/spi.h>
  24 #include <asm/mach-imx/boot_mode.h>
  25 #include <asm/mach-imx/video.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc_imx.h>
  28 #include <micrel.h>
  29 #include <miiphy.h>
  30 #include <netdev.h>
  31 #include <asm/arch/crm_regs.h>
  32 #include <asm/arch/mxc_hdmi.h>
  33 #include <i2c.h>
  34 #include <input.h>
  35 #include <netdev.h>
  36 #include <usb/ehci-ci.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  40
  41 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  46         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  53         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  54
  55 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  57
  58 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  60         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  61
  62 #define RGB_PAD_CTRL    PAD_CTL_DSE_120ohm
  63
  64 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  65         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  66         PAD_CTL_SRE_SLOW)
  67
  68 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  69         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  70         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  71
  72 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  73
  74 /* Prevent compiler error if gpio number 08 or 09 is used */
  75 #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  76
  77 #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,             \
  78                 sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) {                \
  79         .scl = {                                                               \
  80                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  81                                          pad_ctrl),                            \
  82                 .gpio_mode = NEW_PAD_CTRL(                                     \
  83                         cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  84                         pad_ctrl),                                             \
  85                 .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp))                 \
  86         },                                                                     \
  87         .sda = {                                                               \
  88                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  89                                          pad_ctrl),                            \
  90                 .gpio_mode = NEW_PAD_CTRL(                                     \
  91                         cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  92                         pad_ctrl),                                             \
  93                         .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp))         \
  94         }                                                                      \
  95 }
  96
  97 #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,              \
  98                 sda_pad, sda_bank, sda_gp, pad_ctrl)                           \
  99                 _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,     \
 100                                 sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
 101
 102 #if defined(CONFIG_MX6QDL)
 103 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 104                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 105         I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp,      \
 106                 sda_pad, sda_bank, sda_gp, pad_ctrl),                   \
 107         I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp,     \
 108                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 109 #define I2C_PADS_INFO_ENTRY_SPACING 2
 110
 111 #define IOMUX_PAD_CTRL(name, pad_ctrl) \
 112                 NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl),        \
 113                 NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
 114 #else
 115 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 116                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 117         I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp,       \
 118                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 119 #define I2C_PADS_INFO_ENTRY_SPACING 1
 120
 121 #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
 122 #endif
 123
 124 int dram_init(void)
 125 {
 126         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 127
 128         return 0;
 129 }
 130
 131 static iomux_v3_cfg_t const uart1_pads[] = {
 132         IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
 133         IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
 134 };
 135
 136 static iomux_v3_cfg_t const uart2_pads[] = {
 137         IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
 138         IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
 139 };
 140
 141 static struct i2c_pads_info i2c_pads[] = {
 142         /* I2C1, SGTL5000 */
 143         I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
 144         /* I2C2 Camera, MIPI */
 145         I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
 146                             I2C_PAD_CTRL),
 147         /* I2C3, J15 - RGB connector */
 148         I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
 149 };
 150
 151 #define I2C_BUS_CNT    3
 152
 153 static iomux_v3_cfg_t const usdhc2_pads[] = {
 154         IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
 155         IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
 156         IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
 157         IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
 158         IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
 159         IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
 160 };
 161
 162 static iomux_v3_cfg_t const usdhc3_pads[] = {
 163         IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
 164         IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
 165         IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
 166         IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
 167         IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
 168         IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
 169         IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
 170 };
 171
 172 static iomux_v3_cfg_t const usdhc4_pads[] = {
 173         IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
 174         IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
 175         IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
 176         IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
 177         IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
 178         IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
 179         IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
 180 };
 181
 182 static iomux_v3_cfg_t const enet_pads1[] = {
 183         IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
 184         IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
 185         IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
 186         IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
 187         IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
 188         IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
 189         IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
 190         IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
 191         IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
 192         /* pin 35 - 1 (PHY_AD2) on reset */
 193         IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
 194         /* pin 32 - 1 - (MODE0) all */
 195         IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
 196         /* pin 31 - 1 - (MODE1) all */
 197         IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
 198         /* pin 28 - 1 - (MODE2) all */
 199         IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
 200         /* pin 27 - 1 - (MODE3) all */
 201         IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
 202         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 203         IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
 204         /* pin 42 PHY nRST */
 205         IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
 206         IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
 207 };
 208
 209 static iomux_v3_cfg_t const enet_pads2[] = {
 210         IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
 211         IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
 212         IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
 213         IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
 214         IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
 215         IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
 216 };
 217
 218 static iomux_v3_cfg_t const misc_pads[] = {
 219         IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
 220         IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
 221         IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
 222         /* OTG Power enable */
 223         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 224 };
 225
 226 /* wl1271 pads on nitrogen6x */
 227 static iomux_v3_cfg_t const wl12xx_pads[] = {
 228         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 229         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 230         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 231 };
 232 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 233 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 234 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 235
 236 /* Button assignments for J14 */
 237 static iomux_v3_cfg_t const button_pads[] = {
 238         /* Menu */
 239         IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
 240         /* Back */
 241         IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
 242         /* Labelled Search (mapped to Power under Android) */
 243         IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
 244         /* Home */
 245         IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
 246         /* Volume Down */
 247         IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
 248         /* Volume Up */
 249         IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
 250 };
 251
 252 static void setup_iomux_enet(void)
 253 {
 254         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 255         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 256         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 257         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 258         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 259         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 260         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 261         SETUP_IOMUX_PADS(enet_pads1);
 262         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 263
 264         /* Need delay 10ms according to KSZ9021 spec */
 265         udelay(1000 * 10);
 266         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 267         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 268
 269         SETUP_IOMUX_PADS(enet_pads2);
 270         udelay(100);    /* Wait 100 us before using mii interface */
 271 }
 272
 273 static iomux_v3_cfg_t const usb_pads[] = {
 274         IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
 275 };
 276
 277 static void setup_iomux_uart(void)
 278 {
 279         SETUP_IOMUX_PADS(uart1_pads);
 280         SETUP_IOMUX_PADS(uart2_pads);
 281 }
 282
 283 #ifdef CONFIG_USB_EHCI_MX6
 284 int board_ehci_hcd_init(int port)
 285 {
 286         SETUP_IOMUX_PADS(usb_pads);
 287
 288         /* Reset USB hub */
 289         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 290         mdelay(2);
 291         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 292
 293         return 0;
 294 }
 295
 296 int board_ehci_power(int port, int on)
 297 {
 298         if (port)
 299                 return 0;
 300         gpio_set_value(GP_USB_OTG_PWR, on);
 301         return 0;
 302 }
 303
 304 #endif
 305
 306 #ifdef CONFIG_FSL_ESDHC_IMX
 307 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 308         {USDHC3_BASE_ADDR},
 309         {USDHC4_BASE_ADDR},
 310 };
 311
 312 int board_mmc_getcd(struct mmc *mmc)
 313 {
 314         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 315         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 316                         IMX_GPIO_NR(2, 6);
 317
 318         gpio_direction_input(gp_cd);
 319         return !gpio_get_value(gp_cd);
 320 }
 321
 322 int board_mmc_init(bd_t *bis)
 323 {
 324         int ret;
 325         u32 index = 0;
 326
 327         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 328         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 329
 330         usdhc_cfg[0].max_bus_width = 4;
 331         usdhc_cfg[1].max_bus_width = 4;
 332
 333         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 334                 switch (index) {
 335                 case 0:
 336                         SETUP_IOMUX_PADS(usdhc3_pads);
 337                         break;
 338                 case 1:
 339                        SETUP_IOMUX_PADS(usdhc4_pads);
 340                        break;
 341                 default:
 342                        printf("Warning: you configured more USDHC controllers"
 343                                "(%d) then supported by the board (%d)\n",
 344                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 345                        return -EINVAL;
 346                 }
 347
 348                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 349                 if (ret)
 350                         return ret;
 351         }
 352
 353         return 0;
 354 }
 355 #endif
 356
 357 #ifdef CONFIG_MXC_SPI
 358 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 359 {
 360         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 361 }
 362
 363 static iomux_v3_cfg_t const ecspi1_pads[] = {
 364         /* SS1 */
 365         IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
 366         IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
 367         IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
 368         IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
 369 };
 370
 371 static void setup_spi(void)
 372 {
 373         SETUP_IOMUX_PADS(ecspi1_pads);
 374 }
 375 #endif
 376
 377 int board_phy_config(struct phy_device *phydev)
 378 {
 379         /* min rx data delay */
 380         ksz9021_phy_extended_write(phydev,
 381                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 382         /* min tx data delay */
 383         ksz9021_phy_extended_write(phydev,
 384                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 385         /* max rx/tx clock delay, min rx/tx control */
 386         ksz9021_phy_extended_write(phydev,
 387                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 388         if (phydev->drv->config)
 389                 phydev->drv->config(phydev);
 390
 391         return 0;
 392 }
 393
 394 int board_eth_init(bd_t *bis)
 395 {
 396         uint32_t base = IMX_FEC_BASE;
 397         struct mii_dev *bus = NULL;
 398         struct phy_device *phydev = NULL;
 399         int ret;
 400
 401         gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
 402         gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
 403         gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
 404         gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
 405         gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
 406         gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
 407         gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
 408         gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
 409         gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
 410         setup_iomux_enet();
 411
 412 #ifdef CONFIG_FEC_MXC
 413         bus = fec_get_miibus(base, -1);
 414         if (!bus)
 415                 return -EINVAL;
 416         /* scan phy 4,5,6,7 */
 417         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 418         if (!phydev) {
 419                 ret = -EINVAL;
 420                 goto free_bus;
 421         }
 422         printf("using phy at %d\n", phydev->addr);
 423         ret  = fec_probe(bis, -1, base, bus, phydev);
 424         if (ret)
 425                 goto free_phydev;
 426 #endif
 427
 428 #ifdef CONFIG_CI_UDC
 429         /* For otg ethernet*/
 430         usb_eth_initialize(bis);
 431 #endif
 432         return 0;
 433
 434 free_phydev:
 435         free(phydev);
 436 free_bus:
 437         free(bus);
 438         return ret;
 439 }
 440
 441 static void setup_buttons(void)
 442 {
 443         SETUP_IOMUX_PADS(button_pads);
 444 }
 445
 446 #if defined(CONFIG_VIDEO_IPUV3)
 447
 448 static iomux_v3_cfg_t const backlight_pads[] = {
 449         /* Backlight on RGB connector: J15 */
 450         IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
 451 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 452
 453         /* Backlight on LVDS connector: J6 */
 454         IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
 455 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 456 };
 457
 458 static iomux_v3_cfg_t const rgb_pads[] = {
 459         IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
 460         IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
 461         IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
 462         IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
 463         IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
 464         IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
 465         IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
 466         IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
 467         IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
 468         IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
 469         IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
 470         IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
 471         IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
 472         IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
 473         IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
 474         IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
 475         IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
 476         IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
 477         IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
 478         IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
 479         IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
 480         IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
 481         IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
 482         IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
 483         IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
 484         IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
 485         IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
 486         IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
 487         IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
 488 };
 489
 490 static void do_enable_hdmi(struct display_info_t const *dev)
 491 {
 492         imx_enable_hdmi_phy();
 493 }
 494
 495 static int detect_i2c(struct display_info_t const *dev)
 496 {
 497         return ((0 == i2c_set_bus_num(dev->bus))
 498                 &&
 499                 (0 == i2c_probe(dev->addr)));
 500 }
 501
 502 static void enable_lvds(struct display_info_t const *dev)
 503 {
 504         struct iomuxc *iomux = (struct iomuxc *)
 505                                 IOMUXC_BASE_ADDR;
 506         u32 reg = readl(&iomux->gpr[2]);
 507         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 508         writel(reg, &iomux->gpr[2]);
 509         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 510 }
 511
 512 static void enable_lvds_jeida(struct display_info_t const *dev)
 513 {
 514         struct iomuxc *iomux = (struct iomuxc *)
 515                                 IOMUXC_BASE_ADDR;
 516         u32 reg = readl(&iomux->gpr[2]);
 517         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 518              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 519         writel(reg, &iomux->gpr[2]);
 520         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 521 }
 522
 523 static void enable_rgb(struct display_info_t const *dev)
 524 {
 525         SETUP_IOMUX_PADS(rgb_pads);
 526         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 527 }
 528
 529 struct display_info_t const displays[] = {{
 530         .bus    = 1,
 531         .addr   = 0x50,
 532         .pixfmt = IPU_PIX_FMT_RGB24,
 533         .detect = detect_i2c,
 534         .enable = do_enable_hdmi,
 535         .mode   = {
 536                 .name           = "HDMI",
 537                 .refresh        = 60,
 538                 .xres           = 1024,
 539                 .yres           = 768,
 540                 .pixclock       = 15385,
 541                 .left_margin    = 220,
 542                 .right_margin   = 40,
 543                 .upper_margin   = 21,
 544                 .lower_margin   = 7,
 545                 .hsync_len      = 60,
 546                 .vsync_len      = 10,
 547                 .sync           = FB_SYNC_EXT,
 548                 .vmode          = FB_VMODE_NONINTERLACED
 549 } }, {
 550         .bus    = 0,
 551         .addr   = 0,
 552         .pixfmt = IPU_PIX_FMT_RGB24,
 553         .detect = NULL,
 554         .enable = enable_lvds_jeida,
 555         .mode   = {
 556                 .name           = "LDB-WXGA",
 557                 .refresh        = 60,
 558                 .xres           = 1280,
 559                 .yres           = 800,
 560                 .pixclock       = 14065,
 561                 .left_margin    = 40,
 562                 .right_margin   = 40,
 563                 .upper_margin   = 3,
 564                 .lower_margin   = 80,
 565                 .hsync_len      = 10,
 566                 .vsync_len      = 10,
 567                 .sync           = FB_SYNC_EXT,
 568                 .vmode          = FB_VMODE_NONINTERLACED
 569 } }, {
 570         .bus    = 0,
 571         .addr   = 0,
 572         .pixfmt = IPU_PIX_FMT_RGB24,
 573         .detect = NULL,
 574         .enable = enable_lvds,
 575         .mode   = {
 576                 .name           = "LDB-WXGA-S",
 577                 .refresh        = 60,
 578                 .xres           = 1280,
 579                 .yres           = 800,
 580                 .pixclock       = 14065,
 581                 .left_margin    = 40,
 582                 .right_margin   = 40,
 583                 .upper_margin   = 3,
 584                 .lower_margin   = 80,
 585                 .hsync_len      = 10,
 586                 .vsync_len      = 10,
 587                 .sync           = FB_SYNC_EXT,
 588                 .vmode          = FB_VMODE_NONINTERLACED
 589 } }, {
 590         .bus    = 2,
 591         .addr   = 0x4,
 592         .pixfmt = IPU_PIX_FMT_LVDS666,
 593         .detect = detect_i2c,
 594         .enable = enable_lvds,
 595         .mode   = {
 596                 .name           = "Hannstar-XGA",
 597                 .refresh        = 60,
 598                 .xres           = 1024,
 599                 .yres           = 768,
 600                 .pixclock       = 15385,
 601                 .left_margin    = 220,
 602                 .right_margin   = 40,
 603                 .upper_margin   = 21,
 604                 .lower_margin   = 7,
 605                 .hsync_len      = 60,
 606                 .vsync_len      = 10,
 607                 .sync           = FB_SYNC_EXT,
 608                 .vmode          = FB_VMODE_NONINTERLACED
 609 } }, {
 610         .bus    = 0,
 611         .addr   = 0,
 612         .pixfmt = IPU_PIX_FMT_LVDS666,
 613         .detect = NULL,
 614         .enable = enable_lvds,
 615         .mode   = {
 616                 .name           = "LG-9.7",
 617                 .refresh        = 60,
 618                 .xres           = 1024,
 619                 .yres           = 768,
 620                 .pixclock       = 15385, /* ~65MHz */
 621                 .left_margin    = 480,
 622                 .right_margin   = 260,
 623                 .upper_margin   = 16,
 624                 .lower_margin   = 6,
 625                 .hsync_len      = 250,
 626                 .vsync_len      = 10,
 627                 .sync           = FB_SYNC_EXT,
 628                 .vmode          = FB_VMODE_NONINTERLACED
 629 } }, {
 630         .bus    = 2,
 631         .addr   = 0x38,
 632         .pixfmt = IPU_PIX_FMT_LVDS666,
 633         .detect = detect_i2c,
 634         .enable = enable_lvds,
 635         .mode   = {
 636                 .name           = "wsvga-lvds",
 637                 .refresh        = 60,
 638                 .xres           = 1024,
 639                 .yres           = 600,
 640                 .pixclock       = 15385,
 641                 .left_margin    = 220,
 642                 .right_margin   = 40,
 643                 .upper_margin   = 21,
 644                 .lower_margin   = 7,
 645                 .hsync_len      = 60,
 646                 .vsync_len      = 10,
 647                 .sync           = FB_SYNC_EXT,
 648                 .vmode          = FB_VMODE_NONINTERLACED
 649 } }, {
 650         .bus    = 2,
 651         .addr   = 0x10,
 652         .pixfmt = IPU_PIX_FMT_RGB666,
 653         .detect = detect_i2c,
 654         .enable = enable_rgb,
 655         .mode   = {
 656                 .name           = "fusion7",
 657                 .refresh        = 60,
 658                 .xres           = 800,
 659                 .yres           = 480,
 660                 .pixclock       = 33898,
 661                 .left_margin    = 96,
 662                 .right_margin   = 24,
 663                 .upper_margin   = 3,
 664                 .lower_margin   = 10,
 665                 .hsync_len      = 72,
 666                 .vsync_len      = 7,
 667                 .sync           = 0x40000002,
 668                 .vmode          = FB_VMODE_NONINTERLACED
 669 } }, {
 670         .bus    = 0,
 671         .addr   = 0,
 672         .pixfmt = IPU_PIX_FMT_RGB666,
 673         .detect = NULL,
 674         .enable = enable_rgb,
 675         .mode   = {
 676                 .name           = "svga",
 677                 .refresh        = 60,
 678                 .xres           = 800,
 679                 .yres           = 600,
 680                 .pixclock       = 15385,
 681                 .left_margin    = 220,
 682                 .right_margin   = 40,
 683                 .upper_margin   = 21,
 684                 .lower_margin   = 7,
 685                 .hsync_len      = 60,
 686                 .vsync_len      = 10,
 687                 .sync           = 0,
 688                 .vmode          = FB_VMODE_NONINTERLACED
 689 } }, {
 690         .bus    = 2,
 691         .addr   = 0x41,
 692         .pixfmt = IPU_PIX_FMT_LVDS666,
 693         .detect = detect_i2c,
 694         .enable = enable_lvds,
 695         .mode   = {
 696                 .name           = "amp1024x600",
 697                 .refresh        = 60,
 698                 .xres           = 1024,
 699                 .yres           = 600,
 700                 .pixclock       = 15385,
 701                 .left_margin    = 220,
 702                 .right_margin   = 40,
 703                 .upper_margin   = 21,
 704                 .lower_margin   = 7,
 705                 .hsync_len      = 60,
 706                 .vsync_len      = 10,
 707                 .sync           = FB_SYNC_EXT,
 708                 .vmode          = FB_VMODE_NONINTERLACED
 709 } }, {
 710         .bus    = 0,
 711         .addr   = 0,
 712         .pixfmt = IPU_PIX_FMT_LVDS666,
 713         .detect = 0,
 714         .enable = enable_lvds,
 715         .mode   = {
 716                 .name           = "wvga-lvds",
 717                 .refresh        = 57,
 718                 .xres           = 800,
 719                 .yres           = 480,
 720                 .pixclock       = 15385,
 721                 .left_margin    = 220,
 722                 .right_margin   = 40,
 723                 .upper_margin   = 21,
 724                 .lower_margin   = 7,
 725                 .hsync_len      = 60,
 726                 .vsync_len      = 10,
 727                 .sync           = FB_SYNC_EXT,
 728                 .vmode          = FB_VMODE_NONINTERLACED
 729 } }, {
 730         .bus    = 2,
 731         .addr   = 0x48,
 732         .pixfmt = IPU_PIX_FMT_RGB666,
 733         .detect = detect_i2c,
 734         .enable = enable_rgb,
 735         .mode   = {
 736                 .name           = "wvga-rgb",
 737                 .refresh        = 57,
 738                 .xres           = 800,
 739                 .yres           = 480,
 740                 .pixclock       = 37037,
 741                 .left_margin    = 40,
 742                 .right_margin   = 60,
 743                 .upper_margin   = 10,
 744                 .lower_margin   = 10,
 745                 .hsync_len      = 20,
 746                 .vsync_len      = 10,
 747                 .sync           = 0,
 748                 .vmode          = FB_VMODE_NONINTERLACED
 749 } }, {
 750         .bus    = 0,
 751         .addr   = 0,
 752         .pixfmt = IPU_PIX_FMT_RGB24,
 753         .detect = NULL,
 754         .enable = enable_rgb,
 755         .mode   = {
 756                 .name           = "qvga",
 757                 .refresh        = 60,
 758                 .xres           = 320,
 759                 .yres           = 240,
 760                 .pixclock       = 37037,
 761                 .left_margin    = 38,
 762                 .right_margin   = 37,
 763                 .upper_margin   = 16,
 764                 .lower_margin   = 15,
 765                 .hsync_len      = 30,
 766                 .vsync_len      = 3,
 767                 .sync           = 0,
 768                 .vmode          = FB_VMODE_NONINTERLACED
 769 } } };
 770 size_t display_count = ARRAY_SIZE(displays);
 771
 772 int board_cfb_skip(void)
 773 {
 774         return NULL != env_get("novideo");
 775 }
 776
 777 static void setup_display(void)
 778 {
 779         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 780         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 781         int reg;
 782
 783         enable_ipu_clock();
 784         imx_setup_hdmi();
 785         /* Turn on LDB0,IPU,IPU DI0 clocks */
 786         reg = __raw_readl(&mxc_ccm->CCGR3);
 787         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 788         writel(reg, &mxc_ccm->CCGR3);
 789
 790         /* set LDB0, LDB1 clk select to 011/011 */
 791         reg = readl(&mxc_ccm->cs2cdr);
 792         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 793                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 794         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 795               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 796         writel(reg, &mxc_ccm->cs2cdr);
 797
 798         reg = readl(&mxc_ccm->cscmr2);
 799         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 800         writel(reg, &mxc_ccm->cscmr2);
 801
 802         reg = readl(&mxc_ccm->chsccdr);
 803         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 804                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 805         writel(reg, &mxc_ccm->chsccdr);
 806
 807         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 808              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 809              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 810              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 811              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 812              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 813              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 814              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 815              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 816         writel(reg, &iomux->gpr[2]);
 817
 818         reg = readl(&iomux->gpr[3]);
 819         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 820                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 821             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 822                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 823         writel(reg, &iomux->gpr[3]);
 824
 825         /* backlights off until needed */
 826         SETUP_IOMUX_PADS(backlight_pads);
 827         gpio_direction_input(LVDS_BACKLIGHT_GP);
 828         gpio_direction_input(RGB_BACKLIGHT_GP);
 829 }
 830 #endif
 831
 832 static iomux_v3_cfg_t const init_pads[] = {
 833         /* SGTL5000 sys_mclk */
 834         IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 835
 836         /* J5 - Camera MCLK */
 837         IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 838
 839         /* wl1271 pads on nitrogen6x */
 840         /* WL12XX_WL_IRQ_GP */
 841         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 842         /* WL12XX_WL_ENABLE_GP */
 843         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 844         /* WL12XX_BT_ENABLE_GP */
 845         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 846         /* USB otg power */
 847         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 848         IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 849         IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 850         IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 851         IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 852 };
 853
 854 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 855
 856 static unsigned gpios_out_low[] = {
 857         /* Disable wl1271 */
 858         IMX_GPIO_NR(6, 15),     /* disable wireless */
 859         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 860         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 861         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 862         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 863 };
 864
 865 static unsigned gpios_out_high[] = {
 866         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 867         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 868 };
 869
 870 static void set_gpios(unsigned *p, int cnt, int val)
 871 {
 872         int i;
 873
 874         for (i = 0; i < cnt; i++)
 875                 gpio_direction_output(*p++, val);
 876 }
 877
 878 int board_early_init_f(void)
 879 {
 880         setup_iomux_uart();
 881
 882         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 883         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 884         gpio_direction_input(WL12XX_WL_IRQ_GP);
 885
 886         SETUP_IOMUX_PADS(wl12xx_pads);
 887         SETUP_IOMUX_PADS(init_pads);
 888         setup_buttons();
 889
 890 #if defined(CONFIG_VIDEO_IPUV3)
 891         setup_display();
 892 #endif
 893         return 0;
 894 }
 895
 896 /*
 897  * Do not overwrite the console
 898  * Use always serial for U-Boot console
 899  */
 900 int overwrite_console(void)
 901 {
 902         return 1;
 903 }
 904
 905 int board_init(void)
 906 {
 907         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 908         struct i2c_pads_info *p = i2c_pads;
 909         int i;
 910         int stride = 1;
 911
 912 #if defined(CONFIG_MX6QDL)
 913         stride = 2;
 914         if (!is_mx6dq() && !is_mx6dqp())
 915                 p += 1;
 916 #endif
 917         clrsetbits_le32(&iomuxc_regs->gpr[1],
 918                         IOMUXC_GPR1_OTG_ID_MASK,
 919                         IOMUXC_GPR1_OTG_ID_GPIO1);
 920
 921         SETUP_IOMUX_PADS(misc_pads);
 922
 923         /* address of boot parameters */
 924         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 925
 926 #ifdef CONFIG_MXC_SPI
 927         setup_spi();
 928 #endif
 929         SETUP_IOMUX_PADS(usdhc2_pads);
 930         for (i = 0; i < I2C_BUS_CNT; i++) {
 931                 setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
 932                 p += stride;
 933         }
 934
 935 #ifdef CONFIG_SATA
 936         setup_sata();
 937 #endif
 938
 939         return 0;
 940 }
 941
 942 int checkboard(void)
 943 {
 944         int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
 945
 946         if (ret < 0) {
 947                 /* The gpios have not been probed yet. Read it myself */
 948                 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
 949                 int gpio = WL12XX_WL_IRQ_GP & 0x1f;
 950
 951                 ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 952         }
 953         if (ret)
 954                 puts("Board: Nitrogen6X\n");
 955         else
 956                 puts("Board: SABRE Lite\n");
 957
 958         return 0;
 959 }
 960
 961 struct button_key {
 962         char const      *name;
 963         unsigned        gpnum;
 964         char            ident;
 965 };
 966
 967 static struct button_key const buttons[] = {
 968         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 969         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 970         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 971         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 972         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 973         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 974 };
 975
 976 /*
 977  * generate a null-terminated string containing the buttons pressed
 978  * returns number of keys pressed
 979  */
 980 static int read_keys(char *buf)
 981 {
 982         int i, numpressed = 0;
 983         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 984                 if (!gpio_get_value(buttons[i].gpnum))
 985                         buf[numpressed++] = buttons[i].ident;
 986         }
 987         buf[numpressed] = '\0';
 988         return numpressed;
 989 }
 990
 991 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 992 {
 993         char envvalue[ARRAY_SIZE(buttons)+1];
 994         int numpressed = read_keys(envvalue);
 995         env_set("keybd", envvalue);
 996         return numpressed == 0;
 997 }
 998
 999 U_BOOT_CMD(
1000         kbd, 1, 1, do_kbd,
1001         "Tests for keypresses, sets 'keybd' environment variable",
1002         "Returns 0 (true) to shell if key is pressed."
1003 );
1004
1005 #ifdef CONFIG_PREBOOT
1006 static char const kbd_magic_prefix[] = "key_magic";
1007 static char const kbd_command_prefix[] = "key_cmd";
1008
1009 static void preboot_keys(void)
1010 {
1011         int numpressed;
1012         char keypress[ARRAY_SIZE(buttons)+1];
1013         numpressed = read_keys(keypress);
1014         if (numpressed) {
1015                 char *kbd_magic_keys = env_get("magic_keys");
1016                 char *suffix;
1017                 /*
1018                  * loop over all magic keys
1019                  */
1020                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
1021                         char *keys;
1022                         char magic[sizeof(kbd_magic_prefix) + 1];
1023                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
1024                         keys = env_get(magic);
1025                         if (keys) {
1026                                 if (!strcmp(keys, keypress))
1027                                         break;
1028                         }
1029                 }
1030                 if (*suffix) {
1031                         char cmd_name[sizeof(kbd_command_prefix) + 1];
1032                         char *cmd;
1033                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
1034                         cmd = env_get(cmd_name);
1035                         if (cmd) {
1036                                 env_set("preboot", cmd);
1037                                 return;
1038                         }
1039                 }
1040         }
1041 }
1042 #endif
1043
1044 #ifdef CONFIG_CMD_BMODE
1045 static const struct boot_mode board_boot_modes[] = {
1046         /* 4 bit bus width */
1047         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1048         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1049         {NULL,          0},
1050 };
1051 #endif
1052
1053 int misc_init_r(void)
1054 {
1055         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
1056         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
1057         gpio_request(GP_USB_OTG_PWR, "usbotg power");
1058         gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
1059         gpio_request(IMX_GPIO_NR(2, 2), "back");
1060         gpio_request(IMX_GPIO_NR(2, 4), "home");
1061         gpio_request(IMX_GPIO_NR(2, 1), "menu");
1062         gpio_request(IMX_GPIO_NR(2, 3), "search");
1063         gpio_request(IMX_GPIO_NR(7, 13), "volup");
1064         gpio_request(IMX_GPIO_NR(4, 5), "voldown");
1065 #ifdef CONFIG_PREBOOT
1066         preboot_keys();
1067 #endif
1068
1069 #ifdef CONFIG_CMD_BMODE
1070         add_board_boot_modes(board_boot_modes);
1071 #endif
1072         env_set_hex("reset_cause", get_imx_reset_cause());
1073         return 0;
1074 }