board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <malloc.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <linux/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/mach-imx/sata.h>
  20 #include <asm/mach-imx/spi.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/video.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc_imx.h>
  25 #include <micrel.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/mxc_hdmi.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <netdev.h>
  33 #include <usb/ehci-ci.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  43         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  50         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  51
  52 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  58
  59 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_SRE_SLOW)
  62
  63 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  65         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  66
  67 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  72
  73         return 0;
  74 }
  75
  76 static iomux_v3_cfg_t const uart1_pads[] = {
  77         MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const uart2_pads[] = {
  82         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84 };
  85
  86 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  87
  88 /* I2C1, SGTL5000 */
  89 static struct i2c_pads_info i2c_pad_info0 = {
  90         .scl = {
  91                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  92                 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  93                 .gp = IMX_GPIO_NR(3, 21)
  94         },
  95         .sda = {
  96                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  97                 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  98                 .gp = IMX_GPIO_NR(3, 28)
  99         }
 100 };
 101
 102 /* I2C2 Camera, MIPI */
 103 static struct i2c_pads_info i2c_pad_info1 = {
 104         .scl = {
 105                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 106                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 107                 .gp = IMX_GPIO_NR(4, 12)
 108         },
 109         .sda = {
 110                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 111                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 112                 .gp = IMX_GPIO_NR(4, 13)
 113         }
 114 };
 115
 116 /* I2C3, J15 - RGB connector */
 117 static struct i2c_pads_info i2c_pad_info2 = {
 118         .scl = {
 119                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 120                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
 121                 .gp = IMX_GPIO_NR(1, 5)
 122         },
 123         .sda = {
 124                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 125                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
 126                 .gp = IMX_GPIO_NR(7, 11)
 127         }
 128 };
 129
 130 static iomux_v3_cfg_t const usdhc2_pads[] = {
 131         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137 };
 138
 139 static iomux_v3_cfg_t const usdhc3_pads[] = {
 140         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 147 };
 148
 149 static iomux_v3_cfg_t const usdhc4_pads[] = {
 150         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 157 };
 158
 159 static iomux_v3_cfg_t const enet_pads1[] = {
 160         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         /* pin 35 - 1 (PHY_AD2) on reset */
 170         MX6_PAD_RGMII_RXC__GPIO6_IO30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 171         /* pin 32 - 1 - (MODE0) all */
 172         MX6_PAD_RGMII_RD0__GPIO6_IO25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 173         /* pin 31 - 1 - (MODE1) all */
 174         MX6_PAD_RGMII_RD1__GPIO6_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         /* pin 28 - 1 - (MODE2) all */
 176         MX6_PAD_RGMII_RD2__GPIO6_IO28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 177         /* pin 27 - 1 - (MODE3) all */
 178         MX6_PAD_RGMII_RD3__GPIO6_IO29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 179         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 180         MX6_PAD_RGMII_RX_CTL__GPIO6_IO24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 181         /* pin 42 PHY nRST */
 182         MX6_PAD_EIM_D23__GPIO3_IO23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 183         MX6_PAD_ENET_RXD0__GPIO1_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 184 };
 185
 186 static iomux_v3_cfg_t const enet_pads2[] = {
 187         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 188         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 189         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 190         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 191         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 192         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 193 };
 194
 195 static iomux_v3_cfg_t const misc_pads[] = {
 196         MX6_PAD_GPIO_1__USB_OTG_ID              | MUX_PAD_CTRL(WEAK_PULLUP),
 197         MX6_PAD_KEY_COL4__USB_OTG_OC            | MUX_PAD_CTRL(WEAK_PULLUP),
 198         MX6_PAD_EIM_D30__USB_H1_OC              | MUX_PAD_CTRL(WEAK_PULLUP),
 199         /* OTG Power enable */
 200         MX6_PAD_EIM_D22__GPIO3_IO22             | MUX_PAD_CTRL(OUTPUT_40OHM),
 201 };
 202
 203 /* wl1271 pads on nitrogen6x */
 204 static iomux_v3_cfg_t const wl12xx_pads[] = {
 205         (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
 206                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 207         (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
 208                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 209         (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
 210                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 211 };
 212 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 213 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 214 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 215
 216 /* Button assignments for J14 */
 217 static iomux_v3_cfg_t const button_pads[] = {
 218         /* Menu */
 219         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 220         /* Back */
 221         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 222         /* Labelled Search (mapped to Power under Android) */
 223         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 224         /* Home */
 225         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 226         /* Volume Down */
 227         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 228         /* Volume Up */
 229         MX6_PAD_GPIO_18__GPIO7_IO13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 230 };
 231
 232 static void setup_iomux_enet(void)
 233 {
 234         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 235         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 236         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 237         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 238         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 239         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 240         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 241         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 242         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 243
 244         /* Need delay 10ms according to KSZ9021 spec */
 245         udelay(1000 * 10);
 246         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 247         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 248
 249         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 250         udelay(100);    /* Wait 100 us before using mii interface */
 251 }
 252
 253 static iomux_v3_cfg_t const usb_pads[] = {
 254         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 255 };
 256
 257 static void setup_iomux_uart(void)
 258 {
 259         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 260         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 261 }
 262
 263 #ifdef CONFIG_USB_EHCI_MX6
 264 int board_ehci_hcd_init(int port)
 265 {
 266         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 267
 268         /* Reset USB hub */
 269         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 270         mdelay(2);
 271         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 272
 273         return 0;
 274 }
 275
 276 int board_ehci_power(int port, int on)
 277 {
 278         if (port)
 279                 return 0;
 280         gpio_set_value(GP_USB_OTG_PWR, on);
 281         return 0;
 282 }
 283
 284 #endif
 285
 286 #ifdef CONFIG_FSL_ESDHC_IMX
 287 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 288         {USDHC3_BASE_ADDR},
 289         {USDHC4_BASE_ADDR},
 290 };
 291
 292 int board_mmc_getcd(struct mmc *mmc)
 293 {
 294         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 295         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 296                         IMX_GPIO_NR(2, 6);
 297
 298         gpio_direction_input(gp_cd);
 299         return !gpio_get_value(gp_cd);
 300 }
 301
 302 int board_mmc_init(bd_t *bis)
 303 {
 304         int ret;
 305         u32 index = 0;
 306
 307         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 308         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 309
 310         usdhc_cfg[0].max_bus_width = 4;
 311         usdhc_cfg[1].max_bus_width = 4;
 312
 313         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 314                 switch (index) {
 315                 case 0:
 316                         imx_iomux_v3_setup_multiple_pads(
 317                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 318                         break;
 319                 case 1:
 320                        imx_iomux_v3_setup_multiple_pads(
 321                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 322                        break;
 323                 default:
 324                        printf("Warning: you configured more USDHC controllers"
 325                                "(%d) then supported by the board (%d)\n",
 326                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 327                        return -EINVAL;
 328                 }
 329
 330                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 331                 if (ret)
 332                         return ret;
 333         }
 334
 335         return 0;
 336 }
 337 #endif
 338
 339 #ifdef CONFIG_MXC_SPI
 340 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 341 {
 342         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 343 }
 344
 345 static iomux_v3_cfg_t const ecspi1_pads[] = {
 346         /* SS1 */
 347         MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
 348         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 349         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 350         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 351 };
 352
 353 static void setup_spi(void)
 354 {
 355         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 356                                          ARRAY_SIZE(ecspi1_pads));
 357 }
 358 #endif
 359
 360 int board_phy_config(struct phy_device *phydev)
 361 {
 362         /* min rx data delay */
 363         ksz9021_phy_extended_write(phydev,
 364                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 365         /* min tx data delay */
 366         ksz9021_phy_extended_write(phydev,
 367                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 368         /* max rx/tx clock delay, min rx/tx control */
 369         ksz9021_phy_extended_write(phydev,
 370                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 371         if (phydev->drv->config)
 372                 phydev->drv->config(phydev);
 373
 374         return 0;
 375 }
 376
 377 int board_eth_init(bd_t *bis)
 378 {
 379         uint32_t base = IMX_FEC_BASE;
 380         struct mii_dev *bus = NULL;
 381         struct phy_device *phydev = NULL;
 382         int ret;
 383
 384         setup_iomux_enet();
 385
 386 #ifdef CONFIG_FEC_MXC
 387         bus = fec_get_miibus(base, -1);
 388         if (!bus)
 389                 return -EINVAL;
 390         /* scan phy 4,5,6,7 */
 391         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 392         if (!phydev) {
 393                 ret = -EINVAL;
 394                 goto free_bus;
 395         }
 396         printf("using phy at %d\n", phydev->addr);
 397         ret  = fec_probe(bis, -1, base, bus, phydev);
 398         if (ret)
 399                 goto free_phydev;
 400 #endif
 401
 402 #ifdef CONFIG_CI_UDC
 403         /* For otg ethernet*/
 404         usb_eth_initialize(bis);
 405 #endif
 406         return 0;
 407
 408 free_phydev:
 409         free(phydev);
 410 free_bus:
 411         free(bus);
 412         return ret;
 413 }
 414
 415 static void setup_buttons(void)
 416 {
 417         imx_iomux_v3_setup_multiple_pads(button_pads,
 418                                          ARRAY_SIZE(button_pads));
 419 }
 420
 421 #if defined(CONFIG_VIDEO_IPUV3)
 422
 423 static iomux_v3_cfg_t const backlight_pads[] = {
 424         /* Backlight on RGB connector: J15 */
 425         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 426 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 427
 428         /* Backlight on LVDS connector: J6 */
 429         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 430 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 431 };
 432
 433 static iomux_v3_cfg_t const rgb_pads[] = {
 434         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 435         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 436         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 437         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 438         MX6_PAD_DI0_PIN4__GPIO4_IO20,
 439         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 440         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 441         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 442         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 443         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 444         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 445         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 446         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 447         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 448         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 449         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 450         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 451         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 452         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 453         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 454         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 455         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 456         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 457         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 458         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 459         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 460         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 461         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 462         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 463 };
 464
 465 static void do_enable_hdmi(struct display_info_t const *dev)
 466 {
 467         imx_enable_hdmi_phy();
 468 }
 469
 470 static int detect_i2c(struct display_info_t const *dev)
 471 {
 472         return ((0 == i2c_set_bus_num(dev->bus))
 473                 &&
 474                 (0 == i2c_probe(dev->addr)));
 475 }
 476
 477 static void enable_lvds(struct display_info_t const *dev)
 478 {
 479         struct iomuxc *iomux = (struct iomuxc *)
 480                                 IOMUXC_BASE_ADDR;
 481         u32 reg = readl(&iomux->gpr[2]);
 482         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 483         writel(reg, &iomux->gpr[2]);
 484         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 485 }
 486
 487 static void enable_lvds_jeida(struct display_info_t const *dev)
 488 {
 489         struct iomuxc *iomux = (struct iomuxc *)
 490                                 IOMUXC_BASE_ADDR;
 491         u32 reg = readl(&iomux->gpr[2]);
 492         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 493              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 494         writel(reg, &iomux->gpr[2]);
 495         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 496 }
 497
 498 static void enable_rgb(struct display_info_t const *dev)
 499 {
 500         imx_iomux_v3_setup_multiple_pads(
 501                 rgb_pads,
 502                  ARRAY_SIZE(rgb_pads));
 503         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 504 }
 505
 506 struct display_info_t const displays[] = {{
 507         .bus    = 1,
 508         .addr   = 0x50,
 509         .pixfmt = IPU_PIX_FMT_RGB24,
 510         .detect = detect_i2c,
 511         .enable = do_enable_hdmi,
 512         .mode   = {
 513                 .name           = "HDMI",
 514                 .refresh        = 60,
 515                 .xres           = 1024,
 516                 .yres           = 768,
 517                 .pixclock       = 15385,
 518                 .left_margin    = 220,
 519                 .right_margin   = 40,
 520                 .upper_margin   = 21,
 521                 .lower_margin   = 7,
 522                 .hsync_len      = 60,
 523                 .vsync_len      = 10,
 524                 .sync           = FB_SYNC_EXT,
 525                 .vmode          = FB_VMODE_NONINTERLACED
 526 } }, {
 527         .bus    = 0,
 528         .addr   = 0,
 529         .pixfmt = IPU_PIX_FMT_RGB24,
 530         .detect = NULL,
 531         .enable = enable_lvds_jeida,
 532         .mode   = {
 533                 .name           = "LDB-WXGA",
 534                 .refresh        = 60,
 535                 .xres           = 1280,
 536                 .yres           = 800,
 537                 .pixclock       = 14065,
 538                 .left_margin    = 40,
 539                 .right_margin   = 40,
 540                 .upper_margin   = 3,
 541                 .lower_margin   = 80,
 542                 .hsync_len      = 10,
 543                 .vsync_len      = 10,
 544                 .sync           = FB_SYNC_EXT,
 545                 .vmode          = FB_VMODE_NONINTERLACED
 546 } }, {
 547         .bus    = 0,
 548         .addr   = 0,
 549         .pixfmt = IPU_PIX_FMT_RGB24,
 550         .detect = NULL,
 551         .enable = enable_lvds,
 552         .mode   = {
 553                 .name           = "LDB-WXGA-S",
 554                 .refresh        = 60,
 555                 .xres           = 1280,
 556                 .yres           = 800,
 557                 .pixclock       = 14065,
 558                 .left_margin    = 40,
 559                 .right_margin   = 40,
 560                 .upper_margin   = 3,
 561                 .lower_margin   = 80,
 562                 .hsync_len      = 10,
 563                 .vsync_len      = 10,
 564                 .sync           = FB_SYNC_EXT,
 565                 .vmode          = FB_VMODE_NONINTERLACED
 566 } }, {
 567         .bus    = 2,
 568         .addr   = 0x4,
 569         .pixfmt = IPU_PIX_FMT_LVDS666,
 570         .detect = detect_i2c,
 571         .enable = enable_lvds,
 572         .mode   = {
 573                 .name           = "Hannstar-XGA",
 574                 .refresh        = 60,
 575                 .xres           = 1024,
 576                 .yres           = 768,
 577                 .pixclock       = 15385,
 578                 .left_margin    = 220,
 579                 .right_margin   = 40,
 580                 .upper_margin   = 21,
 581                 .lower_margin   = 7,
 582                 .hsync_len      = 60,
 583                 .vsync_len      = 10,
 584                 .sync           = FB_SYNC_EXT,
 585                 .vmode          = FB_VMODE_NONINTERLACED
 586 } }, {
 587         .bus    = 0,
 588         .addr   = 0,
 589         .pixfmt = IPU_PIX_FMT_LVDS666,
 590         .detect = NULL,
 591         .enable = enable_lvds,
 592         .mode   = {
 593                 .name           = "LG-9.7",
 594                 .refresh        = 60,
 595                 .xres           = 1024,
 596                 .yres           = 768,
 597                 .pixclock       = 15385, /* ~65MHz */
 598                 .left_margin    = 480,
 599                 .right_margin   = 260,
 600                 .upper_margin   = 16,
 601                 .lower_margin   = 6,
 602                 .hsync_len      = 250,
 603                 .vsync_len      = 10,
 604                 .sync           = FB_SYNC_EXT,
 605                 .vmode          = FB_VMODE_NONINTERLACED
 606 } }, {
 607         .bus    = 2,
 608         .addr   = 0x38,
 609         .pixfmt = IPU_PIX_FMT_LVDS666,
 610         .detect = detect_i2c,
 611         .enable = enable_lvds,
 612         .mode   = {
 613                 .name           = "wsvga-lvds",
 614                 .refresh        = 60,
 615                 .xres           = 1024,
 616                 .yres           = 600,
 617                 .pixclock       = 15385,
 618                 .left_margin    = 220,
 619                 .right_margin   = 40,
 620                 .upper_margin   = 21,
 621                 .lower_margin   = 7,
 622                 .hsync_len      = 60,
 623                 .vsync_len      = 10,
 624                 .sync           = FB_SYNC_EXT,
 625                 .vmode          = FB_VMODE_NONINTERLACED
 626 } }, {
 627         .bus    = 2,
 628         .addr   = 0x10,
 629         .pixfmt = IPU_PIX_FMT_RGB666,
 630         .detect = detect_i2c,
 631         .enable = enable_rgb,
 632         .mode   = {
 633                 .name           = "fusion7",
 634                 .refresh        = 60,
 635                 .xres           = 800,
 636                 .yres           = 480,
 637                 .pixclock       = 33898,
 638                 .left_margin    = 96,
 639                 .right_margin   = 24,
 640                 .upper_margin   = 3,
 641                 .lower_margin   = 10,
 642                 .hsync_len      = 72,
 643                 .vsync_len      = 7,
 644                 .sync           = 0x40000002,
 645                 .vmode          = FB_VMODE_NONINTERLACED
 646 } }, {
 647         .bus    = 0,
 648         .addr   = 0,
 649         .pixfmt = IPU_PIX_FMT_RGB666,
 650         .detect = NULL,
 651         .enable = enable_rgb,
 652         .mode   = {
 653                 .name           = "svga",
 654                 .refresh        = 60,
 655                 .xres           = 800,
 656                 .yres           = 600,
 657                 .pixclock       = 15385,
 658                 .left_margin    = 220,
 659                 .right_margin   = 40,
 660                 .upper_margin   = 21,
 661                 .lower_margin   = 7,
 662                 .hsync_len      = 60,
 663                 .vsync_len      = 10,
 664                 .sync           = 0,
 665                 .vmode          = FB_VMODE_NONINTERLACED
 666 } }, {
 667         .bus    = 2,
 668         .addr   = 0x41,
 669         .pixfmt = IPU_PIX_FMT_LVDS666,
 670         .detect = detect_i2c,
 671         .enable = enable_lvds,
 672         .mode   = {
 673                 .name           = "amp1024x600",
 674                 .refresh        = 60,
 675                 .xres           = 1024,
 676                 .yres           = 600,
 677                 .pixclock       = 15385,
 678                 .left_margin    = 220,
 679                 .right_margin   = 40,
 680                 .upper_margin   = 21,
 681                 .lower_margin   = 7,
 682                 .hsync_len      = 60,
 683                 .vsync_len      = 10,
 684                 .sync           = FB_SYNC_EXT,
 685                 .vmode          = FB_VMODE_NONINTERLACED
 686 } }, {
 687         .bus    = 0,
 688         .addr   = 0,
 689         .pixfmt = IPU_PIX_FMT_LVDS666,
 690         .detect = 0,
 691         .enable = enable_lvds,
 692         .mode   = {
 693                 .name           = "wvga-lvds",
 694                 .refresh        = 57,
 695                 .xres           = 800,
 696                 .yres           = 480,
 697                 .pixclock       = 15385,
 698                 .left_margin    = 220,
 699                 .right_margin   = 40,
 700                 .upper_margin   = 21,
 701                 .lower_margin   = 7,
 702                 .hsync_len      = 60,
 703                 .vsync_len      = 10,
 704                 .sync           = FB_SYNC_EXT,
 705                 .vmode          = FB_VMODE_NONINTERLACED
 706 } }, {
 707         .bus    = 2,
 708         .addr   = 0x48,
 709         .pixfmt = IPU_PIX_FMT_RGB666,
 710         .detect = detect_i2c,
 711         .enable = enable_rgb,
 712         .mode   = {
 713                 .name           = "wvga-rgb",
 714                 .refresh        = 57,
 715                 .xres           = 800,
 716                 .yres           = 480,
 717                 .pixclock       = 37037,
 718                 .left_margin    = 40,
 719                 .right_margin   = 60,
 720                 .upper_margin   = 10,
 721                 .lower_margin   = 10,
 722                 .hsync_len      = 20,
 723                 .vsync_len      = 10,
 724                 .sync           = 0,
 725                 .vmode          = FB_VMODE_NONINTERLACED
 726 } }, {
 727         .bus    = 0,
 728         .addr   = 0,
 729         .pixfmt = IPU_PIX_FMT_RGB24,
 730         .detect = NULL,
 731         .enable = enable_rgb,
 732         .mode   = {
 733                 .name           = "qvga",
 734                 .refresh        = 60,
 735                 .xres           = 320,
 736                 .yres           = 240,
 737                 .pixclock       = 37037,
 738                 .left_margin    = 38,
 739                 .right_margin   = 37,
 740                 .upper_margin   = 16,
 741                 .lower_margin   = 15,
 742                 .hsync_len      = 30,
 743                 .vsync_len      = 3,
 744                 .sync           = 0,
 745                 .vmode          = FB_VMODE_NONINTERLACED
 746 } } };
 747 size_t display_count = ARRAY_SIZE(displays);
 748
 749 int board_cfb_skip(void)
 750 {
 751         return NULL != env_get("novideo");
 752 }
 753
 754 static void setup_display(void)
 755 {
 756         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 757         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 758         int reg;
 759
 760         enable_ipu_clock();
 761         imx_setup_hdmi();
 762         /* Turn on LDB0,IPU,IPU DI0 clocks */
 763         reg = __raw_readl(&mxc_ccm->CCGR3);
 764         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 765         writel(reg, &mxc_ccm->CCGR3);
 766
 767         /* set LDB0, LDB1 clk select to 011/011 */
 768         reg = readl(&mxc_ccm->cs2cdr);
 769         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 770                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 771         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 772               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 773         writel(reg, &mxc_ccm->cs2cdr);
 774
 775         reg = readl(&mxc_ccm->cscmr2);
 776         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 777         writel(reg, &mxc_ccm->cscmr2);
 778
 779         reg = readl(&mxc_ccm->chsccdr);
 780         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 781                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 782         writel(reg, &mxc_ccm->chsccdr);
 783
 784         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 785              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 786              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 787              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 788              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 789              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 790              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 791              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 792              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 793         writel(reg, &iomux->gpr[2]);
 794
 795         reg = readl(&iomux->gpr[3]);
 796         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 797                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 798             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 799                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 800         writel(reg, &iomux->gpr[3]);
 801
 802         /* backlights off until needed */
 803         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 804                                          ARRAY_SIZE(backlight_pads));
 805         gpio_direction_input(LVDS_BACKLIGHT_GP);
 806         gpio_direction_input(RGB_BACKLIGHT_GP);
 807 }
 808 #endif
 809
 810 static iomux_v3_cfg_t const init_pads[] = {
 811         /* SGTL5000 sys_mclk */
 812         NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 813
 814         /* J5 - Camera MCLK */
 815         NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 816
 817         /* wl1271 pads on nitrogen6x */
 818         /* WL12XX_WL_IRQ_GP */
 819         NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 820         /* WL12XX_WL_ENABLE_GP */
 821         NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 822         /* WL12XX_BT_ENABLE_GP */
 823         NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 824         /* USB otg power */
 825         NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 826         NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 827         NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 828         NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 829         NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 830 };
 831
 832 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 833
 834 static unsigned gpios_out_low[] = {
 835         /* Disable wl1271 */
 836         IMX_GPIO_NR(6, 15),     /* disable wireless */
 837         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 838         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 839         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 840         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 841 };
 842
 843 static unsigned gpios_out_high[] = {
 844         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 845         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 846 };
 847
 848 static void set_gpios(unsigned *p, int cnt, int val)
 849 {
 850         int i;
 851
 852         for (i = 0; i < cnt; i++)
 853                 gpio_direction_output(*p++, val);
 854 }
 855
 856 int board_early_init_f(void)
 857 {
 858         setup_iomux_uart();
 859
 860         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 861         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 862         gpio_direction_input(WL12XX_WL_IRQ_GP);
 863
 864         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 865         imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
 866         setup_buttons();
 867
 868 #if defined(CONFIG_VIDEO_IPUV3)
 869         setup_display();
 870 #endif
 871         return 0;
 872 }
 873
 874 /*
 875  * Do not overwrite the console
 876  * Use always serial for U-Boot console
 877  */
 878 int overwrite_console(void)
 879 {
 880         return 1;
 881 }
 882
 883 int board_init(void)
 884 {
 885         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 886
 887         clrsetbits_le32(&iomuxc_regs->gpr[1],
 888                         IOMUXC_GPR1_OTG_ID_MASK,
 889                         IOMUXC_GPR1_OTG_ID_GPIO1);
 890
 891         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 892
 893         /* address of boot parameters */
 894         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 895
 896 #ifdef CONFIG_MXC_SPI
 897         setup_spi();
 898 #endif
 899         imx_iomux_v3_setup_multiple_pads(
 900                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 901         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 902         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 903         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 904
 905 #ifdef CONFIG_SATA
 906         setup_sata();
 907 #endif
 908
 909         return 0;
 910 }
 911
 912 int checkboard(void)
 913 {
 914         if (gpio_get_value(WL12XX_WL_IRQ_GP))
 915                 puts("Board: Nitrogen6X\n");
 916         else
 917                 puts("Board: SABRE Lite\n");
 918
 919         return 0;
 920 }
 921
 922 struct button_key {
 923         char const      *name;
 924         unsigned        gpnum;
 925         char            ident;
 926 };
 927
 928 static struct button_key const buttons[] = {
 929         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 930         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 931         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 932         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 933         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 934         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 935 };
 936
 937 /*
 938  * generate a null-terminated string containing the buttons pressed
 939  * returns number of keys pressed
 940  */
 941 static int read_keys(char *buf)
 942 {
 943         int i, numpressed = 0;
 944         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 945                 if (!gpio_get_value(buttons[i].gpnum))
 946                         buf[numpressed++] = buttons[i].ident;
 947         }
 948         buf[numpressed] = '\0';
 949         return numpressed;
 950 }
 951
 952 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 953 {
 954         char envvalue[ARRAY_SIZE(buttons)+1];
 955         int numpressed = read_keys(envvalue);
 956         env_set("keybd", envvalue);
 957         return numpressed == 0;
 958 }
 959
 960 U_BOOT_CMD(
 961         kbd, 1, 1, do_kbd,
 962         "Tests for keypresses, sets 'keybd' environment variable",
 963         "Returns 0 (true) to shell if key is pressed."
 964 );
 965
 966 #ifdef CONFIG_PREBOOT
 967 static char const kbd_magic_prefix[] = "key_magic";
 968 static char const kbd_command_prefix[] = "key_cmd";
 969
 970 static void preboot_keys(void)
 971 {
 972         int numpressed;
 973         char keypress[ARRAY_SIZE(buttons)+1];
 974         numpressed = read_keys(keypress);
 975         if (numpressed) {
 976                 char *kbd_magic_keys = env_get("magic_keys");
 977                 char *suffix;
 978                 /*
 979                  * loop over all magic keys
 980                  */
 981                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 982                         char *keys;
 983                         char magic[sizeof(kbd_magic_prefix) + 1];
 984                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 985                         keys = env_get(magic);
 986                         if (keys) {
 987                                 if (!strcmp(keys, keypress))
 988                                         break;
 989                         }
 990                 }
 991                 if (*suffix) {
 992                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 993                         char *cmd;
 994                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 995                         cmd = env_get(cmd_name);
 996                         if (cmd) {
 997                                 env_set("preboot", cmd);
 998                                 return;
 999                         }
1000                 }
1001         }
1002 }
1003 #endif
1004
1005 #ifdef CONFIG_CMD_BMODE
1006 static const struct boot_mode board_boot_modes[] = {
1007         /* 4 bit bus width */
1008         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1009         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1010         {NULL,          0},
1011 };
1012 #endif
1013
1014 int misc_init_r(void)
1015 {
1016 #ifdef CONFIG_PREBOOT
1017         preboot_keys();
1018 #endif
1019
1020 #ifdef CONFIG_CMD_BMODE
1021         add_board_boot_modes(board_boot_modes);
1022 #endif
1023         env_set_hex("reset_cause", get_imx_reset_cause());
1024         return 0;
1025 }