board/bosch/guardian/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Bosch Guardian
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
   9  */
  10
  11 #include <common.h>
  12 #include <cpsw.h>
  13 #include <dm.h>
  14 #include <env_internal.h>
  15 #include <errno.h>
  16 #include <i2c.h>
  17 #include <init.h>
  18 #include <led.h>
  19 #include <miiphy.h>
  20 #include <panel.h>
  21 #include <power/tps65217.h>
  22 #include <power/tps65910.h>
  23 #include <spl.h>
  24 #include <watchdog.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/cpu.h>
  27 #include <asm/arch/ddr_defs.h>
  28 #include <asm/arch/gpio.h>
  29 #include <asm/arch/hardware.h>
  30 #include <asm/arch/mem.h>
  31 #include <asm/arch/mmc_host_def.h>
  32 #include <asm/arch/omap.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <asm/emif.h>
  35 #include <asm/gpio.h>
  36 #include <asm/io.h>
  37 #include "board.h"
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  42 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  43
  44 static const struct ddr_data ddr3_data = {
  45         .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  46         .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  47         .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  48         .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  49 };
  50
  51 static const struct cmd_control ddr3_cmd_ctrl_data = {
  52         .cmd0csratio = MT41K128M16JT125K_RATIO,
  53         .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  54
  55         .cmd1csratio = MT41K128M16JT125K_RATIO,
  56         .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  57
  58         .cmd2csratio = MT41K128M16JT125K_RATIO,
  59         .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  60 };
  61
  62 static struct emif_regs ddr3_emif_reg_data = {
  63         .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  64         .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  65         .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  66         .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  67         .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  68         .zq_config = MT41K128M16JT125K_ZQ_CFG,
  69         .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  70 };
  71
  72 #define OSC     (V_OSCK / 1000000)
  73 const struct dpll_params dpll_ddr = {
  74                 400, OSC - 1, 1, -1, -1, -1, -1};
  75
  76 void am33xx_spl_board_init(void)
  77 {
  78         int mpu_vdd;
  79         int usb_cur_lim;
  80
  81         /* Get the frequency */
  82         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  83
  84         if (i2c_probe(TPS65217_CHIP_PM))
  85                 return;
  86
  87         /*
  88          * Increase USB current limit to 1300mA or 1800mA and set
  89          * the MPU voltage controller as needed.
  90          */
  91         if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  92                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  93                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  94         } else {
  95                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  96                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  97         }
  98
  99         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 100                                TPS65217_POWER_PATH,
 101                                usb_cur_lim,
 102                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 103                 puts("tps65217_reg_write failure\n");
 104
 105         /* Set DCDC3 (CORE) voltage to 1.125V */
 106         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 107                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 108                 puts("tps65217_voltage_update failure\n");
 109                 return;
 110         }
 111
 112         /* Set CORE Frequencies to OPP100 */
 113         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 114
 115         /* Set DCDC2 (MPU) voltage */
 116         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 117                 puts("tps65217_voltage_update failure\n");
 118                 return;
 119         }
 120
 121         /*
 122          * Set LDO3 to 1.8V and LDO4 to 3.3V
 123          */
 124         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 125                                TPS65217_DEFLS1,
 126                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 127                                TPS65217_LDO_MASK))
 128                 puts("tps65217_reg_write failure\n");
 129
 130         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 131                                TPS65217_DEFLS2,
 132                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 133                                TPS65217_LDO_MASK))
 134                 puts("tps65217_reg_write failure\n");
 135
 136         /* Set MPU Frequency to what we detected now that voltages are set */
 137         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 138 }
 139
 140 const struct dpll_params *get_dpll_ddr_params(void)
 141 {
 142         enable_i2c0_pin_mux();
 143         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 144
 145         return &dpll_ddr;
 146 }
 147
 148 void set_uart_mux_conf(void)
 149 {
 150         enable_uart0_pin_mux();
 151 }
 152
 153 void set_mux_conf_regs(void)
 154 {
 155         enable_board_pin_mux();
 156 }
 157
 158 const struct ctrl_ioregs ioregs = {
 159         .cm0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 160         .cm1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 161         .cm2ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 162         .dt0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 163         .dt1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 164 };
 165
 166 void sdram_init(void)
 167 {
 168         config_ddr(400, &ioregs,
 169                    &ddr3_data,
 170                    &ddr3_cmd_ctrl_data,
 171                    &ddr3_emif_reg_data, 0);
 172 }
 173 #endif
 174
 175 int board_init(void)
 176 {
 177         save_omap_boot_params();
 178
 179 #if defined(CONFIG_HW_WATCHDOG)
 180         hw_watchdog_init();
 181 #endif
 182
 183         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 184
 185 #ifdef CONFIG_MTD_RAW_NAND
 186         gpmc_init();
 187 #endif
 188         return 0;
 189 }
 190
 191 #ifdef CONFIG_BOARD_LATE_INIT
 192 static void set_bootmode_env(void)
 193 {
 194         char *boot_device_name = NULL;
 195         char *boot_mode_gpio = "gpio@44e07000_14";
 196         int   ret;
 197         int   value;
 198
 199         struct gpio_desc boot_mode_desc;
 200
 201         switch (gd->arch.omap_boot_device) {
 202         case BOOT_DEVICE_NAND:
 203                 boot_device_name = "nand";
 204                 break;
 205         case BOOT_DEVICE_USBETH:
 206                 boot_device_name = "usbeth";
 207                 break;
 208         default:
 209                 break;
 210         }
 211
 212         if (boot_device_name)
 213                 env_set("boot_device", boot_device_name);
 214
 215         ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
 216         if (ret) {
 217                 printf("%s is not found\n", boot_mode_gpio);
 218                 goto err;
 219         }
 220
 221         ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
 222         if (ret && ret != -EBUSY) {
 223                 printf("requesting gpio: %s failed\n", boot_mode_gpio);
 224                 goto err;
 225         }
 226
 227         value = dm_gpio_get_value(&boot_mode_desc);
 228         value ? env_set("swi_status", "0") : env_set("swi_status", "1");
 229         return;
 230
 231 err:
 232         env_set("swi_status", "err");
 233 }
 234
 235 int board_late_init(void)
 236 {
 237 #ifdef CONFIG_LED_GPIO
 238         led_default_state();
 239 #endif
 240         set_bootmode_env();
 241         return 0;
 242 }
 243 #endif /* CONFIG_BOARD_LATE_INIT */