2 * video.c - run splash screen on lcd
4 * Copyright (c) 2007-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
13 #include <asm/blackfin.h>
14 #include <asm/mach-common/bits/dma.h>
16 #include <linux/types.h>
17 #include <stdio_dev.h>
21 #include <asm/mach-common/bits/ppi.h>
22 #include <asm/mach-common/bits/timer.h>
24 #include <asm/bfin_logo_230x230.h>
26 #define LCD_X_RES 320 /* Horizontal Resolution */
27 #define LCD_Y_RES 240 /* Vertical Resolution */
28 #define LCD_BPP 24 /* Bit Per Pixel */
29 #define LCD_PIXEL_SIZE (LCD_BPP / 8)
31 #define DMA_BUS_SIZE 16
32 #define LCD_CLK (12*1000*1000) /* 12MHz */
34 #define CLOCKS_PER_PIX 3
36 /* HS and VS timing parameters (all in number of PPI clk ticks) */
37 #define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
38 #define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
39 #define H_PULSE 90 /* HS pulse width */
40 #define H_START 204 /* first valid pixel */
42 #define U_LINE 1 /* Blanking Lines */
44 #define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
45 #define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
46 #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
48 #define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
50 #define PPI_TX_MODE 0x2
51 #define PPI_XFER_TYPE_11 0xC
52 #define PPI_PORT_CFG_01 0x10
53 #define PPI_PACK_EN 0x80
54 #define PPI_POLS_1 0x8000
56 /* enable and disable PPI functions */
59 *pPPI_CONTROL |= PORT_EN;
64 *pPPI_CONTROL &= ~PORT_EN;
69 *pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
70 *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
71 *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
73 *pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
74 *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
81 *pPPI_DELAY = H_START;
82 *pPPI_COUNT = (H_ACTPIX-1);
85 /* PPI control, to be replaced with definitions */
86 *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
87 PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
88 PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
89 PPI_PACK_EN | /* packing enabled PACK_EN */
90 PPI_POLS_1; /* faling edge syncs POLS */
93 void Init_DMA(void *dst)
95 *pDMA0_START_ADDR = dst;
98 *pDMA0_X_COUNT = H_ACTPIX / 2;
99 *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
102 *pDMA0_Y_COUNT = V_LINES;
103 *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
107 WDSIZE_16 | /* 16 bit DMA */
109 FLOW_AUTO; /* autobuffer mode */
115 *pDMA0_CONFIG |= DMAEN;
118 void DisableDMA(void)
120 *pDMA0_CONFIG &= ~DMAEN;
124 /* Init TIMER0 as Frame Sync 1 generator */
125 void InitTIMER0(void)
127 *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
129 *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
132 *pTIMER0_PERIOD = H_PERIOD;
134 *pTIMER0_WIDTH = H_PULSE;
137 *pTIMER0_CONFIG = PWM_OUT |
145 void EnableTIMER0(void)
147 *pTIMER_ENABLE |= TIMEN0;
151 void DisableTIMER0(void)
153 *pTIMER_DISABLE |= TIMDIS0;
158 void InitTIMER1(void)
160 *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
162 *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
166 *pTIMER1_PERIOD = V_PERIOD;
168 *pTIMER1_WIDTH = V_PULSE;
171 *pTIMER1_CONFIG = PWM_OUT |
179 void EnableTIMER1(void)
181 *pTIMER_ENABLE |= TIMEN1;
185 void DisableTIMER1(void)
187 *pTIMER_DISABLE |= TIMDIS1;
191 int video_init(void *dst)
202 /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
204 /* Add Some Delay ... */
210 /* now start frame sync 1 */
216 static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
219 blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
221 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
223 /* Setup destination start address */
224 bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
225 + (y * LCD_X_RES * LCD_PIXEL_SIZE));
226 /* Setup destination xcount */
227 bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
228 /* Setup destination xmodify */
229 bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
231 /* Setup destination ycount */
232 bfin_write_MDMA_D0_Y_COUNT(logo->height);
233 /* Setup destination ymodify */
234 bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
237 /* Setup Source start address */
238 bfin_write_MDMA_S0_START_ADDR(logo->data);
239 /* Setup Source xcount */
240 bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
241 /* Setup Source xmodify */
242 bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
244 /* Setup Source ycount */
245 bfin_write_MDMA_S0_Y_COUNT(logo->height);
246 /* Setup Source ymodify */
247 bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
250 /* Enable source DMA */
251 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
253 bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
255 while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
257 bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
258 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
262 void video_putc(const char c)
266 void video_puts(const char *s)
270 int drv_video_init(void)
272 int error, devices = 1;
273 struct stdio_dev videodev;
276 u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
278 dst = malloc(fbmem_size);
281 printf("Failed to alloc FB memory\n");
285 #ifdef EASYLOGO_ENABLE_GZIP
286 unsigned char *data = EASYLOGO_DECOMP_BUFFER;
287 unsigned long src_len = EASYLOGO_ENABLE_GZIP;
288 if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
289 puts("Failed to decompress logo\n");
293 bfin_logo.data = data;
296 memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
298 dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
299 (LCD_X_RES - bfin_logo.width) / 2,
300 (LCD_Y_RES - bfin_logo.height) / 2);
302 video_init(dst); /* Video initialization */
304 memset(&videodev, 0, sizeof(videodev));
306 strcpy(videodev.name, "video");
307 videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
308 videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
309 videodev.putc = video_putc; /* 'putc' function */
310 videodev.puts = video_puts; /* 'puts' function */
312 error = stdio_register(&videodev);
314 return (error == 0) ? devices : error;