1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
6 * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/iomux-mx53.h>
15 #include <asm/mach-imx/mx5_video.h>
20 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
21 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
22 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
23 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
24 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
25 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
26 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
27 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
28 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
29 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
30 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
31 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
32 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
33 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
34 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
37 #define CCAT_BASE_ADDR ((void *)0xf0000000)
38 #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
39 #define CCAT_SIZE 1191788
40 #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
41 static const char CCAT_SIGNATURE[] = "CCAT";
43 static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
44 static const u32 CCAT_MODE_RUN = 0x0033DC8F;
46 DECLARE_GLOBAL_DATA_PTR;
48 u32 get_board_rev(void)
50 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
51 struct fuse_bank *bank = &iim->bank[0];
52 struct fuse_bank0_regs *fuse =
53 (struct fuse_bank0_regs *)bank->fuse_regs;
55 int rev = readl(&fuse->gp[6]);
57 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
62 * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
64 void weim_cs0_settings(u32 mode)
66 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
68 writel(0x0, &weim_regs->cs0gcr1);
69 writel(mode, &weim_regs->cs0gcr1);
70 writel(0x00001002, &weim_regs->cs0gcr2);
72 writel(0x04000000, &weim_regs->cs0rcr1);
73 writel(0x00000000, &weim_regs->cs0rcr2);
75 writel(0x04000000, &weim_regs->cs0wcr1);
76 writel(0x00000000, &weim_regs->cs0wcr2);
79 static void setup_gpio_eim(void)
81 gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
82 gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
83 gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
84 gpio_direction_input(GPIO_C3_STATUS);
85 gpio_direction_input(GPIO_C3_DONE);
86 gpio_direction_output(GPIO_C3_CONFIG, 1);
88 weim_cs0_settings(CCAT_MODE_RUN);
91 static void setup_gpio_sups(void)
93 gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
94 gpio_direction_input(GPIO_SUPS_INT);
96 static const int BLINK_INTERVALL = 50000;
98 while (gpio_get_value(GPIO_SUPS_INT)) {
99 /* signal "CX SUPS power fail" */
100 gpio_set_value(GPIO_LED_PWR_R,
101 (++status / BLINK_INTERVALL) % 2);
104 /* signal "CX power up" */
105 gpio_set_value(GPIO_LED_PWR_R, 1);
108 static void setup_gpio_leds(void)
110 gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
111 gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
112 gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
113 gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
114 gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
115 gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
116 gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
117 gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
118 gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
120 gpio_direction_output(GPIO_LED_SD2_R, 0);
121 gpio_direction_output(GPIO_LED_SD2_B, 0);
122 gpio_direction_output(GPIO_LED_SD2_G, 0);
123 gpio_direction_output(GPIO_LED_SD1_R, 0);
124 gpio_direction_output(GPIO_LED_SD1_B, 0);
125 gpio_direction_output(GPIO_LED_SD1_G, 0);
126 gpio_direction_output(GPIO_LED_PWR_R, 0);
127 gpio_direction_output(GPIO_LED_PWR_B, 0);
128 gpio_direction_output(GPIO_LED_PWR_G, 0);
131 #ifdef CONFIG_USB_EHCI_MX5
132 int board_ehci_hcd_init(int port)
134 /* request VBUS power enable pin, GPIO7_8 */
135 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
141 static int power_init(void)
143 /* nothing to do on CX9020 */
147 static void clock_1GHz(void)
150 u32 ref_clk = MXC_HCLK;
152 * After increasing voltage to 1.25V, we can switch
153 * CPU clock to 1GHz and DDR to 400MHz safely
155 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
157 printf("CPU: Switch CPU clock to 1GHZ failed\n");
159 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
160 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
162 printf("CPU: Switch DDR clock to 400MHz failed\n");
165 int board_early_init_f(void)
173 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
175 mxc_set_sata_internal_clock();
187 puts("Board: Beckhoff CX9020\n");
192 static int ccat_config_fn(int assert_config, int flush, int cookie)
194 /* prepare FPGA for programming */
195 weim_cs0_settings(CCAT_MODE_CONFIG);
196 gpio_set_value(GPIO_C3_CONFIG, 0);
198 gpio_set_value(GPIO_C3_CONFIG, 1);
204 static int ccat_status_fn(int cookie)
209 static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
211 const uint8_t *const buffer = buf;
215 for (i = 0; i < buf_len; ++i)
216 writeb(buffer[i], CCAT_BASE_ADDR);
218 writeb(0xff, CCAT_BASE_ADDR);
219 writeb(0xff, CCAT_BASE_ADDR);
224 static int ccat_done_fn(int cookie)
226 /* programming complete? */
227 return gpio_get_value(GPIO_C3_DONE);
230 static int ccat_post_fn(int cookie)
232 /* switch to FPGA run mode */
233 weim_cs0_settings(CCAT_MODE_RUN);
234 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
236 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
237 printf("Verifing CCAT firmware failed, signature not found\n");
241 /* signal "CX booting OS" */
242 gpio_set_value(GPIO_LED_PWR_R, 1);
243 gpio_set_value(GPIO_LED_PWR_G, 1);
244 gpio_set_value(GPIO_LED_PWR_B, 0);
248 static Altera_CYC2_Passive_Serial_fns ccat_fns = {
249 .config = ccat_config_fn,
250 .status = ccat_status_fn,
251 .done = ccat_done_fn,
252 .write = ccat_write_fn,
253 .abort = ccat_post_fn,
254 .post = ccat_post_fn,
257 static Altera_desc ccat_fpga = {
258 .family = Altera_CYC2,
259 .iface = passive_serial,
261 .iface_fns = &ccat_fns,
262 .base = CCAT_BASE_ADDR,
265 int board_late_init(void)
271 fpga_add(fpga_altera, &ccat_fpga);