board/atmel/sama5d4_xplained/sama5d4_xplained.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Atmel
   4  *                    Bo Shen <voice.shen@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <asm/global_data.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91_common.h>
  12 #include <asm/arch/at91_rstc.h>
  13 #include <asm/arch/atmel_mpddrc.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/arch/clk.h>
  16 #include <asm/arch/sama5d3_smc.h>
  17 #include <asm/arch/sama5d4.h>
  18 #include <debug_uart.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 extern void at91_pda_detect(void);
  23
  24 #ifdef CONFIG_NAND_ATMEL
  25 static void sama5d4_xplained_nand_hw_init(void)
  26 {
  27         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  28
  29         at91_periph_clk_enable(ATMEL_ID_SMC);
  30
  31         /* Configure SMC CS3 for NAND */
  32         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  33                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  34                &smc->cs[3].setup);
  35         writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  36                AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  37                &smc->cs[3].pulse);
  38         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  39                &smc->cs[3].cycle);
  40         writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  41                AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  42                AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  43                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  44         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  45                AT91_SMC_MODE_EXNW_DISABLE |
  46                AT91_SMC_MODE_DBW_8 |
  47                AT91_SMC_MODE_TDF_CYCLE(3),
  48                &smc->cs[3].mode);
  49
  50         at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);   /* D0 */
  51         at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);   /* D1 */
  52         at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);   /* D2 */
  53         at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);   /* D3 */
  54         at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);   /* D4 */
  55         at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);  /* D5 */
  56         at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);  /* D6 */
  57         at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);  /* D7 */
  58         at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);  /* RE */
  59         at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);  /* WE */
  60         at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);  /* NCS */
  61         at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);  /* RDY */
  62         at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);  /* ALE */
  63         at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);  /* CLE */
  64 }
  65 #endif
  66
  67 #ifdef CONFIG_CMD_USB
  68 static void sama5d4_xplained_usb_hw_init(void)
  69 {
  70         at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
  71         at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_BOARD_LATE_INIT
  76 int board_late_init(void)
  77 {
  78         at91_pda_detect();
  79 #ifdef CONFIG_VIDEO
  80         at91_video_show_board_info();
  81 #endif
  82         return 0;
  83 }
  84 #endif
  85
  86 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  87 static void sama5d4_xplained_serial3_hw_init(void)
  88 {
  89         at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);  /* TXD3 */
  90         at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);  /* RXD3 */
  91
  92         /* Enable clock */
  93         at91_periph_clk_enable(ATMEL_ID_USART3);
  94 }
  95
  96 void board_debug_uart_init(void)
  97 {
  98         sama5d4_xplained_serial3_hw_init();
  99 }
 100 #endif
 101
 102 #ifdef CONFIG_BOARD_EARLY_INIT_F
 103 int board_early_init_f(void)
 104 {
 105         return 0;
 106 }
 107 #endif
 108
 109 #define AT24MAC_MAC_OFFSET      0x9a
 110
 111 #ifdef CONFIG_MISC_INIT_R
 112 int misc_init_r(void)
 113 {
 114 #ifdef CONFIG_I2C_EEPROM
 115         at91_set_ethaddr(AT24MAC_MAC_OFFSET);
 116 #endif
 117         return 0;
 118 }
 119 #endif
 120
 121 int board_init(void)
 122 {
 123         /* adress of boot parameters */
 124         gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 125
 126 #ifdef CONFIG_NAND_ATMEL
 127         sama5d4_xplained_nand_hw_init();
 128 #endif
 129 #ifdef CONFIG_CMD_USB
 130         sama5d4_xplained_usb_hw_init();
 131 #endif
 132
 133         return 0;
 134 }
 135
 136 int dram_init(void)
 137 {
 138         gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
 139                                     CFG_SYS_SDRAM_SIZE);
 140         return 0;
 141 }
 142
 143 /* SPL */
 144 #ifdef CONFIG_SPL_BUILD
 145 void spl_board_init(void)
 146 {
 147 #if CONFIG_NAND_BOOT
 148         sama5d4_xplained_nand_hw_init();
 149 #endif
 150 }
 151
 152 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 153 {
 154         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 155
 156         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 157                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 158                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 159                     ATMEL_MPDDRC_CR_NB_8BANKS |
 160                     ATMEL_MPDDRC_CR_NDQS_DISABLED |
 161                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 162                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 163
 164         ddr2->rtr = 0x2b0;
 165
 166         ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 167                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 168                       3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 169                       10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 170                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 171                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 172                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 173                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 174
 175         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 176                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 177                       25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 178                       23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 179
 180         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 181                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 182                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 183                       2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 184                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 185 }
 186
 187 void mem_init(void)
 188 {
 189         struct atmel_mpddrc_config ddr2;
 190
 191         ddr2_conf(&ddr2);
 192
 193         /* Enable MPDDR clock */
 194         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 195         at91_system_clk_enable(AT91_PMC_DDR);
 196
 197         /* DDRAM2 Controller initialize */
 198         ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 199 }
 200
 201 void at91_pmc_init(void)
 202 {
 203         u32 tmp;
 204
 205         tmp = AT91_PMC_PLLAR_29 |
 206               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 207               AT91_PMC_PLLXR_MUL(87) |
 208               AT91_PMC_PLLXR_DIV(1);
 209         at91_plla_init(tmp);
 210
 211         at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
 212
 213         tmp = AT91_PMC_MCKR_H32MXDIV |
 214               AT91_PMC_MCKR_PLLADIV_2 |
 215               AT91_PMC_MCKR_MDIV_3 |
 216               AT91_PMC_MCKR_CSS_PLLA;
 217         at91_mck_init(tmp);
 218 }
 219 #endif