board/atmel/sama5d3_xplained/sama5d3_xplained.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Atmel Corporation
   4  *                    Bo Shen <voice.shen@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <asm/global_data.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/sama5d3_smc.h>
  12 #include <asm/arch/at91_common.h>
  13 #include <asm/arch/at91_rstc.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/arch/clk.h>
  16 #include <debug_uart.h>
  17 #include <spl.h>
  18 #include <asm/arch/atmel_mpddrc.h>
  19 #include <asm/arch/at91_wdt.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 extern void at91_pda_detect(void);
  24
  25 #ifdef CONFIG_NAND_ATMEL
  26 void sama5d3_xplained_nand_hw_init(void)
  27 {
  28         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  29
  30         at91_periph_clk_enable(ATMEL_ID_SMC);
  31
  32         /* Configure SMC CS3 for NAND/SmartMedia */
  33         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  34                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  35                &smc->cs[3].setup);
  36         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  37                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  38                &smc->cs[3].pulse);
  39         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  40                &smc->cs[3].cycle);
  41         writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  42                AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
  43                AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  44                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  45         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  46                AT91_SMC_MODE_EXNW_DISABLE |
  47 #ifdef CONFIG_SYS_NAND_DBW_16
  48                AT91_SMC_MODE_DBW_16 |
  49 #else /* CONFIG_SYS_NAND_DBW_8 */
  50                AT91_SMC_MODE_DBW_8 |
  51 #endif
  52                AT91_SMC_MODE_TDF_CYCLE(3),
  53                &smc->cs[3].mode);
  54 }
  55 #endif
  56
  57 #ifdef CONFIG_CMD_USB
  58 static void sama5d3_xplained_usb_hw_init(void)
  59 {
  60         at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
  61         at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
  62 }
  63 #endif
  64
  65 #ifdef CONFIG_GENERIC_ATMEL_MCI
  66 static void sama5d3_xplained_mci0_hw_init(void)
  67 {
  68         at91_set_pio_output(AT91_PIO_PORTE, 2, 0);      /* MCI0 Power */
  69 }
  70 #endif
  71
  72 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  73 void board_debug_uart_init(void)
  74 {
  75         at91_seriald_hw_init();
  76 }
  77 #endif
  78
  79 #ifdef CONFIG_BOARD_LATE_INIT
  80 int board_late_init(void)
  81 {
  82         at91_pda_detect();
  83         return 0;
  84 }
  85 #endif
  86
  87 #ifdef CONFIG_BOARD_EARLY_INIT_F
  88 int board_early_init_f(void)
  89 {
  90 #ifdef CONFIG_DEBUG_UART
  91         debug_uart_init();
  92 #endif
  93         return 0;
  94 }
  95 #endif
  96
  97 int board_init(void)
  98 {
  99         /* adress of boot parameters */
 100         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 101
 102 #ifdef CONFIG_NAND_ATMEL
 103         sama5d3_xplained_nand_hw_init();
 104 #endif
 105 #ifdef CONFIG_CMD_USB
 106         sama5d3_xplained_usb_hw_init();
 107 #endif
 108 #ifdef CONFIG_GENERIC_ATMEL_MCI
 109         sama5d3_xplained_mci0_hw_init();
 110 #endif
 111         return 0;
 112 }
 113
 114 int dram_init(void)
 115 {
 116         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 117                                     CONFIG_SYS_SDRAM_SIZE);
 118
 119         return 0;
 120 }
 121
 122 /* SPL */
 123 #ifdef CONFIG_SPL_BUILD
 124 void spl_board_init(void)
 125 {
 126 #ifdef CONFIG_SD_BOOT
 127 #ifdef CONFIG_GENERIC_ATMEL_MCI
 128         sama5d3_xplained_mci0_hw_init();
 129 #endif
 130 #elif CONFIG_NAND_BOOT
 131         sama5d3_xplained_nand_hw_init();
 132 #endif
 133 }
 134
 135 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 136 {
 137         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 138
 139         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 140                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 141                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 142                     ATMEL_MPDDRC_CR_ENRDM_ON |
 143                     ATMEL_MPDDRC_CR_NB_8BANKS |
 144                     ATMEL_MPDDRC_CR_NDQS_DISABLED |
 145                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 146                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 147         /*
 148          * As the DDR2-SDRAm device requires a refresh time is 7.8125us
 149          * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
 150          */
 151         ddr2->rtr = 0x411;
 152
 153         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 154                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 155                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 156                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 157                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 158                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 159                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 160                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 161
 162         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 163                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 164                       28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 165                       26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 166
 167         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 168                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 169                       2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 170                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 171                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 172 }
 173
 174 void mem_init(void)
 175 {
 176         struct atmel_mpddrc_config ddr2;
 177
 178         ddr2_conf(&ddr2);
 179
 180         /* Enable MPDDR clock */
 181         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 182         at91_system_clk_enable(AT91_PMC_DDR);
 183
 184         /* DDRAM2 Controller initialize */
 185         ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 186 }
 187
 188 void at91_pmc_init(void)
 189 {
 190         u32 tmp;
 191
 192         tmp = AT91_PMC_PLLAR_29 |
 193               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 194               AT91_PMC_PLLXR_MUL(43) |
 195               AT91_PMC_PLLXR_DIV(1);
 196         at91_plla_init(tmp);
 197
 198         at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
 199
 200         tmp = AT91_PMC_MCKR_MDIV_4 |
 201               AT91_PMC_MCKR_CSS_PLLA;
 202         at91_mck_init(tmp);
 203 }
 204 #endif