board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Microchip Corporation
   4  *                    Wenyou.Yang <wenyou.yang@microchip.com>
   5  */
   6
   7 #include <common.h>
   8 #include <debug_uart.h>
   9 #include <init.h>
  10 #include <asm/global_data.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/at91_common.h>
  13 #include <asm/arch/atmel_pio4.h>
  14 #include <asm/arch/atmel_mpddrc.h>
  15 #include <asm/arch/atmel_sdhci.h>
  16 #include <asm/arch/clk.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/sama5d2.h>
  19
  20 extern void at91_pda_detect(void);
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #ifdef CONFIG_CMD_USB
  25 static void board_usb_hw_init(void)
  26 {
  27         atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
  28 }
  29 #endif
  30
  31 #ifdef CONFIG_BOARD_LATE_INIT
  32 int board_late_init(void)
  33 {
  34 #ifdef CONFIG_DM_VIDEO
  35         at91_video_show_board_info();
  36 #endif
  37         at91_pda_detect();
  38         return 0;
  39 }
  40 #endif
  41
  42 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  43 static void board_uart1_hw_init(void)
  44 {
  45         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);        /* URXD1 */
  46         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);  /* UTXD1 */
  47
  48         at91_periph_clk_enable(ATMEL_ID_UART1);
  49 }
  50
  51 void board_debug_uart_init(void)
  52 {
  53         board_uart1_hw_init();
  54 }
  55 #endif
  56
  57 #ifdef CONFIG_BOARD_EARLY_INIT_F
  58 int board_early_init_f(void)
  59 {
  60 #ifdef CONFIG_DEBUG_UART
  61         debug_uart_init();
  62 #endif
  63
  64         return 0;
  65 }
  66 #endif
  67
  68 int board_init(void)
  69 {
  70         /* address of boot parameters */
  71         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  72
  73 #ifdef CONFIG_CMD_USB
  74         board_usb_hw_init();
  75 #endif
  76
  77         return 0;
  78 }
  79
  80 int dram_init(void)
  81 {
  82         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  83                                     CONFIG_SYS_SDRAM_SIZE);
  84         return 0;
  85 }
  86
  87 #define MAC24AA_MAC_OFFSET      0xfa
  88
  89 #ifdef CONFIG_MISC_INIT_R
  90 int misc_init_r(void)
  91 {
  92 #ifdef CONFIG_I2C_EEPROM
  93         at91_set_ethaddr(MAC24AA_MAC_OFFSET);
  94 #endif
  95         return 0;
  96 }
  97 #endif
  98
  99 /* SPL */
 100 #ifdef CONFIG_SPL_BUILD
 101 void spl_board_init(void)
 102 {
 103 }
 104
 105 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
 106 {
 107         ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 108
 109         ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 110                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 111                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 112                     ATMEL_MPDDRC_CR_DIC_DS |
 113                     ATMEL_MPDDRC_CR_ZQ_LONG |
 114                     ATMEL_MPDDRC_CR_NB_8BANKS |
 115                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 116                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 117
 118         ddrc->rtr = 0x511;
 119
 120         ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
 121                       (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
 122                       (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
 123                       (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
 124                       (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
 125                       (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
 126                       (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
 127                       (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
 128
 129         ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
 130                       (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
 131                       (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
 132                       (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
 133
 134         ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
 135                       (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
 136                       (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
 137                       (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
 138                       (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
 139 }
 140
 141 void mem_init(void)
 142 {
 143         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 144         struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 145         struct atmel_mpddrc_config ddrc_config;
 146         u32 reg;
 147
 148         ddrc_conf(&ddrc_config);
 149
 150         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 151         writel(AT91_PMC_DDR, &pmc->scer);
 152
 153         reg = readl(&mpddrc->io_calibr);
 154         reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
 155         reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
 156         reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
 157         reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
 158         writel(reg, &mpddrc->io_calibr);
 159
 160         writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
 161                &mpddrc->rd_data_path);
 162
 163         ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
 164
 165         writel(0x3, &mpddrc->cal_mr4);
 166         writel(64, &mpddrc->tim_cal);
 167 }
 168
 169 void at91_pmc_init(void)
 170 {
 171         u32 tmp;
 172
 173         /*
 174          * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
 175          * so we need to slow down and configure MCKR accordingly.
 176          * This is why we have a special flavor of the switching function.
 177          */
 178         tmp = AT91_PMC_MCKR_PLLADIV_2 |
 179               AT91_PMC_MCKR_MDIV_3 |
 180               AT91_PMC_MCKR_CSS_MAIN;
 181         at91_mck_init_down(tmp);
 182
 183         tmp = AT91_PMC_PLLAR_29 |
 184               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 185               AT91_PMC_PLLXR_MUL(40) |
 186               AT91_PMC_PLLXR_DIV(1);
 187         at91_plla_init(tmp);
 188
 189         tmp = AT91_PMC_MCKR_H32MXDIV |
 190               AT91_PMC_MCKR_PLLADIV_2 |
 191               AT91_PMC_MCKR_MDIV_3 |
 192               AT91_PMC_MCKR_CSS_PLLA;
 193         at91_mck_init(tmp);
 194 }
 195 #endif