1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
5 * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
11 #include <asm/arch/at91sam9_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/at91_sfr.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/gpio.h>
17 #include <debug_uart.h>
18 #include <asm/mach-types.h>
20 extern void at91_pda_detect(void);
22 DECLARE_GLOBAL_DATA_PTR;
24 void at91_prepare_cpu_var(void);
26 #ifdef CONFIG_CMD_NAND
27 static void sam9x60ek_nand_hw_init(void)
29 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
30 struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
33 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
34 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
35 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
36 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
37 /* Enable NandFlash */
38 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
39 /* Configure RDY/BSY */
40 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
41 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
42 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
43 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
44 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
45 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
46 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
47 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
48 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
50 at91_periph_clk_enable(ATMEL_ID_PIOD);
53 csa = readl(&sfr->ebicsa);
54 csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
56 /* Configure IO drive */
57 csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
59 writel(csa, &sfr->ebicsa);
61 /* Configure SMC CS3 for NAND/SmartMedia */
62 writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
64 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
65 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
68 writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
71 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
72 #ifdef CONFIG_SYS_NAND_DBW_16
73 AT91_SMC_MODE_DBW_16 |
74 #else /* CONFIG_SYS_NAND_DBW_8 */
77 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
82 #ifdef CONFIG_BOARD_LATE_INIT
83 int board_late_init(void)
85 at91_prepare_cpu_var();
93 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
94 void board_debug_uart_init(void)
96 at91_seriald_hw_init();
100 #ifdef CONFIG_BOARD_EARLY_INIT_F
101 int board_early_init_f(void)
103 #ifdef CONFIG_DEBUG_UART
110 #define MAC24AA_MAC_OFFSET 0xfa
112 #ifdef CONFIG_MISC_INIT_R
113 int misc_init_r(void)
115 #ifdef CONFIG_I2C_EEPROM
116 at91_set_ethaddr(MAC24AA_MAC_OFFSET);
124 /* address of boot parameters */
125 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
127 #ifdef CONFIG_CMD_NAND
128 sam9x60ek_nand_hw_init();
135 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
136 CONFIG_SYS_SDRAM_SIZE);