1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Atmel Corporation
8 #include <asm/global_data.h>
10 #include <asm/arch/at91sam9x5_matrix.h>
11 #include <asm/arch/at91sam9_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/gpio.h>
16 #include <debug_uart.h>
17 #include <asm/mach-types.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 /* ------------------------------------------------------------------------- */
23 * Miscelaneous platform dependent initialisations
26 void at91_prepare_cpu_var(void);
28 #ifdef CONFIG_CMD_NAND
29 static void at91sam9x5ek_nand_hw_init(void)
31 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
32 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
36 csa = readl(&matrix->ebicsa);
37 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
38 /* NAND flash on D16 */
39 csa |= AT91_MATRIX_NFD0_ON_D16;
41 /* Configure IO drive */
42 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
44 writel(csa, &matrix->ebicsa);
46 /* Configure SMC CS3 for NAND/SmartMedia */
47 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
48 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
51 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
53 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
55 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
56 AT91_SMC_MODE_EXNW_DISABLE |
57 #ifdef CONFIG_SYS_NAND_DBW_16
58 AT91_SMC_MODE_DBW_16 |
59 #else /* CONFIG_SYS_NAND_DBW_8 */
62 AT91_SMC_MODE_TDF_CYCLE(1),
65 at91_periph_clk_enable(ATMEL_ID_PIOCD);
67 /* Configure RDY/BSY */
68 at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
69 /* Enable NandFlash */
70 at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
72 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
73 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
74 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
75 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
76 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
77 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
78 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
79 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
80 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
81 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
82 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
83 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
87 #ifdef CONFIG_BOARD_LATE_INIT
88 int board_late_init(void)
91 at91_video_show_board_info();
93 at91_prepare_cpu_var();
98 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
99 void board_debug_uart_init(void)
101 at91_seriald_hw_init();
105 #ifdef CONFIG_BOARD_EARLY_INIT_F
106 int board_early_init_f(void)
114 /* arch number of AT91SAM9X5EK-Board */
115 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
117 /* adress of boot parameters */
118 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
120 #ifdef CONFIG_CMD_NAND
121 at91sam9x5ek_nand_hw_init();
124 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
132 gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
137 #if defined(CONFIG_SPL_BUILD)
141 void at91_spl_board_init(void)
143 #ifdef CONFIG_SD_BOOT
145 #elif CONFIG_NAND_BOOT
146 at91sam9x5ek_nand_hw_init();
150 #include <asm/arch/atmel_mpddrc.h>
151 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
153 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
155 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
156 ATMEL_MPDDRC_CR_NR_ROW_13 |
157 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
158 ATMEL_MPDDRC_CR_NB_8BANKS |
159 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
163 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
164 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
165 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
166 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
167 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
168 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
169 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
170 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
172 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
173 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
174 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
175 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
177 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
178 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
179 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
180 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
181 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
186 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
187 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
188 struct atmel_mpddrc_config ddr2;
193 /* enable DDR2 clock */
194 writel(AT91_PMC_DDR, &pmc->scer);
196 /* Chip select 1 is for DDR2/SDRAM */
197 csa = readl(&matrix->ebicsa);
198 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
199 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
200 csa |= AT91_MATRIX_EBI_DBPD_OFF;
201 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
202 writel(csa, &matrix->ebicsa);
204 /* DDRAM2 Controller initialize */
205 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);