2 * Copyright (C) 2012 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/at91sam9x5_matrix.h>
26 #include <asm/arch/at91sam9_smc.h>
27 #include <asm/arch/at91_common.h>
28 #include <asm/arch/at91_pmc.h>
29 #include <asm/arch/at91_rstc.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/clk.h>
33 #include <atmel_hlcdc.h>
34 #include <atmel_mci.h>
39 #ifdef CONFIG_LCD_INFO
43 #ifdef CONFIG_ATMEL_SPI
47 DECLARE_GLOBAL_DATA_PTR;
49 /* ------------------------------------------------------------------------- */
51 * Miscelaneous platform dependent initialisations
53 #ifdef CONFIG_CMD_NAND
54 static void at91sam9x5ek_nand_hw_init(void)
56 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
57 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
58 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
62 csa = readl(&matrix->ebicsa);
63 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
64 /* NAND flash on D16 */
65 csa |= AT91_MATRIX_NFD0_ON_D16;
67 /* Configure IO drive */
68 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
70 writel(csa, &matrix->ebicsa);
72 /* Configure SMC CS3 for NAND/SmartMedia */
73 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
74 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
76 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
77 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
79 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
81 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
82 AT91_SMC_MODE_EXNW_DISABLE |
83 #ifdef CONFIG_SYS_NAND_DBW_16
84 AT91_SMC_MODE_DBW_16 |
85 #else /* CONFIG_SYS_NAND_DBW_8 */
88 AT91_SMC_MODE_TDF_CYCLE(1),
91 writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
93 /* Configure RDY/BSY */
94 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
95 /* Enable NandFlash */
96 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
98 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
99 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
100 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
101 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
102 at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
103 at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
104 at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
105 at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
106 at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
107 at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
108 at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
109 at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
113 int board_eth_init(bd_t *bis)
119 rc = macb_eth_initialize(0,
120 (void *)ATMEL_BASE_EMAC0, 0x00);
122 rc = macb_eth_initialize(1,
123 (void *)ATMEL_BASE_EMAC1, 0x00);
129 vidinfo_t panel_info = {
133 .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
138 .vl_left_margin = 64,
139 .vl_right_margin = 64,
141 .vl_upper_margin = 22,
142 .vl_lower_margin = 21,
143 .mmio = ATMEL_BASE_LCDC,
146 void lcd_enable(void)
149 at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
152 void lcd_disable(void)
155 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
158 static void at91sam9x5ek_lcd_hw_init(void)
160 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
163 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
164 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
165 at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
166 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
167 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
168 at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
170 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
171 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
172 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
173 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
174 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
175 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
176 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
177 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
178 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
179 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
180 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
181 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
182 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
183 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
184 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
185 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
186 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
187 at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
188 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
189 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
190 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
191 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
192 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
193 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
195 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
199 #ifdef CONFIG_LCD_INFO
200 void lcd_show_board_info(void)
202 ulong dram_size, nand_size;
207 lcd_printf("%s\n", U_BOOT_VERSION);
208 lcd_printf("(C) 2012 ATMEL Corp\n");
209 lcd_printf("at91support@atmel.com\n");
210 lcd_printf("%s CPU at %s MHz\n",
212 strmhz(temp, get_cpu_clk_rate()));
215 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
216 dram_size += gd->bd->bi_dram[i].size;
218 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
219 nand_size += nand_info[i].size;
220 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
225 #endif /* CONFIG_LCD_INFO */
226 #endif /* CONFIG_LCD */
228 /* SPI chip select control */
229 #ifdef CONFIG_ATMEL_SPI
230 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
232 return bus == 0 && cs < 2;
235 void spi_cs_activate(struct spi_slave *slave)
239 at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
243 at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
248 void spi_cs_deactivate(struct spi_slave *slave)
252 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
256 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
260 #endif /* CONFIG_ATMEL_SPI */
262 #ifdef CONFIG_GENERIC_ATMEL_MCI
263 int board_mmc_init(bd_t *bd)
267 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
271 int board_early_init_f(void)
273 at91_seriald_hw_init();
279 /* arch number of AT91SAM9X5EK-Board */
280 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
282 /* adress of boot parameters */
283 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
285 #ifdef CONFIG_CMD_NAND
286 at91sam9x5ek_nand_hw_init();
289 #ifdef CONFIG_ATMEL_SPI
290 at91_spi0_hw_init(1 << 0);
291 at91_spi0_hw_init(1 << 4);
299 at91sam9x5ek_lcd_hw_init();
306 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
307 CONFIG_SYS_SDRAM_SIZE);