board/atmel/at91sam9x5ek/at91sam9x5ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Atmel Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <asm/global_data.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91sam9x5_matrix.h>
  11 #include <asm/arch/at91sam9_smc.h>
  12 #include <asm/arch/at91_common.h>
  13 #include <asm/arch/at91_rstc.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/gpio.h>
  16 #include <debug_uart.h>
  17 #include <asm/mach-types.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /* ------------------------------------------------------------------------- */
  22 /*
  23  * Miscelaneous platform dependent initialisations
  24  */
  25
  26 void at91_prepare_cpu_var(void);
  27
  28 #ifdef CONFIG_CMD_NAND
  29 static void at91sam9x5ek_nand_hw_init(void)
  30 {
  31         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  32         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  33         unsigned long csa;
  34
  35         /* Enable CS3 */
  36         csa = readl(&matrix->ebicsa);
  37         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  38         /* NAND flash on D16 */
  39         csa |= AT91_MATRIX_NFD0_ON_D16;
  40
  41         /* Configure IO drive */
  42         csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  43
  44         writel(csa, &matrix->ebicsa);
  45
  46         /* Configure SMC CS3 for NAND/SmartMedia */
  47         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  48                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  49                 &smc->cs[3].setup);
  50         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  51                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  52                 &smc->cs[3].pulse);
  53         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
  54                 &smc->cs[3].cycle);
  55         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  56                 AT91_SMC_MODE_EXNW_DISABLE |
  57 #ifdef CONFIG_SYS_NAND_DBW_16
  58                 AT91_SMC_MODE_DBW_16 |
  59 #else /* CONFIG_SYS_NAND_DBW_8 */
  60                 AT91_SMC_MODE_DBW_8 |
  61 #endif
  62                 AT91_SMC_MODE_TDF_CYCLE(1),
  63                 &smc->cs[3].mode);
  64
  65         at91_periph_clk_enable(ATMEL_ID_PIOCD);
  66
  67         /* Configure RDY/BSY */
  68         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  69         /* Enable NandFlash */
  70         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  71
  72         at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);   /* NAND OE */
  73         at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);   /* NAND WE */
  74         at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);   /* NAND ALE */
  75         at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);   /* NAND CLE */
  76         at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
  77         at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
  78         at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
  79         at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
  80         at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
  81         at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
  82         at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
  83         at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
  84 }
  85 #endif
  86
  87 #ifdef CONFIG_BOARD_LATE_INIT
  88 int board_late_init(void)
  89 {
  90 #ifdef CONFIG_DM_VIDEO
  91         at91_video_show_board_info();
  92 #endif
  93         at91_prepare_cpu_var();
  94         return 0;
  95 }
  96 #endif
  97
  98 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  99 void board_debug_uart_init(void)
 100 {
 101         at91_seriald_hw_init();
 102 }
 103 #endif
 104
 105 #ifdef CONFIG_BOARD_EARLY_INIT_F
 106 int board_early_init_f(void)
 107 {
 108 #ifdef CONFIG_DEBUG_UART
 109         debug_uart_init();
 110 #endif
 111         return 0;
 112 }
 113 #endif
 114
 115 int board_init(void)
 116 {
 117         /* arch number of AT91SAM9X5EK-Board */
 118         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
 119
 120         /* adress of boot parameters */
 121         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 122
 123 #ifdef CONFIG_CMD_NAND
 124         at91sam9x5ek_nand_hw_init();
 125 #endif
 126
 127 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
 128         at91_uhp_hw_init();
 129 #endif
 130         return 0;
 131 }
 132
 133 int dram_init(void)
 134 {
 135         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
 136                                         CONFIG_SYS_SDRAM_SIZE);
 137         return 0;
 138 }
 139
 140 #if defined(CONFIG_SPL_BUILD)
 141 #include <spl.h>
 142 #include <nand.h>
 143
 144 void at91_spl_board_init(void)
 145 {
 146 #ifdef CONFIG_SD_BOOT
 147         at91_mci_hw_init();
 148 #elif CONFIG_NAND_BOOT
 149         at91sam9x5ek_nand_hw_init();
 150 #endif
 151 }
 152
 153 #include <asm/arch/atmel_mpddrc.h>
 154 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 155 {
 156         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 157
 158         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 159                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 160                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 161                     ATMEL_MPDDRC_CR_NB_8BANKS |
 162                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
 163
 164         ddr2->rtr = 0x411;
 165
 166         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 167                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 168                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 169                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 170                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 171                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 172                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 173                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 174
 175         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 176                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 177                       19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 178                       18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 179
 180         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 181                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 182                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 183                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 184                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 185 }
 186
 187 void mem_init(void)
 188 {
 189         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 190         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 191         struct atmel_mpddrc_config ddr2;
 192         unsigned long csa;
 193
 194         ddr2_conf(&ddr2);
 195
 196         /* enable DDR2 clock */
 197         writel(AT91_PMC_DDR, &pmc->scer);
 198
 199         /* Chip select 1 is for DDR2/SDRAM */
 200         csa = readl(&matrix->ebicsa);
 201         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
 202         csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
 203         csa |= AT91_MATRIX_EBI_DBPD_OFF;
 204         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 205         writel(csa, &matrix->ebicsa);
 206
 207         /* DDRAM2 Controller initialize */
 208         ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
 209 }
 210 #endif