2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91sam9rl.h>
27 #include <asm/arch/at91sam9rl_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_pmc.h>
30 #include <asm/arch/at91_rstc.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/io.h>
34 #include <atmel_lcdc.h>
35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39 DECLARE_GLOBAL_DATA_PTR;
41 /* ------------------------------------------------------------------------- */
43 * Miscelaneous platform dependent initialisations
46 static void at91sam9rlek_serial_hw_init(void)
49 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
50 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
51 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0);
55 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
56 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
57 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1);
61 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
62 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
63 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2);
66 #ifdef CONFIG_USART3 /* DBGU */
67 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
68 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
69 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
73 #ifdef CONFIG_CMD_NAND
74 static void at91sam9rlek_nand_hw_init(void)
79 csa = at91_sys_read(AT91_MATRIX_EBICSA);
80 at91_sys_write(AT91_MATRIX_EBICSA,
81 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
83 /* Configure SMC CS3 for NAND/SmartMedia */
84 at91_sys_write(AT91_SMC_SETUP(3),
85 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
86 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
87 at91_sys_write(AT91_SMC_PULSE(3),
88 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
89 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
90 at91_sys_write(AT91_SMC_CYCLE(3),
91 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
92 at91_sys_write(AT91_SMC_MODE(3),
93 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
94 AT91_SMC_EXNWMODE_DISABLE |
95 #ifdef CONFIG_SYS_NAND_DBW_16
97 #else /* CONFIG_SYS_NAND_DBW_8 */
102 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
104 /* Configure RDY/BSY */
105 at91_set_gpio_input(AT91_PIN_PD17, 1);
107 /* Enable NandFlash */
108 at91_set_gpio_output(AT91_PIN_PB6, 1);
110 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
111 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
115 #ifdef CONFIG_HAS_DATAFLASH
116 static void at91sam9rlek_spi_hw_init(void)
118 at91_set_A_periph(AT91_PIN_PA28, 0); /* SPI0_NPCS0 */
120 at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
121 at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
122 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
125 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
130 vidinfo_t panel_info = {
134 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
135 ATMEL_LCDC_INVFRAME_INVERTED,
144 mmio: AT91SAM9RL_LCDC_BASE,
147 void lcd_enable(void)
149 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
152 void lcd_disable(void)
154 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
156 static void at91sam9rlek_lcd_hw_init(void)
158 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
159 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
160 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
161 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
162 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
163 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
164 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
165 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
166 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
167 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
168 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
169 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
170 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
171 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
172 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
173 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
174 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
175 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
176 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
177 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
178 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
180 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
185 #ifdef CONFIG_LCD_INFO
189 void lcd_show_board_info(void)
191 ulong dram_size, nand_size;
195 lcd_printf ("%s\n", U_BOOT_VERSION);
196 lcd_printf ("(C) 2008 ATMEL Corp\n");
197 lcd_printf ("at91support@atmel.com\n");
198 lcd_printf ("%s CPU at %s MHz\n",
200 strmhz(temp, AT91_CPU_CLOCK));
203 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
204 dram_size += gd->bd->bi_dram[i].size;
206 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
207 nand_size += nand_info[i].size;
208 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
212 #endif /* CONFIG_LCD_INFO */
221 /* arch number of AT91SAM9RLEK-Board */
222 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
223 /* adress of boot parameters */
224 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
226 at91sam9rlek_serial_hw_init();
227 #ifdef CONFIG_CMD_NAND
228 at91sam9rlek_nand_hw_init();
230 #ifdef CONFIG_HAS_DATAFLASH
231 at91sam9rlek_spi_hw_init();
234 at91sam9rlek_lcd_hw_init();
241 gd->bd->bi_dram[0].start = PHYS_SDRAM;
242 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;