board/atmel/at91sam9rlek/at91sam9rlek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <init.h>
  11 #include <vsprintf.h>
  12 #include <asm/io.h>
  13 #include <asm/mach-types.h>
  14 #include <asm/arch/at91sam9rl.h>
  15 #include <asm/arch/at91sam9rl_matrix.h>
  16 #include <asm/arch/at91sam9_smc.h>
  17 #include <asm/arch/at91_common.h>
  18 #include <asm/arch/at91_rstc.h>
  19 #include <asm/arch/clk.h>
  20 #include <asm/arch/gpio.h>
  21
  22 #include <lcd.h>
  23 #include <atmel_lcdc.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31
  32 #ifdef CONFIG_CMD_NAND
  33 static void at91sam9rlek_nand_hw_init(void)
  34 {
  35         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  37         unsigned long csa;
  38
  39         /* Enable CS3 */
  40         csa = readl(&matrix->ebicsa);
  41         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  42
  43         writel(csa, &matrix->ebicsa);
  44
  45         /* Configure SMC CS3 for NAND/SmartMedia */
  46         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  47                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  48                 &smc->cs[3].setup);
  49         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  50                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  51                 &smc->cs[3].pulse);
  52         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  53                 &smc->cs[3].cycle);
  54         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  55                 AT91_SMC_MODE_EXNW_DISABLE |
  56 #ifdef CONFIG_SYS_NAND_DBW_16
  57                 AT91_SMC_MODE_DBW_16 |
  58 #else /* CONFIG_SYS_NAND_DBW_8 */
  59                 AT91_SMC_MODE_DBW_8 |
  60 #endif
  61                 AT91_SMC_MODE_TDF_CYCLE(2),
  62                 &smc->cs[3].mode);
  63
  64         at91_periph_clk_enable(ATMEL_ID_PIOD);
  65
  66         /* Configure RDY/BSY */
  67         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  68
  69         /* Enable NandFlash */
  70         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  71
  72         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
  73         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
  74 }
  75 #endif
  76
  77 #ifdef CONFIG_LCD
  78 vidinfo_t panel_info = {
  79         .vl_col =               240,
  80         .vl_row =               320,
  81         .vl_clk =               4965000,
  82         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
  83                                 ATMEL_LCDC_INVFRAME_INVERTED,
  84         .vl_bpix =              3,
  85         .vl_tft =               1,
  86         .vl_hsync_len =         5,
  87         .vl_left_margin =       1,
  88         .vl_right_margin =      33,
  89         .vl_vsync_len =         1,
  90         .vl_upper_margin =      1,
  91         .vl_lower_margin =      0,
  92         .mmio =                 ATMEL_BASE_LCDC,
  93 };
  94
  95 void lcd_enable(void)
  96 {
  97         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
  98 }
  99
 100 void lcd_disable(void)
 101 {
 102         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
 103 }
 104 static void at91sam9rlek_lcd_hw_init(void)
 105 {
 106         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 107         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 108         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 109         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 110         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 111         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 112         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 113         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 114         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 115         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 116         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 117         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 118         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 119         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 120         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 121         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 122         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 123         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 124         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 125         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 126         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 127
 128         at91_periph_clk_enable(ATMEL_ID_LCDC);
 129 }
 130
 131 #ifdef CONFIG_LCD_INFO
 132 #include <nand.h>
 133 #include <version.h>
 134
 135 void lcd_show_board_info(void)
 136 {
 137         ulong dram_size, nand_size;
 138         int i;
 139         char temp[32];
 140
 141         lcd_printf ("%s\n", U_BOOT_VERSION);
 142         lcd_printf ("(C) 2008 ATMEL Corp\n");
 143         lcd_printf ("at91support@atmel.com\n");
 144         lcd_printf ("%s CPU at %s MHz\n",
 145                 ATMEL_CPU_NAME,
 146                 strmhz(temp, get_cpu_clk_rate()));
 147
 148         dram_size = 0;
 149         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 150                 dram_size += gd->bd->bi_dram[i].size;
 151         nand_size = 0;
 152         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 153                 nand_size += get_nand_dev_by_index(i)->size;
 154         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 155                 dram_size >> 20,
 156                 nand_size >> 20 );
 157 }
 158 #endif /* CONFIG_LCD_INFO */
 159 #endif
 160
 161 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 162 void board_debug_uart_init(void)
 163 {
 164         at91_seriald_hw_init();
 165 }
 166 #endif
 167
 168 #ifdef CONFIG_BOARD_EARLY_INIT_F
 169 int board_early_init_f(void)
 170 {
 171 #ifdef CONFIG_DEBUG_UART
 172         debug_uart_init();
 173 #endif
 174         return 0;
 175 }
 176 #endif
 177
 178 int board_init(void)
 179 {
 180         /* arch number of AT91SAM9RLEK-Board */
 181         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 182         /* adress of boot parameters */
 183         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 184
 185 #ifdef CONFIG_CMD_NAND
 186         at91sam9rlek_nand_hw_init();
 187 #endif
 188 #ifdef CONFIG_LCD
 189         at91sam9rlek_lcd_hw_init();
 190 #endif
 191         return 0;
 192 }
 193
 194 int dram_init(void)
 195 {
 196         gd->ram_size = get_ram_size(
 197                 (void *)CONFIG_SYS_SDRAM_BASE,
 198                 CONFIG_SYS_SDRAM_SIZE);
 199         return 0;
 200 }