board/atmel/at91sam9rlek/at91sam9rlek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9rl.h>
  27 #include <asm/arch/at91sam9rl_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_common.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/at91_rstc.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/io.h>
  34 #include <lcd.h>
  35 #include <atmel_lcdc.h>
  36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  37 #include <net.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /* ------------------------------------------------------------------------- */
  43 /*
  44  * Miscelaneous platform dependent initialisations
  45  */
  46
  47 #ifdef CONFIG_CMD_NAND
  48 static void at91sam9rlek_nand_hw_init(void)
  49 {
  50         unsigned long csa;
  51
  52         /* Enable CS3 */
  53         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  54         at91_sys_write(AT91_MATRIX_EBICSA,
  55                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  56
  57         /* Configure SMC CS3 for NAND/SmartMedia */
  58         at91_sys_write(AT91_SMC_SETUP(3),
  59                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  60                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  61         at91_sys_write(AT91_SMC_PULSE(3),
  62                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  63                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  64         at91_sys_write(AT91_SMC_CYCLE(3),
  65                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  66         at91_sys_write(AT91_SMC_MODE(3),
  67                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  68                        AT91_SMC_EXNWMODE_DISABLE |
  69 #ifdef CONFIG_SYS_NAND_DBW_16
  70                        AT91_SMC_DBW_16 |
  71 #else /* CONFIG_SYS_NAND_DBW_8 */
  72                        AT91_SMC_DBW_8 |
  73 #endif
  74                        AT91_SMC_TDF_(2));
  75
  76         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
  77
  78         /* Configure RDY/BSY */
  79         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  80
  81         /* Enable NandFlash */
  82         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  83
  84         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
  85         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_LCD
  90 vidinfo_t panel_info = {
  91         vl_col:         240,
  92         vl_row:         320,
  93         vl_clk:         4965000,
  94         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
  95                         ATMEL_LCDC_INVFRAME_INVERTED,
  96         vl_bpix:        3,
  97         vl_tft:         1,
  98         vl_hsync_len:   5,
  99         vl_left_margin: 1,
 100         vl_right_margin:33,
 101         vl_vsync_len:   1,
 102         vl_upper_margin:1,
 103         vl_lower_margin:0,
 104         mmio:           AT91SAM9RL_LCDC_BASE,
 105 };
 106
 107 void lcd_enable(void)
 108 {
 109         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
 110 }
 111
 112 void lcd_disable(void)
 113 {
 114         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
 115 }
 116 static void at91sam9rlek_lcd_hw_init(void)
 117 {
 118         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 119         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 120         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 121         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 122         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 123         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 124         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 125         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 126         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 127         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 128         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 129         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 130         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 131         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 132         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 133         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 134         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 135         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 136         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 137         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 138         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 139
 140         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
 141
 142         gd->fb_base = 0;
 143 }
 144
 145 #ifdef CONFIG_LCD_INFO
 146 #include <nand.h>
 147 #include <version.h>
 148
 149 void lcd_show_board_info(void)
 150 {
 151         ulong dram_size, nand_size;
 152         int i;
 153         char temp[32];
 154
 155         lcd_printf ("%s\n", U_BOOT_VERSION);
 156         lcd_printf ("(C) 2008 ATMEL Corp\n");
 157         lcd_printf ("at91support@atmel.com\n");
 158         lcd_printf ("%s CPU at %s MHz\n",
 159                 AT91_CPU_NAME,
 160                 strmhz(temp, AT91_CPU_CLOCK));
 161
 162         dram_size = 0;
 163         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 164                 dram_size += gd->bd->bi_dram[i].size;
 165         nand_size = 0;
 166         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 167                 nand_size += nand_info[i].size;
 168         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 169                 dram_size >> 20,
 170                 nand_size >> 20 );
 171 }
 172 #endif /* CONFIG_LCD_INFO */
 173 #endif
 174
 175
 176 int board_init(void)
 177 {
 178         /* Enable Ctrlc */
 179         console_init_f();
 180
 181         /* arch number of AT91SAM9RLEK-Board */
 182         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 183         /* adress of boot parameters */
 184         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 185
 186         at91_serial_hw_init();
 187 #ifdef CONFIG_CMD_NAND
 188         at91sam9rlek_nand_hw_init();
 189 #endif
 190 #ifdef CONFIG_HAS_DATAFLASH
 191         at91_spi0_hw_init(1 << 0);
 192 #endif
 193 #ifdef CONFIG_LCD
 194         at91sam9rlek_lcd_hw_init();
 195 #endif
 196         return 0;
 197 }
 198
 199 int dram_init(void)
 200 {
 201         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 202         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 203         return 0;
 204 }