board/atmel/at91sam9n12ek/at91sam9n12ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Atmel Corporation
   4  * Josh Wu <josh.wu@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <vsprintf.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91sam9x5_matrix.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_rstc.h>
  15 #include <asm/arch/at91_pio.h>
  16 #include <asm/arch/clk.h>
  17 #include <debug_uart.h>
  18 #include <lcd.h>
  19 #include <atmel_hlcdc.h>
  20 #include <netdev.h>
  21
  22 #ifdef CONFIG_LCD_INFO
  23 #include <nand.h>
  24 #include <version.h>
  25 #endif
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* ------------------------------------------------------------------------- */
  30 /*
  31  * Miscelaneous platform dependent initialisations
  32  */
  33 #ifdef CONFIG_NAND_ATMEL
  34 static void at91sam9n12ek_nand_hw_init(void)
  35 {
  36         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  37         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  38         unsigned long csa;
  39
  40         /* Assign CS3 to NAND/SmartMedia Interface */
  41         csa = readl(&matrix->ebicsa);
  42         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  43         /* Configure databus */
  44         csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
  45         /* Configure IO drive */
  46         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  47
  48         writel(csa, &matrix->ebicsa);
  49
  50         /* Configure SMC CS3 for NAND/SmartMedia */
  51         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  52                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  53                 &smc->cs[3].setup);
  54         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  55                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  56                 &smc->cs[3].pulse);
  57         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
  58                 &smc->cs[3].cycle);
  59         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  60                 AT91_SMC_MODE_EXNW_DISABLE |
  61 #ifdef CONFIG_SYS_NAND_DBW_16
  62                 AT91_SMC_MODE_DBW_16 |
  63 #else /* CONFIG_SYS_NAND_DBW_8 */
  64                 AT91_SMC_MODE_DBW_8 |
  65 #endif
  66                 AT91_SMC_MODE_TDF_CYCLE(1),
  67                 &smc->cs[3].mode);
  68
  69         /* Configure RDY/BSY pin */
  70         at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
  71
  72         /* Configure ENABLE pin for NandFlash */
  73         at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
  74
  75         at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
  76         at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
  77         at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
  78         at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
  79 }
  80 #endif
  81
  82 #ifdef CONFIG_LCD
  83 vidinfo_t panel_info = {
  84         .vl_col = 480,
  85         .vl_row = 272,
  86         .vl_clk = 9000000,
  87         .vl_bpix = LCD_BPP,
  88         .vl_sync = 0,
  89         .vl_tft = 1,
  90         .vl_hsync_len = 5,
  91         .vl_left_margin = 8,
  92         .vl_right_margin = 43,
  93         .vl_vsync_len = 10,
  94         .vl_upper_margin = 4,
  95         .vl_lower_margin = 12,
  96         .mmio = ATMEL_BASE_LCDC,
  97 };
  98
  99 void lcd_enable(void)
 100 {
 101         at91_set_pio_output(AT91_PIO_PORTC, 25, 0);     /* power up */
 102 }
 103
 104 void lcd_disable(void)
 105 {
 106         at91_set_pio_output(AT91_PIO_PORTC, 25, 1);     /* power down */
 107 }
 108
 109 #ifdef CONFIG_LCD_INFO
 110 void lcd_show_board_info(void)
 111 {
 112         ulong dram_size, nand_size;
 113         int i;
 114         char temp[32];
 115
 116         lcd_printf("%s\n", U_BOOT_VERSION);
 117         lcd_printf("ATMEL Corp\n");
 118         lcd_printf("at91@atmel.com\n");
 119         lcd_printf("%s CPU at %s MHz\n",
 120                 ATMEL_CPU_NAME,
 121                 strmhz(temp, get_cpu_clk_rate()));
 122
 123         dram_size = 0;
 124         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 125                 dram_size += gd->bd->bi_dram[i].size;
 126         nand_size = 0;
 127         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 128                 nand_size += get_nand_dev_by_index(i)->size;
 129         lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 130                 dram_size >> 20,
 131                 nand_size >> 20);
 132 }
 133 #endif /* CONFIG_LCD_INFO */
 134 #endif /* CONFIG_LCD */
 135
 136 #ifdef CONFIG_KS8851_MLL
 137 void at91sam9n12ek_ks8851_hw_init(void)
 138 {
 139         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 140
 141         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
 142                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
 143                &smc->cs[2].setup);
 144         writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 145                AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
 146                &smc->cs[2].pulse);
 147         writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
 148                &smc->cs[2].cycle);
 149         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 150                AT91_SMC_MODE_EXNW_DISABLE |
 151                AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 152                AT91_SMC_MODE_TDF_CYCLE(1),
 153                &smc->cs[2].mode);
 154
 155         /* Configure NCS2 PIN */
 156         at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
 157 }
 158 #endif
 159
 160 #ifdef CONFIG_USB_ATMEL
 161 void at91sam9n12ek_usb_hw_init(void)
 162 {
 163         at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
 164 }
 165 #endif
 166
 167 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 168 void board_debug_uart_init(void)
 169 {
 170         at91_seriald_hw_init();
 171 }
 172 #endif
 173
 174 #ifdef CONFIG_BOARD_EARLY_INIT_F
 175 int board_early_init_f(void)
 176 {
 177 #ifdef CONFIG_DEBUG_UART
 178         debug_uart_init();
 179 #endif
 180         return 0;
 181 }
 182 #endif
 183
 184 int board_init(void)
 185 {
 186         /* adress of boot parameters */
 187         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 188
 189 #ifdef CONFIG_NAND_ATMEL
 190         at91sam9n12ek_nand_hw_init();
 191 #endif
 192
 193 #ifdef CONFIG_LCD
 194         at91_lcd_hw_init();
 195 #endif
 196
 197 #ifdef CONFIG_KS8851_MLL
 198         at91sam9n12ek_ks8851_hw_init();
 199 #endif
 200
 201 #ifdef CONFIG_USB_ATMEL
 202         at91sam9n12ek_usb_hw_init();
 203 #endif
 204
 205         return 0;
 206 }
 207
 208 #ifdef CONFIG_KS8851_MLL
 209 int board_eth_init(bd_t *bis)
 210 {
 211         return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
 212 }
 213 #endif
 214
 215 int dram_init(void)
 216 {
 217         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 218                                         CONFIG_SYS_SDRAM_SIZE);
 219         return 0;
 220 }
 221
 222 #if defined(CONFIG_SPL_BUILD)
 223 #include <spl.h>
 224 #include <nand.h>
 225
 226 void at91_spl_board_init(void)
 227 {
 228 #ifdef CONFIG_SD_BOOT
 229         at91_mci_hw_init();
 230 #elif CONFIG_NAND_BOOT
 231         at91sam9n12ek_nand_hw_init();
 232 #elif CONFIG_SPI_BOOT
 233         at91_spi0_hw_init(1 << 4);
 234 #endif
 235 }
 236
 237 #include <asm/arch/atmel_mpddrc.h>
 238 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 239 {
 240         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 241
 242         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 243                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 244                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 245                     ATMEL_MPDDRC_CR_NB_8BANKS |
 246                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
 247
 248         ddr2->rtr = 0x411;
 249
 250         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 251                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 252                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 253                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 254                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 255                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 256                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 257                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 258
 259         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 260                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 261                       19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 262                       18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 263
 264         ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 265                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 266                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 267                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 268 }
 269
 270 void mem_init(void)
 271 {
 272         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 273         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 274         struct atmel_mpddrc_config ddr2;
 275         unsigned long csa;
 276
 277         ddr2_conf(&ddr2);
 278
 279         /* enable DDR2 clock */
 280         writel(AT91_PMC_DDR, &pmc->scer);
 281
 282         /* Chip select 1 is for DDR2/SDRAM */
 283         csa = readl(&matrix->ebicsa);
 284         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
 285         csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
 286         csa |= AT91_MATRIX_EBI_DBPD_OFF;
 287         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 288         writel(csa, &matrix->ebicsa);
 289
 290         /* DDRAM2 Controller initialize */
 291         ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
 292 }
 293 #endif