1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
9 #include <debug_uart.h>
13 #include <asm/global_data.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/at91sam9g45_matrix.h>
17 #include <asm/arch/at91sam9_smc.h>
18 #include <asm/arch/at91_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clk.h>
22 #include <linux/mtd/rawnand.h>
23 #include <atmel_lcdc.h>
24 #include <asm/mach-types.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 /* ------------------------------------------------------------------------- */
30 * Miscelaneous platform dependent initialisations
33 #ifdef CONFIG_CMD_NAND
34 void at91sam9m10g45ek_nand_hw_init(void)
36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
41 csa = readl(&matrix->ebicsa);
42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
43 writel(csa, &matrix->ebicsa);
45 /* Configure SMC CS3 for NAND/SmartMedia */
46 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
61 AT91_SMC_MODE_TDF_CYCLE(3),
64 at91_periph_clk_enable(ATMEL_ID_PIOC);
66 /* Configure RDY/BSY */
67 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
69 /* Enable NandFlash */
70 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
74 #if defined(CONFIG_SPL_BUILD)
78 void at91_spl_board_init(void)
81 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
82 * test mode, so it needs do some action to exit test mode.
84 at91_periph_clk_enable(ATMEL_ID_PIODE);
85 at91_set_gpio_output(AT91_PIN_PD7, 0);
86 at91_set_gpio_output(AT91_PIN_PD8, 0);
87 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
88 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
92 #elif CONFIG_NAND_BOOT
93 at91sam9m10g45ek_nand_hw_init();
97 #include <asm/arch/atmel_mpddrc.h>
98 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
100 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
102 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
103 ATMEL_MPDDRC_CR_NR_ROW_14 |
104 ATMEL_MPDDRC_CR_DQMS_SHARED |
105 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
109 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
110 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
111 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
112 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
113 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
114 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
115 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
116 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
118 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
119 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
120 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
121 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
123 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
124 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
125 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
126 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
131 struct atmel_mpddrc_config ddr2;
135 at91_system_clk_enable(AT91_PMC_DDR);
137 /* DDRAM2 Controller initialize */
138 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
142 #ifdef CONFIG_CMD_USB
143 static void at91sam9m10g45ek_usb_hw_init(void)
145 at91_periph_clk_enable(ATMEL_ID_PIODE);
147 at91_set_gpio_output(AT91_PIN_PD1, 0);
148 at91_set_gpio_output(AT91_PIN_PD3, 0);
154 vidinfo_t panel_info = {
158 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
159 ATMEL_LCDC_INVFRAME_NORMAL,
164 .vl_right_margin = 1,
166 .vl_upper_margin = 40,
167 .vl_lower_margin = 1,
168 .mmio = ATMEL_BASE_LCDC,
172 void lcd_enable(void)
174 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
177 void lcd_disable(void)
179 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
182 static void at91sam9m10g45ek_lcd_hw_init(void)
184 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
185 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
186 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
187 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
188 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
190 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
191 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
192 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
193 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
194 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
195 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
196 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
197 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
198 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
199 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
200 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
201 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
202 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
203 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
204 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
205 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
206 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
207 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
208 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
209 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
210 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
211 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
212 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
213 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
215 at91_periph_clk_enable(ATMEL_ID_LCDC);
217 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
220 #ifdef CONFIG_LCD_INFO
224 void lcd_show_board_info(void)
226 ulong dram_size, nand_size;
230 lcd_printf ("%s\n", U_BOOT_VERSION);
231 lcd_printf ("(C) 2008 ATMEL Corp\n");
232 lcd_printf ("at91support@atmel.com\n");
233 lcd_printf ("%s CPU at %s MHz\n",
235 strmhz(temp, get_cpu_clk_rate()));
238 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
239 dram_size += gd->bd->bi_dram[i].size;
241 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
242 nand_size += get_nand_dev_by_index(i)->size;
243 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
247 #endif /* CONFIG_LCD_INFO */
250 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
251 void board_debug_uart_init(void)
253 at91_seriald_hw_init();
257 #ifdef CONFIG_BOARD_EARLY_INIT_F
258 int board_early_init_f(void)
260 #ifdef CONFIG_DEBUG_UART
269 /* arch number of AT91SAM9M10G45EK-Board */
270 #ifdef CONFIG_AT91SAM9M10G45EK
271 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
272 #elif defined CONFIG_AT91SAM9G45EKES
273 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
276 /* adress of boot parameters */
277 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
279 #ifdef CONFIG_CMD_NAND
280 at91sam9m10g45ek_nand_hw_init();
282 #ifdef CONFIG_CMD_USB
283 at91sam9m10g45ek_usb_hw_init();
286 at91sam9m10g45ek_lcd_hw_init();
293 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
294 CONFIG_SYS_SDRAM_SIZE);
298 #ifdef CONFIG_RESET_PHY_R