board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <vsprintf.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/at91sam9g45_matrix.h>
  16 #include <asm/arch/at91sam9_smc.h>
  17 #include <asm/arch/at91_common.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clk.h>
  20 #include <lcd.h>
  21 #include <linux/mtd/rawnand.h>
  22 #include <atmel_lcdc.h>
  23 #include <asm/mach-types.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31
  32 #ifdef CONFIG_CMD_NAND
  33 void at91sam9m10g45ek_nand_hw_init(void)
  34 {
  35         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  37         unsigned long csa;
  38
  39         /* Enable CS3 */
  40         csa = readl(&matrix->ebicsa);
  41         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  42         writel(csa, &matrix->ebicsa);
  43
  44         /* Configure SMC CS3 for NAND/SmartMedia */
  45         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  46                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  47                &smc->cs[3].setup);
  48         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  49                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  50                &smc->cs[3].pulse);
  51         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  52                &smc->cs[3].cycle);
  53         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  54                AT91_SMC_MODE_EXNW_DISABLE |
  55 #ifdef CONFIG_SYS_NAND_DBW_16
  56                AT91_SMC_MODE_DBW_16 |
  57 #else /* CONFIG_SYS_NAND_DBW_8 */
  58                AT91_SMC_MODE_DBW_8 |
  59 #endif
  60                AT91_SMC_MODE_TDF_CYCLE(3),
  61                &smc->cs[3].mode);
  62
  63         at91_periph_clk_enable(ATMEL_ID_PIOC);
  64
  65         /* Configure RDY/BSY */
  66         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  67
  68         /* Enable NandFlash */
  69         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  70 }
  71 #endif
  72
  73 #if defined(CONFIG_SPL_BUILD)
  74 #include <spl.h>
  75 #include <nand.h>
  76
  77 void at91_spl_board_init(void)
  78 {
  79         /*
  80          * On the at91sam9m10g45ek board, the chip wm9711 stays in the
  81          * test mode, so it needs do some action to exit test mode.
  82          */
  83         at91_periph_clk_enable(ATMEL_ID_PIODE);
  84         at91_set_gpio_output(AT91_PIN_PD7, 0);
  85         at91_set_gpio_output(AT91_PIN_PD8, 0);
  86         at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
  87         at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
  88
  89 #ifdef CONFIG_SD_BOOT
  90         at91_mci_hw_init();
  91 #elif CONFIG_NAND_BOOT
  92         at91sam9m10g45ek_nand_hw_init();
  93 #endif
  94 }
  95
  96 #include <asm/arch/atmel_mpddrc.h>
  97 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  98 {
  99         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 100
 101         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 102                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 103                     ATMEL_MPDDRC_CR_DQMS_SHARED |
 104                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
 105
 106         ddr2->rtr = 0x24b;
 107
 108         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
 109                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
 110                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
 111                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
 112                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
 113                       1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
 114                       1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
 115                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
 116
 117         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
 118                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 119                       16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 120                       14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 121
 122         ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 123                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 124                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 125                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 126 }
 127
 128 void mem_init(void)
 129 {
 130         struct atmel_mpddrc_config ddr2;
 131
 132         ddr2_conf(&ddr2);
 133
 134         at91_system_clk_enable(AT91_PMC_DDR);
 135
 136         /* DDRAM2 Controller initialize */
 137         ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
 138 }
 139 #endif
 140
 141 #ifdef CONFIG_CMD_USB
 142 static void at91sam9m10g45ek_usb_hw_init(void)
 143 {
 144         at91_periph_clk_enable(ATMEL_ID_PIODE);
 145
 146         at91_set_gpio_output(AT91_PIN_PD1, 0);
 147         at91_set_gpio_output(AT91_PIN_PD3, 0);
 148 }
 149 #endif
 150
 151 #ifdef CONFIG_LCD
 152
 153 vidinfo_t panel_info = {
 154         .vl_col =               480,
 155         .vl_row =               272,
 156         .vl_clk =               9000000,
 157         .vl_sync =              ATMEL_LCDC_INVLINE_NORMAL |
 158                                 ATMEL_LCDC_INVFRAME_NORMAL,
 159         .vl_bpix =              3,
 160         .vl_tft =               1,
 161         .vl_hsync_len =         45,
 162         .vl_left_margin =       1,
 163         .vl_right_margin =      1,
 164         .vl_vsync_len =         1,
 165         .vl_upper_margin =      40,
 166         .vl_lower_margin =      1,
 167         .mmio =                 ATMEL_BASE_LCDC,
 168 };
 169
 170
 171 void lcd_enable(void)
 172 {
 173         at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 174 }
 175
 176 void lcd_disable(void)
 177 {
 178         at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 179 }
 180
 181 static void at91sam9m10g45ek_lcd_hw_init(void)
 182 {
 183         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 184         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 185         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 186         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 187         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 188
 189         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 190         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 191         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 192         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 193         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 194         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 195         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 196         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 197         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 198         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 199         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 200         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 201         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 202         at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 203         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 204         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 205         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 206         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 207         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 208         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 209         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 210         at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 211         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 212         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 213
 214         at91_periph_clk_enable(ATMEL_ID_LCDC);
 215
 216         gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 217 }
 218
 219 #ifdef CONFIG_LCD_INFO
 220 #include <nand.h>
 221 #include <version.h>
 222
 223 void lcd_show_board_info(void)
 224 {
 225         ulong dram_size, nand_size;
 226         int i;
 227         char temp[32];
 228
 229         lcd_printf ("%s\n", U_BOOT_VERSION);
 230         lcd_printf ("(C) 2008 ATMEL Corp\n");
 231         lcd_printf ("at91support@atmel.com\n");
 232         lcd_printf ("%s CPU at %s MHz\n",
 233                 ATMEL_CPU_NAME,
 234                 strmhz(temp, get_cpu_clk_rate()));
 235
 236         dram_size = 0;
 237         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 238                 dram_size += gd->bd->bi_dram[i].size;
 239         nand_size = 0;
 240         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 241                 nand_size += get_nand_dev_by_index(i)->size;
 242         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 243                 dram_size >> 20,
 244                 nand_size >> 20 );
 245 }
 246 #endif /* CONFIG_LCD_INFO */
 247 #endif
 248
 249 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 250 void board_debug_uart_init(void)
 251 {
 252         at91_seriald_hw_init();
 253 }
 254 #endif
 255
 256 #ifdef CONFIG_BOARD_EARLY_INIT_F
 257 int board_early_init_f(void)
 258 {
 259 #ifdef CONFIG_DEBUG_UART
 260         debug_uart_init();
 261 #endif
 262         return 0;
 263 }
 264 #endif
 265
 266 int board_init(void)
 267 {
 268         /* arch number of AT91SAM9M10G45EK-Board */
 269 #ifdef CONFIG_AT91SAM9M10G45EK
 270         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
 271 #elif defined CONFIG_AT91SAM9G45EKES
 272         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
 273 #endif
 274
 275         /* adress of boot parameters */
 276         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 277
 278 #ifdef CONFIG_CMD_NAND
 279         at91sam9m10g45ek_nand_hw_init();
 280 #endif
 281 #ifdef CONFIG_CMD_USB
 282         at91sam9m10g45ek_usb_hw_init();
 283 #endif
 284 #ifdef CONFIG_LCD
 285         at91sam9m10g45ek_lcd_hw_init();
 286 #endif
 287         return 0;
 288 }
 289
 290 int dram_init(void)
 291 {
 292         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
 293                                     CONFIG_SYS_SDRAM_SIZE);
 294         return 0;
 295 }
 296
 297 #ifdef CONFIG_RESET_PHY_R
 298 void reset_phy(void)
 299 {
 300 }
 301 #endif