1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
9 #include <debug_uart.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/at91sam9g45_matrix.h>
15 #include <asm/arch/at91sam9_smc.h>
16 #include <asm/arch/at91_common.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/clk.h>
20 #include <linux/mtd/rawnand.h>
21 #include <atmel_lcdc.h>
22 #include <asm/mach-types.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 /* ------------------------------------------------------------------------- */
28 * Miscelaneous platform dependent initialisations
31 #ifdef CONFIG_CMD_NAND
32 void at91sam9m10g45ek_nand_hw_init(void)
34 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
35 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
39 csa = readl(&matrix->ebicsa);
40 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
41 writel(csa, &matrix->ebicsa);
43 /* Configure SMC CS3 for NAND/SmartMedia */
44 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
45 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
47 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
48 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
50 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
52 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
53 AT91_SMC_MODE_EXNW_DISABLE |
54 #ifdef CONFIG_SYS_NAND_DBW_16
55 AT91_SMC_MODE_DBW_16 |
56 #else /* CONFIG_SYS_NAND_DBW_8 */
59 AT91_SMC_MODE_TDF_CYCLE(3),
62 at91_periph_clk_enable(ATMEL_ID_PIOC);
64 /* Configure RDY/BSY */
65 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
67 /* Enable NandFlash */
68 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
72 #if defined(CONFIG_SPL_BUILD)
76 void at91_spl_board_init(void)
79 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
80 * test mode, so it needs do some action to exit test mode.
82 at91_periph_clk_enable(ATMEL_ID_PIODE);
83 at91_set_gpio_output(AT91_PIN_PD7, 0);
84 at91_set_gpio_output(AT91_PIN_PD8, 0);
85 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
86 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
90 #elif CONFIG_NAND_BOOT
91 at91sam9m10g45ek_nand_hw_init();
95 #include <asm/arch/atmel_mpddrc.h>
96 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
98 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
100 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
101 ATMEL_MPDDRC_CR_NR_ROW_14 |
102 ATMEL_MPDDRC_CR_DQMS_SHARED |
103 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
107 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
108 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
109 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
110 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
111 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
112 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
113 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
114 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
116 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
117 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
118 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
119 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
121 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
122 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
123 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
124 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
129 struct atmel_mpddrc_config ddr2;
133 at91_system_clk_enable(AT91_PMC_DDR);
135 /* DDRAM2 Controller initialize */
136 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
140 #ifdef CONFIG_CMD_USB
141 static void at91sam9m10g45ek_usb_hw_init(void)
143 at91_periph_clk_enable(ATMEL_ID_PIODE);
145 at91_set_gpio_output(AT91_PIN_PD1, 0);
146 at91_set_gpio_output(AT91_PIN_PD3, 0);
152 vidinfo_t panel_info = {
156 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
157 ATMEL_LCDC_INVFRAME_NORMAL,
162 .vl_right_margin = 1,
164 .vl_upper_margin = 40,
165 .vl_lower_margin = 1,
166 .mmio = ATMEL_BASE_LCDC,
170 void lcd_enable(void)
172 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
175 void lcd_disable(void)
177 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
180 static void at91sam9m10g45ek_lcd_hw_init(void)
182 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
183 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
184 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
185 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
186 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
188 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
189 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
190 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
191 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
192 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
193 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
194 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
195 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
196 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
197 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
198 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
199 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
200 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
201 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
202 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
203 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
204 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
205 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
206 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
207 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
208 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
209 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
210 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
211 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
213 at91_periph_clk_enable(ATMEL_ID_LCDC);
215 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
218 #ifdef CONFIG_LCD_INFO
222 void lcd_show_board_info(void)
224 ulong dram_size, nand_size;
228 lcd_printf ("%s\n", U_BOOT_VERSION);
229 lcd_printf ("(C) 2008 ATMEL Corp\n");
230 lcd_printf ("at91support@atmel.com\n");
231 lcd_printf ("%s CPU at %s MHz\n",
233 strmhz(temp, get_cpu_clk_rate()));
236 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
237 dram_size += gd->bd->bi_dram[i].size;
239 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
240 nand_size += get_nand_dev_by_index(i)->size;
241 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
245 #endif /* CONFIG_LCD_INFO */
248 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
249 void board_debug_uart_init(void)
251 at91_seriald_hw_init();
255 #ifdef CONFIG_BOARD_EARLY_INIT_F
256 int board_early_init_f(void)
258 #ifdef CONFIG_DEBUG_UART
267 /* arch number of AT91SAM9M10G45EK-Board */
268 #ifdef CONFIG_AT91SAM9M10G45EK
269 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
270 #elif defined CONFIG_AT91SAM9G45EKES
271 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
274 /* adress of boot parameters */
275 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
277 #ifdef CONFIG_CMD_NAND
278 at91sam9m10g45ek_nand_hw_init();
280 #ifdef CONFIG_CMD_USB
281 at91sam9m10g45ek_usb_hw_init();
284 at91sam9m10g45ek_lcd_hw_init();
291 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
292 CONFIG_SYS_SDRAM_SIZE);
296 #ifdef CONFIG_RESET_PHY_R