board/atmel/at91sam9263ek/at91sam9263ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <net.h>
  11 #include <vsprintf.h>
  12 #include <linux/sizes.h>
  13 #include <asm/arch/at91sam9263.h>
  14 #include <asm/arch/at91sam9_smc.h>
  15 #include <asm/arch/at91_common.h>
  16 #include <asm/arch/at91_matrix.h>
  17 #include <asm/arch/at91_pio.h>
  18 #include <asm/arch/clk.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/hardware.h>
  22 #include <lcd.h>
  23 #include <atmel_lcdc.h>
  24 #include <asm/mach-types.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /* ------------------------------------------------------------------------- */
  29 /*
  30  * Miscelaneous platform dependent initialisations
  31  */
  32
  33 #ifdef CONFIG_CMD_NAND
  34 static void at91sam9263ek_nand_hw_init(void)
  35 {
  36         unsigned long csa;
  37         at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  38         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  39
  40         /* Enable CS3 */
  41         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  42         writel(csa, &matrix->csa[0]);
  43
  44         /* Enable CS3 */
  45
  46         /* Configure SMC CS3 for NAND/SmartMedia */
  47         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  48                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  49                 &smc->cs[3].setup);
  50
  51         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  52                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  53                 &smc->cs[3].pulse);
  54
  55         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  56                 &smc->cs[3].cycle);
  57         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  58                 AT91_SMC_MODE_EXNW_DISABLE |
  59 #ifdef CONFIG_SYS_NAND_DBW_16
  60                        AT91_SMC_MODE_DBW_16 |
  61 #else /* CONFIG_SYS_NAND_DBW_8 */
  62                        AT91_SMC_MODE_DBW_8 |
  63 #endif
  64                        AT91_SMC_MODE_TDF_CYCLE(2),
  65                 &smc->cs[3].mode);
  66
  67         at91_periph_clk_enable(ATMEL_ID_PIOA);
  68         at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  69
  70         /* Configure RDY/BSY */
  71         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  72
  73         /* Enable NandFlash */
  74         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  75 }
  76 #endif
  77
  78 #ifdef CONFIG_LCD
  79 vidinfo_t panel_info = {
  80         .vl_col =               240,
  81         .vl_row =               320,
  82         .vl_clk =               4965000,
  83         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
  84                                 ATMEL_LCDC_INVFRAME_INVERTED,
  85         .vl_bpix =              3,
  86         .vl_tft =               1,
  87         .vl_hsync_len =         5,
  88         .vl_left_margin =       1,
  89         .vl_right_margin =      33,
  90         .vl_vsync_len =         1,
  91         .vl_upper_margin =      1,
  92         .vl_lower_margin =      0,
  93         .mmio =                 ATMEL_BASE_LCDC,
  94 };
  95
  96 void lcd_enable(void)
  97 {
  98         at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
  99 }
 100
 101 void lcd_disable(void)
 102 {
 103         at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 104 }
 105
 106 static void at91sam9263ek_lcd_hw_init(void)
 107 {
 108         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 109         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 110         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 111         at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 112         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 113         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 114         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 115         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 116         at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 117         at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 118         at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 119         at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 120         at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 121         at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 122         at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 123         at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 124         at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 125         at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 126         at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 127         at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 128         at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 129         at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 130
 131         at91_periph_clk_enable(ATMEL_ID_LCDC);
 132         gd->fb_base = ATMEL_BASE_SRAM0;
 133 }
 134
 135 #ifdef CONFIG_LCD_INFO
 136 #include <nand.h>
 137 #include <version.h>
 138
 139 #ifdef CONFIG_MTD_NOR_FLASH
 140 extern flash_info_t flash_info[];
 141 #endif
 142
 143 void lcd_show_board_info(void)
 144 {
 145         ulong dram_size, nand_size;
 146 #ifdef CONFIG_MTD_NOR_FLASH
 147         ulong flash_size;
 148 #endif
 149         int i;
 150         char temp[32];
 151
 152         lcd_printf ("%s\n", U_BOOT_VERSION);
 153         lcd_printf ("(C) 2008 ATMEL Corp\n");
 154         lcd_printf ("at91support@atmel.com\n");
 155         lcd_printf ("%s CPU at %s MHz\n",
 156                 ATMEL_CPU_NAME,
 157                 strmhz(temp, get_cpu_clk_rate()));
 158
 159         dram_size = 0;
 160         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 161                 dram_size += gd->bd->bi_dram[i].size;
 162         nand_size = 0;
 163         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 164                 nand_size += get_nand_dev_by_index(i)->size;
 165 #ifdef CONFIG_MTD_NOR_FLASH
 166         flash_size = 0;
 167         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 168                 flash_size += flash_info[i].size;
 169 #endif
 170         lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 171                 dram_size >> 20,
 172                 nand_size >> 20 );
 173 #ifdef CONFIG_MTD_NOR_FLASH
 174         lcd_printf (",\n  %ld MB NOR",
 175                 flash_size >> 20);
 176 #endif
 177         lcd_puts ("\n");
 178 }
 179 #endif /* CONFIG_LCD_INFO */
 180 #endif
 181
 182 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 183 void board_debug_uart_init(void)
 184 {
 185         at91_seriald_hw_init();
 186 }
 187 #endif
 188
 189 #ifdef CONFIG_BOARD_EARLY_INIT_F
 190 int board_early_init_f(void)
 191 {
 192 #ifdef CONFIG_DEBUG_UART
 193         debug_uart_init();
 194 #endif
 195         return 0;
 196 }
 197 #endif
 198
 199 int board_init(void)
 200 {
 201         /* arch number of AT91SAM9263EK-Board */
 202         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 203         /* adress of boot parameters */
 204         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 205
 206 #ifdef CONFIG_CMD_NAND
 207         at91sam9263ek_nand_hw_init();
 208 #endif
 209 #ifdef CONFIG_USB_OHCI_NEW
 210         at91_uhp_hw_init();
 211 #endif
 212 #ifdef CONFIG_LCD
 213         at91sam9263ek_lcd_hw_init();
 214 #endif
 215         return 0;
 216 }
 217
 218 int dram_init(void)
 219 {
 220         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 221                 CONFIG_SYS_SDRAM_SIZE);
 222
 223         return 0;
 224 }
 225
 226 #ifdef CONFIG_RESET_PHY_R
 227 void reset_phy(void)
 228 {
 229 }
 230 #endif