board/atmel/at91sam9263ek/at91sam9263ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <vsprintf.h>
  13 #include <asm/global_data.h>
  14 #include <linux/sizes.h>
  15 #include <asm/arch/at91sam9263.h>
  16 #include <asm/arch/at91sam9_smc.h>
  17 #include <asm/arch/at91_common.h>
  18 #include <asm/arch/at91_matrix.h>
  19 #include <asm/arch/at91_pio.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/hardware.h>
  24 #include <lcd.h>
  25 #include <atmel_lcdc.h>
  26 #include <asm/mach-types.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34
  35 #ifdef CONFIG_CMD_NAND
  36 static void at91sam9263ek_nand_hw_init(void)
  37 {
  38         unsigned long csa;
  39         at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  40         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  41
  42         /* Enable CS3 */
  43         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  44         writel(csa, &matrix->csa[0]);
  45
  46         /* Enable CS3 */
  47
  48         /* Configure SMC CS3 for NAND/SmartMedia */
  49         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  50                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  51                 &smc->cs[3].setup);
  52
  53         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  54                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  55                 &smc->cs[3].pulse);
  56
  57         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  58                 &smc->cs[3].cycle);
  59         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  60                 AT91_SMC_MODE_EXNW_DISABLE |
  61 #ifdef CONFIG_SYS_NAND_DBW_16
  62                        AT91_SMC_MODE_DBW_16 |
  63 #else /* CONFIG_SYS_NAND_DBW_8 */
  64                        AT91_SMC_MODE_DBW_8 |
  65 #endif
  66                        AT91_SMC_MODE_TDF_CYCLE(2),
  67                 &smc->cs[3].mode);
  68
  69         at91_periph_clk_enable(ATMEL_ID_PIOA);
  70         at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  71
  72         /* Configure RDY/BSY */
  73         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  74
  75         /* Enable NandFlash */
  76         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  77 }
  78 #endif
  79
  80 #ifdef CONFIG_LCD
  81 vidinfo_t panel_info = {
  82         .vl_col =               240,
  83         .vl_row =               320,
  84         .vl_clk =               4965000,
  85         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
  86                                 ATMEL_LCDC_INVFRAME_INVERTED,
  87         .vl_bpix =              3,
  88         .vl_tft =               1,
  89         .vl_hsync_len =         5,
  90         .vl_left_margin =       1,
  91         .vl_right_margin =      33,
  92         .vl_vsync_len =         1,
  93         .vl_upper_margin =      1,
  94         .vl_lower_margin =      0,
  95         .mmio =                 ATMEL_BASE_LCDC,
  96 };
  97
  98 void lcd_enable(void)
  99 {
 100         at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
 101 }
 102
 103 void lcd_disable(void)
 104 {
 105         at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 106 }
 107
 108 static void at91sam9263ek_lcd_hw_init(void)
 109 {
 110         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 111         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 112         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 113         at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 114         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 115         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 116         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 117         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 118         at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 119         at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 120         at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 121         at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 122         at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 123         at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 124         at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 125         at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 126         at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 127         at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 128         at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 129         at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 130         at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 131         at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 132
 133         at91_periph_clk_enable(ATMEL_ID_LCDC);
 134         gd->fb_base = ATMEL_BASE_SRAM0;
 135 }
 136
 137 #ifdef CONFIG_LCD_INFO
 138 #include <nand.h>
 139 #include <version.h>
 140
 141 #ifdef CONFIG_MTD_NOR_FLASH
 142 #include <flash.h>
 143 #endif
 144
 145 void lcd_show_board_info(void)
 146 {
 147         ulong dram_size, nand_size;
 148 #ifdef CONFIG_MTD_NOR_FLASH
 149         ulong flash_size;
 150 #endif
 151         int i;
 152         char temp[32];
 153
 154         lcd_printf ("%s\n", U_BOOT_VERSION);
 155         lcd_printf ("(C) 2008 ATMEL Corp\n");
 156         lcd_printf ("at91support@atmel.com\n");
 157         lcd_printf ("%s CPU at %s MHz\n",
 158                 ATMEL_CPU_NAME,
 159                 strmhz(temp, get_cpu_clk_rate()));
 160
 161         dram_size = 0;
 162         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 163                 dram_size += gd->bd->bi_dram[i].size;
 164         nand_size = 0;
 165         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 166                 nand_size += get_nand_dev_by_index(i)->size;
 167 #ifdef CONFIG_MTD_NOR_FLASH
 168         flash_size = 0;
 169         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 170                 flash_size += flash_info[i].size;
 171 #endif
 172         lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 173                 dram_size >> 20,
 174                 nand_size >> 20 );
 175 #ifdef CONFIG_MTD_NOR_FLASH
 176         lcd_printf (",\n  %ld MB NOR",
 177                 flash_size >> 20);
 178 #endif
 179         lcd_puts ("\n");
 180 }
 181 #endif /* CONFIG_LCD_INFO */
 182 #endif
 183
 184 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 185 void board_debug_uart_init(void)
 186 {
 187         at91_seriald_hw_init();
 188 }
 189 #endif
 190
 191 #ifdef CONFIG_BOARD_EARLY_INIT_F
 192 int board_early_init_f(void)
 193 {
 194         return 0;
 195 }
 196 #endif
 197
 198 int board_init(void)
 199 {
 200         /* arch number of AT91SAM9263EK-Board */
 201         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 202         /* adress of boot parameters */
 203         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 204
 205 #ifdef CONFIG_CMD_NAND
 206         at91sam9263ek_nand_hw_init();
 207 #endif
 208 #ifdef CONFIG_USB_OHCI_NEW
 209         at91_uhp_hw_init();
 210 #endif
 211 #ifdef CONFIG_LCD
 212         at91sam9263ek_lcd_hw_init();
 213 #endif
 214         return 0;
 215 }
 216
 217 int dram_init(void)
 218 {
 219         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 220                 CONFIG_SYS_SDRAM_SIZE);
 221
 222         return 0;
 223 }
 224
 225 #ifdef CONFIG_RESET_PHY_R
 226 void reset_phy(void)
 227 {
 228 }
 229 #endif