2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91cap9.h>
27 #include <asm/arch/at91cap9_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_pmc.h>
30 #include <asm/arch/at91_rstc.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/io.h>
34 #include <atmel_lcdc.h>
35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39 #define MP_BLOCK_3_BASE 0xFDF00000
41 DECLARE_GLOBAL_DATA_PTR;
43 /* ------------------------------------------------------------------------- */
45 * Miscelaneous platform dependent initialisations
48 static void at91cap9_serial_hw_init(void)
51 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
52 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
53 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
57 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
58 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
59 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
63 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
64 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
65 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
68 #ifdef CONFIG_USART3 /* DBGU */
69 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
70 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
71 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
75 static void at91cap9_slowclock_hw_init(void)
78 * On AT91CAP9 revC CPUs, the slow clock can be based on an
79 * internal impreciseRC oscillator or an external 32kHz oscillator.
80 * Switch to the latter.
82 #define ARCH_ID_AT91CAP9_REVB 0x399
83 #define ARCH_ID_AT91CAP9_REVC 0x601
84 if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
85 unsigned i, tmp = at91_sys_read(AT91_SCKCR);
86 if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
87 extern void timer_init(void);
89 tmp |= AT91CAP9_SCKCR_OSC32EN;
90 at91_sys_write(AT91_SCKCR, tmp);
91 for (i = 0; i < 1200; i++)
93 tmp |= AT91CAP9_SCKCR_OSCSEL_32;
94 at91_sys_write(AT91_SCKCR, tmp);
96 tmp &= ~AT91CAP9_SCKCR_RCEN;
97 at91_sys_write(AT91_SCKCR, tmp);
102 static void at91cap9_nor_hw_init(void)
106 /* Ensure EBI supply is 3.3V */
107 csa = at91_sys_read(AT91_MATRIX_EBICSA);
108 at91_sys_write(AT91_MATRIX_EBICSA,
109 csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
110 /* Configure SMC CS0 for parallel flash */
111 at91_sys_write(AT91_SMC_SETUP(0),
112 AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
113 AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
114 at91_sys_write(AT91_SMC_PULSE(0),
115 AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
116 AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
117 at91_sys_write(AT91_SMC_CYCLE(0),
118 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
119 at91_sys_write(AT91_SMC_MODE(0),
120 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
121 AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
122 AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
125 #ifdef CONFIG_CMD_NAND
126 static void at91cap9_nand_hw_init(void)
131 csa = at91_sys_read(AT91_MATRIX_EBICSA);
132 at91_sys_write(AT91_MATRIX_EBICSA,
133 csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
134 AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
136 /* Configure SMC CS3 for NAND/SmartMedia */
137 at91_sys_write(AT91_SMC_SETUP(3),
138 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
139 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
140 at91_sys_write(AT91_SMC_PULSE(3),
141 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
142 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
143 at91_sys_write(AT91_SMC_CYCLE(3),
144 AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
145 at91_sys_write(AT91_SMC_MODE(3),
146 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
147 AT91_SMC_EXNWMODE_DISABLE |
148 #ifdef CFG_NAND_DBW_16
150 #else /* CFG_NAND_DBW_8 */
155 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
157 /* RDY/BSY is not connected */
159 /* Enable NandFlash */
160 at91_set_gpio_output(AT91_PIN_PD15, 1);
164 #ifdef CONFIG_HAS_DATAFLASH
165 static void at91cap9_spi_hw_init(void)
167 at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
169 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
170 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
171 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
174 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
179 static void at91cap9_macb_hw_init(void)
182 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
185 * Disable pull-up on:
186 * RXDV (PB22) => PHY normal mode (not Test mode)
187 * ERX0 (PB25) => PHY ADDR0
188 * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
190 * PHY has internal pull-down
192 writel(pin_to_mask(AT91_PIN_PB22) |
193 pin_to_mask(AT91_PIN_PB25) |
194 pin_to_mask(AT91_PIN_PB26),
195 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
197 /* Need to reset PHY -> 500ms reset */
198 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
199 AT91_RSTC_ERSTL | (0x0D << 8) |
202 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
204 /* Wait for end hardware reset */
205 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
207 /* Re-enable pull-up */
208 writel(pin_to_mask(AT91_PIN_PB22) |
209 pin_to_mask(AT91_PIN_PB25) |
210 pin_to_mask(AT91_PIN_PB26),
211 pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
213 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
214 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
215 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
216 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
217 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
218 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
219 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
220 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
221 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
222 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
225 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
226 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
227 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
228 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
229 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
230 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
231 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
232 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
234 /* Unlock EMAC, 3 0 2 1 sequence */
235 #define MP_MAC_KEY0 0x5969cb2a
236 #define MP_MAC_KEY1 0xb4a1872e
237 #define MP_MAC_KEY2 0x05683fbc
238 #define MP_MAC_KEY3 0x3634fba4
239 #define UNLOCK_MAC 0x00000008
240 writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
241 writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
242 writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
243 writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
244 writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
248 #ifdef CONFIG_USB_OHCI_NEW
249 static void at91cap9_uhp_hw_init(void)
251 /* Unlock USB OHCI, 3 2 0 1 sequence */
252 #define MP_OHCI_KEY0 0x896c11ca
253 #define MP_OHCI_KEY1 0x68ebca21
254 #define MP_OHCI_KEY2 0x4823efbc
255 #define MP_OHCI_KEY3 0x8651aae4
256 #define UNLOCK_OHCI 0x00000010
257 writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
258 writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
259 writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
260 writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
261 writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
266 vidinfo_t panel_info = {
270 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
271 ATMEL_LCDC_INVFRAME_INVERTED,
280 mmio: AT91CAP9_LCDC_BASE,
283 void lcd_enable(void)
285 at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
288 void lcd_disable(void)
290 at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
293 static void at91cap9_lcd_hw_init(void)
295 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
296 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
297 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
298 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
299 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
300 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
301 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
302 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
303 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
304 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
305 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
306 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
307 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
308 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
309 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
310 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
311 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
312 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
313 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
314 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
315 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
316 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
318 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
329 /* arch number of AT91CAP9ADK-Board */
330 gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
331 /* adress of boot parameters */
332 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
334 at91cap9_serial_hw_init();
335 at91cap9_slowclock_hw_init();
336 at91cap9_nor_hw_init();
337 #ifdef CONFIG_CMD_NAND
338 at91cap9_nand_hw_init();
340 #ifdef CONFIG_HAS_DATAFLASH
341 at91cap9_spi_hw_init();
344 at91cap9_macb_hw_init();
346 #ifdef CONFIG_USB_OHCI_NEW
347 at91cap9_uhp_hw_init();
350 at91cap9_lcd_hw_init();
357 gd->bd->bi_dram[0].start = PHYS_SDRAM;
358 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
362 #ifdef CONFIG_RESET_PHY_R
367 * Initialize ethernet HW addr prior to starting Linux,