board/armltd/vexpress64/pcie.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) ARM Ltd 2015
   4  *
   5  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <linux/bitops.h>
  13 #include <pci_ids.h>
  14 #include <linux/delay.h>
  15 #include "pcie.h"
  16
  17 /* XpressRICH3 support */
  18 #define XR3_CONFIG_BASE                 0x7ff30000
  19 #define XR3_RESET_BASE                  0x7ff20000
  20
  21 #define XR3_PCI_ECAM_START              0x40000000
  22 #define XR3_PCI_ECAM_SIZE               28      /* as power of 2 = 0x10000000 */
  23 #define XR3_PCI_IOSPACE_START           0x5f800000
  24 #define XR3_PCI_IOSPACE_SIZE            23      /* as power of 2 = 0x800000 */
  25 #define XR3_PCI_MEMSPACE_START          0x50000000
  26 #define XR3_PCI_MEMSPACE_SIZE           27      /* as power of 2 = 0x8000000 */
  27 #define XR3_PCI_MEMSPACE64_START        0x4000000000
  28 #define XR3_PCI_MEMSPACE64_SIZE         33      /* as power of 2 = 0x200000000 */
  29
  30 #define JUNO_V2M_MSI_START              0x2c1c0000
  31 #define JUNO_V2M_MSI_SIZE               12      /* as power of 2 = 4096 */
  32
  33 #define XR3PCI_BASIC_STATUS             0x18
  34 #define XR3PCI_BS_GEN_MASK              (0xf << 8)
  35 #define XR3PCI_BS_LINK_MASK             0xff
  36
  37 #define XR3PCI_VIRTCHAN_CREDITS         0x90
  38 #define XR3PCI_BRIDGE_PCI_IDS           0x9c
  39 #define XR3PCI_PEX_SPC2                 0xd8
  40
  41 #define XR3PCI_ATR_PCIE_WIN0            0x600
  42 #define XR3PCI_ATR_PCIE_WIN1            0x700
  43 #define XR3PCI_ATR_AXI4_SLV0            0x800
  44
  45 #define XR3PCI_ATR_TABLE_SIZE           0x20
  46 #define XR3PCI_ATR_SRC_ADDR_LOW         0x0
  47 #define XR3PCI_ATR_SRC_ADDR_HIGH        0x4
  48 #define XR3PCI_ATR_TRSL_ADDR_LOW        0x8
  49 #define XR3PCI_ATR_TRSL_ADDR_HIGH       0xc
  50 #define XR3PCI_ATR_TRSL_PARAM           0x10
  51
  52 /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
  53 #define XR3PCI_ATR_TRSLID_AXIDEVICE     (0x420004)
  54 #define XR3PCI_ATR_TRSLID_AXIMEMORY     (0x4e0004)  /* Write-through, read/write allocate */
  55 #define XR3PCI_ATR_TRSLID_PCIE_CONF     (0x000001)
  56 #define XR3PCI_ATR_TRSLID_PCIE_IO       (0x020000)
  57 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY   (0x000000)
  58
  59 #define JUNO_RESET_CTRL                 0x1004
  60 #define JUNO_RESET_CTRL_PHY             BIT(0)
  61 #define JUNO_RESET_CTRL_RC              BIT(1)
  62
  63 #define JUNO_RESET_STATUS               0x1008
  64 #define JUNO_RESET_STATUS_PLL           BIT(0)
  65 #define JUNO_RESET_STATUS_PHY           BIT(1)
  66 #define JUNO_RESET_STATUS_RC            BIT(2)
  67 #define JUNO_RESET_STATUS_MASK          (JUNO_RESET_STATUS_PLL | \
  68                                          JUNO_RESET_STATUS_PHY | \
  69                                          JUNO_RESET_STATUS_RC)
  70
  71 static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
  72                                  unsigned long trsl_addr, int window_size,
  73                                  int trsl_param)
  74 {
  75         /* X3PCI_ATR_SRC_ADDR_LOW:
  76              - bit 0: enable entry,
  77              - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
  78              - bits 7-11: reserved
  79              - bits 12-31: start of source address
  80         */
  81         writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
  82                base + XR3PCI_ATR_SRC_ADDR_LOW);
  83         writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
  84         writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
  85         writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
  86         writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
  87
  88         debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
  89                src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
  90                ((u64)1) << window_size, trsl_param);
  91 }
  92
  93 static void xr3pci_setup_atr(void)
  94 {
  95         /* setup PCIe to CPU address translation tables */
  96         unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
  97
  98         /* forward all writes from PCIe to GIC V2M (used for MSI) */
  99         xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
 100                              JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
 101
 102         base += XR3PCI_ATR_TABLE_SIZE;
 103
 104         /* PCIe devices can write anywhere in memory */
 105         xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
 106                              31 /* grant access to all RAM under 4GB */,
 107                              XR3PCI_ATR_TRSLID_AXIMEMORY);
 108         base += XR3PCI_ATR_TABLE_SIZE;
 109         xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
 110                              XR3_PCI_MEMSPACE64_SIZE,
 111                              XR3PCI_ATR_TRSLID_AXIMEMORY);
 112
 113
 114         /* setup CPU to PCIe address translation table */
 115         base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
 116
 117         /* setup ECAM space to bus configuration interface */
 118         xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
 119                              XR3PCI_ATR_TRSLID_PCIE_CONF);
 120
 121         base += XR3PCI_ATR_TABLE_SIZE;
 122
 123         /* setup IO space translation */
 124         xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
 125                              XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
 126
 127         base += XR3PCI_ATR_TABLE_SIZE;
 128
 129         /* setup 32bit MEM space translation */
 130         xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
 131                              XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
 132
 133         base += XR3PCI_ATR_TABLE_SIZE;
 134
 135         /* setup 64bit MEM space translation */
 136         xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
 137                              XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
 138 }
 139
 140 static void xr3pci_init(void)
 141 {
 142         u32 val;
 143         int timeout = 200;
 144
 145         /* Initialise the XpressRICH3 PCIe host bridge */
 146
 147         /* add credits */
 148         writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
 149         writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
 150         /* allow ECRC */
 151         writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
 152         /* setup the correct class code for the host bridge */
 153         writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
 154
 155         /* reset phy and root complex */
 156         writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
 157                XR3_RESET_BASE + JUNO_RESET_CTRL);
 158
 159         do {
 160                 mdelay(1);
 161                 val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
 162         } while (--timeout &&
 163                 (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
 164
 165         if (!timeout) {
 166                 printf("PCI XR3 Root complex reset timed out\n");
 167                 return;
 168         }
 169
 170         /* Wait for the link to train */
 171         mdelay(20);
 172         timeout = 20;
 173
 174         do {
 175                 mdelay(1);
 176                 val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
 177         } while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
 178
 179         if (!(val & XR3PCI_BS_LINK_MASK)) {
 180                 printf("Failed to negotiate a link!\n");
 181                 return;
 182         }
 183
 184         printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
 185                val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
 186
 187         xr3pci_setup_atr();
 188 }
 189
 190 void vexpress64_pcie_init(void)
 191 {
 192         /* Initialise and configure the PCIe host bridge. */
 193         xr3pci_init();
 194
 195         /* Register the now ECAM complaint PCIe host controller with U-Boot. */
 196         pci_init();
 197 }