1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) ARM Ltd 2015
5 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
10 #include <linux/bitops.h>
14 /* XpressRICH3 support */
15 #define XR3_CONFIG_BASE 0x7ff30000
16 #define XR3_RESET_BASE 0x7ff20000
18 #define XR3_PCI_ECAM_START 0x40000000
19 #define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */
20 #define XR3_PCI_IOSPACE_START 0x5f800000
21 #define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */
22 #define XR3_PCI_MEMSPACE_START 0x50000000
23 #define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */
24 #define XR3_PCI_MEMSPACE64_START 0x4000000000
25 #define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */
27 #define JUNO_V2M_MSI_START 0x2c1c0000
28 #define JUNO_V2M_MSI_SIZE 12 /* as power of 2 = 4096 */
30 #define XR3PCI_BASIC_STATUS 0x18
31 #define XR3PCI_BS_GEN_MASK (0xf << 8)
32 #define XR3PCI_BS_LINK_MASK 0xff
34 #define XR3PCI_VIRTCHAN_CREDITS 0x90
35 #define XR3PCI_BRIDGE_PCI_IDS 0x9c
36 #define XR3PCI_PEX_SPC2 0xd8
38 #define XR3PCI_ATR_PCIE_WIN0 0x600
39 #define XR3PCI_ATR_PCIE_WIN1 0x700
40 #define XR3PCI_ATR_AXI4_SLV0 0x800
42 #define XR3PCI_ATR_TABLE_SIZE 0x20
43 #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
44 #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
45 #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
46 #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
47 #define XR3PCI_ATR_TRSL_PARAM 0x10
49 /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
50 #define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004)
51 #define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */
52 #define XR3PCI_ATR_TRSLID_PCIE_CONF (0x000001)
53 #define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000)
54 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000)
56 #define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \
57 (PCI_SLOT(d) << 15) | \
58 (PCI_FUNC(d) << 12) | o)
60 #define JUNO_RESET_CTRL 0x1004
61 #define JUNO_RESET_CTRL_PHY BIT(0)
62 #define JUNO_RESET_CTRL_RC BIT(1)
64 #define JUNO_RESET_STATUS 0x1008
65 #define JUNO_RESET_STATUS_PLL BIT(0)
66 #define JUNO_RESET_STATUS_PHY BIT(1)
67 #define JUNO_RESET_STATUS_RC BIT(2)
68 #define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \
69 JUNO_RESET_STATUS_PHY | \
72 void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
73 unsigned long trsl_addr, int window_size,
76 /* X3PCI_ATR_SRC_ADDR_LOW:
77 - bit 0: enable entry,
78 - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
80 - bits 12-31: start of source address
82 writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
83 base + XR3PCI_ATR_SRC_ADDR_LOW);
84 writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
85 writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
86 writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
87 writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
89 debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
90 src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
91 ((u64)1) << window_size, trsl_param);
94 void xr3pci_setup_atr(void)
96 /* setup PCIe to CPU address translation tables */
97 unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
99 /* forward all writes from PCIe to GIC V2M (used for MSI) */
100 xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
101 JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
103 base += XR3PCI_ATR_TABLE_SIZE;
105 /* PCIe devices can write anywhere in memory */
106 xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
107 31 /* grant access to all RAM under 4GB */,
108 XR3PCI_ATR_TRSLID_AXIMEMORY);
109 base += XR3PCI_ATR_TABLE_SIZE;
110 xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
111 XR3_PCI_MEMSPACE64_SIZE,
112 XR3PCI_ATR_TRSLID_AXIMEMORY);
115 /* setup CPU to PCIe address translation table */
116 base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
118 /* setup ECAM space to bus configuration interface */
119 xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
120 XR3PCI_ATR_TRSLID_PCIE_CONF);
122 base += XR3PCI_ATR_TABLE_SIZE;
124 /* setup IO space translation */
125 xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
126 XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
128 base += XR3PCI_ATR_TABLE_SIZE;
130 /* setup 32bit MEM space translation */
131 xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
132 XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
134 base += XR3PCI_ATR_TABLE_SIZE;
136 /* setup 64bit MEM space translation */
137 xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
138 XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
141 void xr3pci_init(void)
146 /* Initialise the XpressRICH3 PCIe host bridge */
149 writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
150 writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
152 writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
153 /* setup the correct class code for the host bridge */
154 writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
156 /* reset phy and root complex */
157 writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
158 XR3_RESET_BASE + JUNO_RESET_CTRL);
162 val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
163 } while (--timeout &&
164 (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
167 printf("PCI XR3 Root complex reset timed out\n");
171 /* Wait for the link to train */
177 val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
178 } while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
180 if (!(val & XR3PCI_BS_LINK_MASK)) {
181 printf("Failed to negotiate a link!\n");
185 printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
186 val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
191 void vexpress64_pcie_init(void)