1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
16 * Philippe Robin, <philippe.robin@arm.com>
19 #include <bootstage.h>
27 #include <asm/mach-types.h>
28 #include <asm/arch/systimer.h>
29 #include <asm/arch/sysctrl.h>
30 #include <asm/arch/wdt.h>
31 #include "../drivers/mmc/arm_pl180_mmci.h"
33 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
34 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
36 static void flash__init(void);
37 static void vexpress_timer_init(void);
38 DECLARE_GLOBAL_DATA_PTR;
40 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
41 void show_boot_progress(int progress)
43 printf("Boot reached stage %d\n", progress);
47 static inline void delay(ulong loops)
49 __asm__ volatile ("1:\n"
51 "bne 1b" : "=r" (loops) : "0" (loops));
56 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
57 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
62 vexpress_timer_init();
67 int board_eth_init(bd_t *bis)
71 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
76 int cpu_mmc_init(bd_t *bis)
80 #ifdef CONFIG_ARM_PL180_MMCI
81 struct pl180_mmc_host *host;
84 host = malloc(sizeof(struct pl180_mmc_host));
87 memset(host, 0, sizeof(*host));
89 strcpy(host->name, "MMC");
90 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
91 host->pwr_init = INIT_PWR;
92 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
93 host->voltages = VOLTAGE_WINDOW_MMC;
95 host->clock_in = ARM_MCLK;
96 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
97 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
98 rc = arm_pl180_mmci_init(host, &mmc);
103 static void flash__init(void)
105 /* Setup the sytem control register to allow writing to flash */
106 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
107 &sysctrl_base->scflashctrl);
113 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
117 int dram_init_banksize(void)
119 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
120 gd->bd->bi_dram[0].size =
121 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
122 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
123 gd->bd->bi_dram[1].size =
124 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
131 * Setup a 32 bit timer, running at 1KHz
132 * Versatile Express Motherboard provides 1 MHz timer
134 static void vexpress_timer_init(void)
137 * Set clock frequency in system controller:
138 * VEXPRESS_REFCLK is 32KHz
139 * VEXPRESS_TIMCLK is 1MHz
141 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
142 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
143 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
147 * Enabled, free running, no interrupt, 32-bit, wrapping
149 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
150 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
151 writel(SYSTIMER_EN | SYSTIMER_32BIT |
152 readl(&systimer_base->timer0control),
153 &systimer_base->timer0control);
156 int v2m_cfg_write(u32 devfn, u32 data)
158 /* Configuration interface broken? */
161 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
163 val = readl(V2M_SYS_CFGSTAT);
164 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
166 writel(data, V2M_SYS_CFGDATA);
167 writel(devfn, V2M_SYS_CFGCTRL);
170 val = readl(V2M_SYS_CFGSTAT);
173 return !!(val & SYS_CFG_ERR);
176 /* Use the ARM Watchdog System to cause reset */
177 void reset_cpu(ulong addr)
179 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
180 printf("Unable to reboot\n");
183 void lowlevel_init(void)
187 ulong get_board_rev(void){
188 return readl((u32 *)SYS_ID);
191 #ifdef CONFIG_ARMV7_NONSEC
192 /* Setting the address at which secondary cores start from.
193 * Versatile Express uses one address for all cores, so ignore corenr
195 void smp_set_core_boot_addr(unsigned long addr, int corenr)
197 /* The SYSFLAGS register on VExpress needs to be cleared first
198 * by writing to the next address, since any writes to the address
199 * at offset 0 will only be ORed in
201 writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
202 writel(addr, CONFIG_SYSFLAGS_ADDR);