3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
15 * Philippe Robin, <philippe.robin@arm.com>
17 * SPDX-License-Identifier: GPL-2.0+
23 #ifdef CONFIG_ARCH_CINTEGRATOR
24 #define DIV_CLOCK_INIT 1
25 #define TIMER_LOAD_VAL 0xFFFFFFFFL
27 #define DIV_CLOCK_INIT 256
28 #define TIMER_LOAD_VAL 0x0000FFFFL
30 /* The Integrator/CP timer1 is clocked at 1MHz
31 * can be divided by 16 or 256
32 * and can be set up as a 32-bit timer
34 /* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
35 /* Keep total timer count to avoid losing decrements < div_timer */
36 static unsigned long long total_count = 0;
37 static unsigned long long lastdec; /* Timer reading at last call */
38 /* Divisor applied to timer clock */
39 static unsigned long long div_clock = DIV_CLOCK_INIT;
40 static unsigned long long div_timer = 1; /* Divisor to convert timer reading
41 * change to U-Boot ticks
43 /* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
44 static ulong timestamp; /* U-Boot ticks since startup */
46 #define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
48 /* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
49 * - unless otherwise stated
52 /* starts up a counter
53 * - the Integrator/CP timer can be set up to issue an interrupt */
56 /* Load timer with initial value */
57 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
58 #ifdef CONFIG_ARCH_CINTEGRATOR
64 * divider 1 00 == less rounding error
68 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
77 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
80 /* init the timestamp */
82 /* capure current decrementer value */
84 /* start "advancing" time stamp from 0 */
87 div_timer = CONFIG_SYS_HZ_CLOCK;
88 do_div(div_timer, CONFIG_SYS_HZ);
89 do_div(div_timer, div_clock);
95 * timer without interrupts
97 ulong get_timer (ulong base_ticks)
99 return get_timer_masked () - base_ticks;
102 /* delay usec useconds */
103 void __udelay (unsigned long usec)
107 /* Convert to U-Boot ticks */
108 tmo = usec * CONFIG_SYS_HZ;
111 tmp = get_timer_masked(); /* get current timestamp */
112 tmo += tmp; /* form target timestamp */
114 while (get_timer_masked () < tmo) {/* loop till event */
119 /* converts the timer reading to U-Boot ticks */
120 /* the timestamp is the number of ticks since reset */
121 ulong get_timer_masked (void)
123 /* get current count */
124 unsigned long long now = READ_TIMER;
127 /* Must have wrapped */
128 total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
130 total_count += lastdec - now;
136 do_div(now, div_timer);
142 /* waits specified delay value and resets timestamp */
143 void udelay_masked (unsigned long usec)
149 * This function is derived from PowerPC code (read timebase as long long).
150 * On ARM it just returns the timer value.
152 unsigned long long get_ticks(void)
158 * Return the timebase clock frequency
159 * i.e. how often the timer decrements
161 ulong get_tbclk (void)
163 unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
165 do_div(tmp, div_clock);