1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
16 * Philippe Robin, <philippe.robin@arm.com>
20 #include <bootstage.h>
27 #include <armcoremodule.h>
28 #include <asm/global_data.h>
30 #include <dm/platform_data/serial_pl01x.h>
32 #include "integrator-sc.h"
33 #include <asm/mach-types.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 static const struct pl01x_serial_plat serial_plat = {
39 #ifdef CONFIG_ARCH_CINTEGRATOR
44 .clock = 0, /* Not used for PL010 */
48 U_BOOT_DRVINFO(integrator_serials) = {
49 .name = "serial_pl01x",
53 void peripheral_power_enable (void);
55 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
56 void show_boot_progress(int progress)
58 printf("Boot reached stage %d\n", progress);
62 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
65 * Miscellaneous platform dependent initialisations
72 /* arch number of Integrator Board */
73 #ifdef CONFIG_ARCH_CINTEGRATOR
74 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
76 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
79 /* adress of boot parameters */
80 gd->bd->bi_boot_params = 0x00000100;
82 #ifdef CONFIG_CM_REMAP
83 extern void cm_remap(void);
84 cm_remap(); /* remaps writeable memory to 0x00000000 */
87 #ifdef CONFIG_ARCH_CINTEGRATOR
89 * Flash protection on the Integrator/CP is in a simple register
91 val = readl(CP_FLASHPROG);
92 val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
93 writel(val, CP_FLASHPROG);
96 * The Integrator/AP has some special protection mechanisms
97 * for the external memories, first the External Bus Interface (EBI)
98 * then the system controller (SC).
100 * The system comes up with the flash memory non-writable and
101 * configuration locked. If we want U-Boot to be used for flash
102 * access we cannot have the flash memory locked.
104 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
105 val = readl(EBI_BASE + EBI_CSR1_REG);
106 val &= EBI_CSR_WREN_MASK;
107 val |= EBI_CSR_WREN_ENABLE;
108 writel(val, EBI_BASE + EBI_CSR1_REG);
109 writel(0, EBI_BASE + EBI_LOCK_REG);
112 * Set up the system controller to remove write protection from
113 * the flash memory and enable Vpp
115 writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
123 int misc_init_r (void)
125 env_set("verify", "n");
130 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
131 * from there, which means we cannot test the RAM underneath the ROM at this
132 * point. It will be unmapped later on, when we are executing from the
133 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
134 * RAM on higher addresses works fine.
136 #define REMAPPED_FLASH_SZ 0x40000
140 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
141 #ifdef CONFIG_CM_SPD_DETECT
143 extern void dram_query(void);
147 dram_query(); /* Assembler accesses to CM registers */
148 /* Queries the SPD values */
150 /* Obtain the SDRAM size from the CM SDRAM register */
152 cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
153 /* Register SDRAM size
155 * 0xXXXXXXbbb000bb 16 MB
156 * 0xXXXXXXbbb001bb 32 MB
157 * 0xXXXXXXbbb010bb 64 MB
158 * 0xXXXXXXbbb011bb 128 MB
159 * 0xXXXXXXbbb100bb 256 MB
162 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
163 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
165 0x01000000 << sdram_shift);
168 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
171 #endif /* CM_SPD_DETECT */
172 /* We only have one bank of RAM, set it to whatever was detected */
173 gd->bd->bi_dram[0].size = gd->ram_size;
178 #ifdef CONFIG_CMD_NET
179 int board_eth_init(struct bd_info *bis)
182 #ifdef CONFIG_SMC91111
183 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);