1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
16 * Philippe Robin, <philippe.robin@arm.com>
20 #include <bootstage.h>
28 #include <dm/platform_data/serial_pl01x.h>
30 #include "integrator-sc.h"
31 #include <asm/mach-types.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 static const struct pl01x_serial_platdata serial_platdata = {
37 #ifdef CONFIG_ARCH_CINTEGRATOR
42 .clock = 0, /* Not used for PL010 */
46 U_BOOT_DEVICE(integrator_serials) = {
47 .name = "serial_pl01x",
48 .platdata = &serial_platdata,
51 void peripheral_power_enable (void);
53 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
54 void show_boot_progress(int progress)
56 printf("Boot reached stage %d\n", progress);
60 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
63 * Miscellaneous platform dependent initialisations
70 /* arch number of Integrator Board */
71 #ifdef CONFIG_ARCH_CINTEGRATOR
72 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
74 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
77 /* adress of boot parameters */
78 gd->bd->bi_boot_params = 0x00000100;
80 #ifdef CONFIG_CM_REMAP
81 extern void cm_remap(void);
82 cm_remap(); /* remaps writeable memory to 0x00000000 */
85 #ifdef CONFIG_ARCH_CINTEGRATOR
87 * Flash protection on the Integrator/CP is in a simple register
89 val = readl(CP_FLASHPROG);
90 val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
91 writel(val, CP_FLASHPROG);
94 * The Integrator/AP has some special protection mechanisms
95 * for the external memories, first the External Bus Interface (EBI)
96 * then the system controller (SC).
98 * The system comes up with the flash memory non-writable and
99 * configuration locked. If we want U-Boot to be used for flash
100 * access we cannot have the flash memory locked.
102 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
103 val = readl(EBI_BASE + EBI_CSR1_REG);
104 val &= EBI_CSR_WREN_MASK;
105 val |= EBI_CSR_WREN_ENABLE;
106 writel(val, EBI_BASE + EBI_CSR1_REG);
107 writel(0, EBI_BASE + EBI_LOCK_REG);
110 * Set up the system controller to remove write protection from
111 * the flash memory and enable Vpp
113 writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
121 int misc_init_r (void)
123 env_set("verify", "n");
128 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
129 * from there, which means we cannot test the RAM underneath the ROM at this
130 * point. It will be unmapped later on, when we are executing from the
131 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
132 * RAM on higher addresses works fine.
134 #define REMAPPED_FLASH_SZ 0x40000
138 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
139 #ifdef CONFIG_CM_SPD_DETECT
141 extern void dram_query(void);
145 dram_query(); /* Assembler accesses to CM registers */
146 /* Queries the SPD values */
148 /* Obtain the SDRAM size from the CM SDRAM register */
150 cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
151 /* Register SDRAM size
153 * 0xXXXXXXbbb000bb 16 MB
154 * 0xXXXXXXbbb001bb 32 MB
155 * 0xXXXXXXbbb010bb 64 MB
156 * 0xXXXXXXbbb011bb 128 MB
157 * 0xXXXXXXbbb100bb 256 MB
160 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
161 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
163 0x01000000 << sdram_shift);
166 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
169 #endif /* CM_SPD_DETECT */
170 /* We only have one bank of RAM, set it to whatever was detected */
171 gd->bd->bi_dram[0].size = gd->ram_size;
176 #ifdef CONFIG_CMD_NET
177 int board_eth_init(bd_t *bis)
180 #ifdef CONFIG_SMC91111
181 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
183 rc += pci_eth_init(bis);