board/armadeus/apf27/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
   4  */
   5
   6 #include <config.h>
   7 #include <generated/asm-offsets.h>
   8 #include <asm/macro.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include "apf27.h"
  11
  12         .macro init_aipi
  13         /*
  14          * setup AIPI1 and AIPI2
  15          */
  16         write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
  17         write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
  18         write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
  19         write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
  20
  21         /* Change SDRAM signal strengh */
  22         ldr r0, =GPCR
  23         ldr r1, =ACFG_GPCR_VAL
  24         ldr r5, [r0]
  25         orr r5, r5, r1
  26         str r5, [r0]
  27
  28         .endm /* init_aipi */
  29
  30         .macro init_clock
  31         ldr r0, =CSCR
  32         /* disable MPLL/SPLL first */
  33         ldr r1, [r0]
  34         bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
  35         str r1, [r0]
  36
  37         /*
  38          * pll clock initialization predefined in apf27.h
  39          */
  40         write32 MPCTL0, ACFG_MPCTL0_VAL
  41         write32 SPCTL0, ACFG_SPCTL0_VAL
  42
  43         write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
  44
  45         /*
  46          * add some delay here
  47          */
  48         mov r1, #0x1000
  49         1:  subs r1, r1, #0x1
  50         bne 1b
  51
  52         /* peripheral clock divider */
  53         write32 PCDR0, ACFG_PCDR0_VAL
  54         write32 PCDR1, ACFG_PCDR1_VAL
  55
  56         /* Configure PCCR0 and PCCR1 */
  57         write32 PCCR0, ACFG_PCCR0_VAL
  58         write32 PCCR1, ACFG_PCCR1_VAL
  59
  60         .endm /* init_clock */
  61
  62         .macro init_ddr
  63         /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
  64         ldr             r0, =IMX_ESD_BASE
  65         ldr             r4, =ESDMISC_SDRAM_RDY
  66 2:      ldr             r1, [r0, #ESDMISC_ROF]
  67         ands            r1, r1, r4
  68         bpl             2b
  69
  70         /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
  71         ldr             r0, =IMX_ESD_BASE
  72         ldr             r4, =ACFG_ESDMISC_VAL
  73         orr             r1, r4, #ESDMISC_MDDR_DL_RST
  74         str             r1, [r0, #ESDMISC_ROF]
  75
  76         /* Hold for more than 200ns */
  77         ldr             r1, =0x10000
  78 1:      subs            r1, r1, #0x1
  79         bne             1b
  80
  81         str             r4, [r0]
  82
  83         ldr             r0, =IMX_ESD_BASE
  84         ldr             r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
  85         str             r1, [r0, #ESDCFG0_ROF]
  86
  87         ldr             r0, =IMX_ESD_BASE
  88         ldr             r1, =ACFG_PRECHARGE_CMD
  89         str             r1, [r0, #ESDCTL0_ROF]
  90
  91         /* write8(0xA0001000, any value) */
  92         ldr             r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
  93         strb            r2, [r1]
  94
  95         ldr             r1, =ACFG_AUTOREFRESH_CMD
  96         str             r1, [r0, #ESDCTL0_ROF]
  97
  98         ldr             r4, =PHYS_SDRAM_1       /* CSD0 base address    */
  99
 100         ldr             r6,=0x7         /* load loop counter    */
 101 1:      str             r5,[r4]         /* run auto-refresh cycle to array 0 */
 102         subs            r6,r6,#1
 103         bne 1b
 104
 105         ldr             r1, =ACFG_SET_MODE_REG_CMD
 106         str             r1, [r0, #ESDCTL0_ROF]
 107
 108         /* set standard mode register */
 109         ldr             r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
 110         strb            r2, [r4]
 111
 112         /* set extended mode register */
 113         ldr             r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
 114         strb            r5, [r4]
 115
 116         ldr             r1, =ACFG_NORMAL_RW_CMD
 117         str             r1, [r0, #ESDCTL0_ROF]
 118
 119         /* 2nd sdram */
 120         ldr             r0, =IMX_ESD_BASE
 121         ldr             r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
 122         str             r1, [r0, #ESDCFG1_ROF]
 123
 124         ldr             r0, =IMX_ESD_BASE
 125         ldr             r1, =ACFG_PRECHARGE_CMD
 126         str             r1, [r0, #ESDCTL1_ROF]
 127
 128         /* write8(0xB0001000, any value) */
 129         ldr             r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
 130         strb            r2, [r1]
 131
 132         ldr             r1, =ACFG_AUTOREFRESH_CMD
 133         str             r1, [r0, #ESDCTL1_ROF]
 134
 135         ldr             r4, =PHYS_SDRAM_2       /* CSD1 base address */
 136
 137         ldr             r6,=0x7         /* load loop counter */
 138 1:      str             r5,[r4]         /* run auto-refresh cycle to array 0 */
 139         subs            r6,r6,#1
 140         bne 1b
 141
 142         ldr             r1, =ACFG_SET_MODE_REG_CMD
 143         str             r1, [r0, #ESDCTL1_ROF]
 144
 145         /* set standard mode register */
 146         ldr             r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
 147         strb            r2, [r4]
 148
 149         /* set extended mode register */
 150         ldr             r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
 151         strb            r2, [r4]
 152
 153         ldr             r1, =ACFG_NORMAL_RW_CMD
 154         str             r1, [r0, #ESDCTL1_ROF]
 155         .endm /* init_ddr */
 156
 157 .globl lowlevel_init
 158 lowlevel_init:
 159
 160         init_aipi
 161         init_clock
 162 #ifdef CONFIG_SPL_BUILD
 163         init_ddr
 164 #endif
 165
 166         mov     pc, lr