1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * Author: Fabio Estevam <fabio.estevam@freescale.com>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <linux/errno.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/sys_proto.h>
27 #include <i2c_eeprom.h>
33 #include <power/pmic.h>
34 #include <power/regulator.h>
35 #include <power/da9063_pmic.h>
39 DECLARE_GLOBAL_DATA_PTR;
46 #define ARI_BT_4 "aristainetos2_4@2"
47 #define ARI_BT_7 "aristainetos2_7@1"
49 int board_phy_config(struct phy_device *phydev)
51 /* control data pad skew - devaddr = 0x02, register = 0x04 */
52 ksz9031_phy_extended_write(phydev, 0x02,
53 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
54 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
55 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
56 ksz9031_phy_extended_write(phydev, 0x02,
57 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
58 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
59 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
60 ksz9031_phy_extended_write(phydev, 0x02,
61 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
62 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
63 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
64 ksz9031_phy_extended_write(phydev, 0x02,
65 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
66 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
68 if (phydev->drv->config)
69 phydev->drv->config(phydev);
74 static int rotate_logo_one(unsigned char *out, unsigned char *in)
78 for (i = 0; i < BMP_LOGO_WIDTH; i++)
79 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
80 out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
81 in[i * BMP_LOGO_WIDTH + j];
86 * Rotate the BMP_LOGO (only)
87 * Will only work, if the logo is square, as
88 * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
90 void rotate_logo(int rotations)
92 unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
93 struct bmp_header *header;
94 unsigned char *in_logo;
97 if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
100 header = (struct bmp_header *)bmp_logo_bitmap;
101 in_logo = bmp_logo_bitmap + header->data_offset;
103 /* one 90 degree rotation */
104 if (rotations == 1 || rotations == 2 || rotations == 3)
105 rotate_logo_one(out_logo, in_logo);
107 /* second 90 degree rotation */
108 if (rotations == 2 || rotations == 3)
109 rotate_logo_one(in_logo, out_logo);
111 /* third 90 degree rotation */
113 rotate_logo_one(out_logo, in_logo);
115 /* copy result back to original array */
116 if (rotations == 1 || rotations == 3)
117 for (i = 0; i < BMP_LOGO_WIDTH; i++)
118 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
119 in_logo[i * BMP_LOGO_WIDTH + j] =
120 out_logo[i * BMP_LOGO_WIDTH + j];
123 static void enable_lvds(struct display_info_t const *dev)
125 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
126 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
128 s32 timeout = 100000;
131 reg = readl(&ccm->analog_pll_video);
132 reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
133 writel(reg, &ccm->analog_pll_video);
135 /* set PLL5 to 232720000Hz */
136 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
137 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
138 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
139 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
140 writel(reg, &ccm->analog_pll_video);
142 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
143 &ccm->analog_pll_video_num);
144 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
145 &ccm->analog_pll_video_denom);
147 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
148 writel(reg, &ccm->analog_pll_video);
151 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
154 printf("Warning: video pll lock timeout!\n");
156 reg = readl(&ccm->analog_pll_video);
157 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
158 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
159 writel(reg, &ccm->analog_pll_video);
161 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
162 reg = readl(&ccm->cs2cdr);
163 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
164 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
165 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
166 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
167 writel(reg, &ccm->cs2cdr);
169 reg = readl(&ccm->cscmr2);
170 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
171 writel(reg, &ccm->cscmr2);
173 reg = readl(&ccm->chsccdr);
174 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
175 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
176 writel(reg, &ccm->chsccdr);
178 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
179 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
180 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
181 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
182 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
183 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
184 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
185 writel(reg, &iomux->gpr[2]);
187 reg = readl(&iomux->gpr[3]);
188 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
189 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
190 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
191 writel(reg, &iomux->gpr[3]);
194 static void enable_spi_display(struct display_info_t const *dev)
196 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
197 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
199 s32 timeout = 100000;
201 #if defined(CONFIG_VIDEO_BMP_LOGO)
202 rotate_logo(3); /* portrait display in landscape mode */
205 reg = readl(&ccm->cs2cdr);
207 /* select pll 5 clock */
208 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
209 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
210 writel(reg, &ccm->cs2cdr);
212 /* set PLL5 to 197994996Hz */
213 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
214 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
215 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
216 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
217 writel(reg, &ccm->analog_pll_video);
219 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
220 &ccm->analog_pll_video_num);
221 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
222 &ccm->analog_pll_video_denom);
224 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
225 writel(reg, &ccm->analog_pll_video);
228 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
231 printf("Warning: video pll lock timeout!\n");
233 reg = readl(&ccm->analog_pll_video);
234 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
235 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
236 writel(reg, &ccm->analog_pll_video);
238 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
239 reg = readl(&ccm->cs2cdr);
240 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
241 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
242 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
243 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
244 writel(reg, &ccm->cs2cdr);
246 reg = readl(&ccm->cscmr2);
247 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
248 writel(reg, &ccm->cscmr2);
250 reg = readl(&ccm->chsccdr);
251 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
252 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
253 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
254 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
255 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
256 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
257 writel(reg, &ccm->chsccdr);
259 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
260 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
261 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
262 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
263 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
264 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
265 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
266 writel(reg, &iomux->gpr[2]);
268 reg = readl(&iomux->gpr[3]);
269 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
270 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
271 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
272 writel(reg, &iomux->gpr[3]);
275 static void setup_display(void)
280 static void set_gpr_register(void)
282 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
284 writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
285 IOMUXC_GPR1_EXC_MON_SLVE |
286 (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
288 &iomuxc_regs->gpr[1]);
289 writel(0x0, &iomuxc_regs->gpr[8]);
290 writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
291 IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
292 &iomuxc_regs->gpr[12]);
295 extern char __bss_start[], __bss_end[];
296 int board_early_init_f(void)
298 select_ldb_di_clock_source(MXC_PLL5_CLK);
302 * clear bss here, so we can use spi driver
303 * before relocation and read Environment
306 memset(__bss_start, 0x00, __bss_end - __bss_start);
311 static void setup_one_led(char *label, int state)
316 ret = led_get_by_label(label, &dev);
318 led_set_state(dev, state);
321 static void setup_board_gpio(void)
323 setup_one_led("led_ena", LEDST_ON);
324 /* switch off Status LEDs */
325 setup_one_led("led_yellow", LEDST_OFF);
326 setup_one_led("led_red", LEDST_OFF);
327 setup_one_led("led_green", LEDST_OFF);
328 setup_one_led("led_blue", LEDST_OFF);
331 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
334 static void aristainetos_run_rescue_command(int reason)
336 char rescue_reason_command[80];
338 sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
339 run_command(rescue_reason_command, 0);
342 static int aristainetos_eeprom(void)
350 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
352 printf("%s: No eeprom0 path offset\n", __func__);
356 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
358 printf("%s: Could not find EEPROM\n", __func__);
362 ret = i2c_set_chip_offset_len(dev, 2);
366 ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
368 printf("%s: Could not read EEPROM\n", __func__);
372 if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
373 rescue_reason = *(uint8_t *)&data[9];
374 memset(&data[3], 0xff, 7);
375 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
376 printf("\nBooting into Rescue System (EEPROM)\n");
377 aristainetos_run_rescue_command(rescue_reason);
378 run_command("run rescue_load_fit rescueboot", 0);
379 } else if (strncmp((char *)data, "DeF", 3) == 0) {
380 memset(data, 0xff, 3);
381 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
382 printf("\nClear u-boot environment (set back to defaults)\n");
383 run_command("run default_env; saveenv; saveenv", 0);
389 static void aristainetos_bootmode_settings(void)
391 struct gpio_desc *desc;
392 struct src *psrc = (struct src *)SRC_BASE_ADDR;
393 unsigned int sbmr1 = readl(&psrc->sbmr1);
399 * Check the boot-source. If booting from NOR Flash,
402 ret = gpio_hog_lookup_name("bootsel0", &desc);
404 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
405 ret = gpio_hog_lookup_name("bootsel1", &desc);
407 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
408 ret = gpio_hog_lookup_name("bootsel2", &desc);
410 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
413 my_bootdelay = env_get("nor_bootdelay");
415 env_set("bootdelay", my_bootdelay);
417 env_set("bootdelay", "-2");
421 env_set("bootmode", "1");
422 printf("SD bootmode jumper set!\n");
424 env_set("bootmode", "0");
427 /* read out some jumper values*/
428 ret = gpio_hog_lookup_name("env_reset", &desc);
430 if (dm_gpio_get_value(desc)) {
431 printf("\nClear env (set back to defaults)\n");
432 run_command("run default_env; saveenv; saveenv", 0);
435 ret = gpio_hog_lookup_name("boot_rescue", &desc);
437 if (dm_gpio_get_value(desc)) {
438 aristainetos_run_rescue_command(16);
439 run_command("run rescue_xload_boot", 0);
444 #if defined(CONFIG_DM_PMIC_DA9063)
446 * On the aristainetos2c boards the PMIC needs to be initialized,
447 * because the Ethernet PHY uses a different regulator that is not
448 * setup per hardware default. This does not influence the other versions
449 * as this regulator isn't used there at all.
451 * Unfortunately we have not yet a interface to setup all
454 static int setup_pmic_voltages(void)
460 off = fdt_path_offset(gd->fdt_blob, "pmic0");
462 printf("%s: No pmic path offset\n", __func__);
466 ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
468 printf("%s: Could not find PMIC\n", __func__);
472 pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
473 pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
474 ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
476 printf("%s: error %d get register\n", __func__, ret);
481 pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
482 pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
483 pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
488 static int setup_pmic_voltages(void)
494 int board_late_init(void)
499 splash_get_pos(&x, &y);
500 bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
502 aristainetos_bootmode_settings();
505 aristainetos_eeprom();
508 if (gd->board_type == BOARD_TYPE_4)
509 env_set("board_type", ARI_BT_4);
511 env_set("board_type", ARI_BT_7);
513 if (setup_pmic_voltages())
514 printf("Error setup PMIC\n");
521 gd->ram_size = imx_ddr_size();
526 struct display_info_t const displays[] = {
530 .pixfmt = IPU_PIX_FMT_RGB24,
532 .enable = enable_lvds,
546 .vmode = FB_VMODE_NONINTERLACED
549 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
550 (CONFIG_SYS_BOARD_VERSION == 3) || \
551 (CONFIG_SYS_BOARD_VERSION == 4) || \
552 (CONFIG_SYS_BOARD_VERSION == 5))
556 .pixfmt = IPU_PIX_FMT_RGB24,
558 .enable = enable_spi_display,
571 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
572 FB_SYNC_VERT_HIGH_ACT,
573 .vmode = FB_VMODE_NONINTERLACED
578 size_t display_count = ARRAY_SIZE(displays);
580 #if defined(CONFIG_MTD_RAW_NAND)
581 iomux_v3_cfg_t nfc_pads[] = {
582 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
583 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
584 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
585 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
586 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
587 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
588 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
589 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
590 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
591 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
592 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
593 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
594 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
595 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
596 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
597 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
600 static void setup_gpmi_nand(void)
602 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
604 /* config gpmi nand iomux */
605 imx_iomux_v3_setup_multiple_pads(nfc_pads,
606 ARRAY_SIZE(nfc_pads));
608 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
609 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
611 /* config gpmi and bch clock to 100 MHz */
612 clrsetbits_le32(&mxc_ccm->cs2cdr,
613 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
614 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
615 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
616 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
617 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
618 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
620 /* enable ENFC_CLK_ROOT clock */
621 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
623 /* enable gpmi and bch clock gating */
624 setbits_le32(&mxc_ccm->CCGR4,
625 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
626 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
627 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
628 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
629 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
631 /* enable apbh clock gating */
632 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
635 static void setup_gpmi_nand(void)
642 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
644 /* address of boot parameters */
645 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
651 /* GPIO_1 for USB_OTG_ID */
652 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
656 int board_fit_config_name_match(const char *name)
658 if (gd->board_type == BOARD_TYPE_4 &&
662 if (gd->board_type == BOARD_TYPE_7 &&
669 static void do_board_detect(void)
674 /* default use board type 7 */
675 gd->board_type = BOARD_TYPE_7;
679 ret = env_get_f("panel", s, sizeof(s));
683 if (!strncmp("lg4573", s, 6))
684 gd->board_type = BOARD_TYPE_4;
687 #ifdef CONFIG_DTB_RESELECT
688 int embedded_dtb_select(void)
693 fdtdec_resetup(&rescan);