board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <command.h>
  13 #include <image.h>
  14 #include <init.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/global_data.h>
  20 #include <linux/errno.h>
  21 #include <asm/gpio.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <bmp_logo.h>
  29 #include <dm/root.h>
  30 #include <env.h>
  31 #include <env_internal.h>
  32 #include <i2c_eeprom.h>
  33 #include <i2c.h>
  34 #include <micrel.h>
  35 #include <miiphy.h>
  36 #include <lcd.h>
  37 #include <led.h>
  38 #include <power/pmic.h>
  39 #include <power/regulator.h>
  40 #include <power/da9063_pmic.h>
  41 #include <splash.h>
  42 #include <video_fb.h>
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 enum {
  47         BOARD_TYPE_4 = 4,
  48         BOARD_TYPE_7 = 7,
  49 };
  50
  51 #define ARI_BT_4 "aristainetos2_4@2"
  52 #define ARI_BT_7 "aristainetos2_7@1"
  53
  54 int board_phy_config(struct phy_device *phydev)
  55 {
  56         /* control data pad skew - devaddr = 0x02, register = 0x04 */
  57         ksz9031_phy_extended_write(phydev, 0x02,
  58                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  59                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  60         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  61         ksz9031_phy_extended_write(phydev, 0x02,
  62                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  63                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  64         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  65         ksz9031_phy_extended_write(phydev, 0x02,
  66                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  67                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  68         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  69         ksz9031_phy_extended_write(phydev, 0x02,
  70                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  71                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  72
  73         if (phydev->drv->config)
  74                 phydev->drv->config(phydev);
  75
  76         return 0;
  77 }
  78
  79 static int rotate_logo_one(unsigned char *out, unsigned char *in)
  80 {
  81         int   i, j;
  82
  83         for (i = 0; i < BMP_LOGO_WIDTH; i++)
  84                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  85                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  86                         in[i * BMP_LOGO_WIDTH + j];
  87         return 0;
  88 }
  89
  90 /*
  91  * Rotate the BMP_LOGO (only)
  92  * Will only work, if the logo is square, as
  93  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  94  */
  95 void rotate_logo(int rotations)
  96 {
  97         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  98         struct bmp_header *header;
  99         unsigned char *in_logo;
 100         int   i, j;
 101
 102         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 103                 return;
 104
 105         header = (struct bmp_header *)bmp_logo_bitmap;
 106         in_logo = bmp_logo_bitmap + header->data_offset;
 107
 108         /* one 90 degree rotation */
 109         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 110                 rotate_logo_one(out_logo, in_logo);
 111
 112         /* second 90 degree rotation */
 113         if (rotations == 2  ||  rotations == 3)
 114                 rotate_logo_one(in_logo, out_logo);
 115
 116         /* third 90 degree rotation */
 117         if (rotations == 3)
 118                 rotate_logo_one(out_logo, in_logo);
 119
 120         /* copy result back to original array */
 121         if (rotations == 1  ||  rotations == 3)
 122                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 123                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 124                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 125                                 out_logo[i * BMP_LOGO_WIDTH + j];
 126 }
 127
 128 static void enable_lvds(struct display_info_t const *dev)
 129 {
 130         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 131         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 132         int reg;
 133         s32 timeout = 100000;
 134
 135         /* set PLL5 clock */
 136         reg = readl(&ccm->analog_pll_video);
 137         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 138         writel(reg, &ccm->analog_pll_video);
 139
 140         /* set PLL5 to 232720000Hz */
 141         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 142         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 143         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 144         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 145         writel(reg, &ccm->analog_pll_video);
 146
 147         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 148                &ccm->analog_pll_video_num);
 149         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 150                &ccm->analog_pll_video_denom);
 151
 152         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 153         writel(reg, &ccm->analog_pll_video);
 154
 155         while (timeout--)
 156                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 157                         break;
 158         if (timeout < 0)
 159                 printf("Warning: video pll lock timeout!\n");
 160
 161         reg = readl(&ccm->analog_pll_video);
 162         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 163         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 164         writel(reg, &ccm->analog_pll_video);
 165
 166         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 167         reg = readl(&ccm->cs2cdr);
 168         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 169                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 170         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 171                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 172         writel(reg, &ccm->cs2cdr);
 173
 174         reg = readl(&ccm->cscmr2);
 175         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 176         writel(reg, &ccm->cscmr2);
 177
 178         reg = readl(&ccm->chsccdr);
 179         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 180                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 181         writel(reg, &ccm->chsccdr);
 182
 183         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 184               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 185               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 186               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 187               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 188               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 189               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 190         writel(reg, &iomux->gpr[2]);
 191
 192         reg = readl(&iomux->gpr[3]);
 193         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 194                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 195                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 196         writel(reg, &iomux->gpr[3]);
 197 }
 198
 199 static void setup_display(void)
 200 {
 201         enable_ipu_clock();
 202 }
 203
 204 static void set_gpr_register(void)
 205 {
 206         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 207
 208         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 209                IOMUXC_GPR1_EXC_MON_SLVE |
 210                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 211                IOMUXC_GPR1_ACT_CS0,
 212                &iomuxc_regs->gpr[1]);
 213         writel(0x0, &iomuxc_regs->gpr[8]);
 214         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 215                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 216                &iomuxc_regs->gpr[12]);
 217 }
 218
 219 extern char __bss_start[], __bss_end[];
 220 int board_early_init_f(void)
 221 {
 222         select_ldb_di_clock_source(MXC_PLL5_CLK);
 223         set_gpr_register();
 224
 225         /*
 226          * clear bss here, so we can use spi driver
 227          * before relocation and read Environment
 228          * from spi flash.
 229          */
 230         memset(__bss_start, 0x00, __bss_end - __bss_start);
 231
 232         return 0;
 233 }
 234
 235 static void setup_one_led(char *label, int state)
 236 {
 237         struct udevice *dev;
 238         int ret;
 239
 240         ret = led_get_by_label(label, &dev);
 241         if (ret == 0)
 242                 led_set_state(dev, state);
 243 }
 244
 245 static void setup_board_gpio(void)
 246 {
 247         setup_one_led("led_ena", LEDST_ON);
 248         /* switch off Status LEDs */
 249         setup_one_led("led_yellow", LEDST_OFF);
 250         setup_one_led("led_red", LEDST_OFF);
 251         setup_one_led("led_green", LEDST_OFF);
 252         setup_one_led("led_blue", LEDST_OFF);
 253 }
 254
 255 static void aristainetos_run_rescue_command(int reason)
 256 {
 257         char rescue_reason_command[20];
 258
 259         sprintf(rescue_reason_command, "setenv rreason %d", reason);
 260         run_command(rescue_reason_command, 0);
 261 }
 262
 263 static int aristainetos_bootmode_settings(void)
 264 {
 265         struct gpio_desc *desc;
 266         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 267         unsigned int sbmr1 = readl(&psrc->sbmr1);
 268         char *my_bootdelay;
 269         char bootmode = 0;
 270         int ret;
 271         struct udevice *dev;
 272         int off;
 273         u8 data[0x10];
 274         u8 rescue_reason;
 275
 276         /* jumper controlled reset of the environment */
 277         ret = gpio_hog_lookup_name("env_reset", &desc);
 278         if (!ret) {
 279                 if (dm_gpio_get_value(desc)) {
 280                         printf("\nReset u-boot environment (jumper)\n");
 281                         run_command("run default_env; saveenv; saveenv", 0);
 282                 }
 283         }
 284
 285         off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 286         if (off < 0) {
 287                 printf("%s: No eeprom0 path offset\n", __func__);
 288                 return off;
 289         }
 290
 291         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 292         if (ret) {
 293                 printf("%s: Could not find EEPROM\n", __func__);
 294                 return ret;
 295         }
 296
 297         ret = i2c_set_chip_offset_len(dev, 2);
 298         if (ret)
 299                 return ret;
 300
 301         ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
 302         if (ret) {
 303                 printf("%s: Could not read EEPROM\n", __func__);
 304                 return ret;
 305         }
 306
 307         /* software controlled reset of the environment (EEPROM magic) */
 308         if (strncmp((char *)data, "DeF", 3) == 0) {
 309                 memset(data, 0xff, 3);
 310                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
 311                 printf("\nReset u-boot environment (EEPROM)\n");
 312                 run_command("run default_env; saveenv; saveenv", 0);
 313         }
 314
 315         if (sbmr1 & 0x40) {
 316                 env_set("bootmode", "1");
 317                 printf("SD bootmode jumper set!\n");
 318         } else {
 319                 env_set("bootmode", "0");
 320         }
 321
 322         /*
 323          * Check the boot-source. If booting from NOR Flash,
 324          * disable bootdelay
 325          */
 326         ret = gpio_hog_lookup_name("bootsel0", &desc);
 327         if (!ret)
 328                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 329         ret = gpio_hog_lookup_name("bootsel1", &desc);
 330         if (!ret)
 331                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 332         ret = gpio_hog_lookup_name("bootsel2", &desc);
 333         if (!ret)
 334                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 335
 336         if (bootmode == 7) {
 337                 my_bootdelay = env_get("nor_bootdelay");
 338                 if (my_bootdelay)
 339                         env_set("bootdelay", my_bootdelay);
 340                 else
 341                         env_set("bootdelay", "-2");
 342         }
 343
 344         /* jumper controlled boot of the rescue system */
 345         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 346         if (!ret) {
 347                 if (dm_gpio_get_value(desc)) {
 348                         printf("\nBooting into Rescue System (jumper)\n");
 349                         aristainetos_run_rescue_command(16);
 350                         run_command("run rescue_xload_boot", 0);
 351                 }
 352         }
 353
 354         /* software controlled boot of the rescue system (EEPROM magic) */
 355         if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
 356                 rescue_reason = *(uint8_t *)&data[9];
 357                 memset(&data[3], 0xff, 7);
 358                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
 359                 printf("\nBooting into Rescue System (EEPROM)\n");
 360                 aristainetos_run_rescue_command(rescue_reason);
 361                 run_command("run rescue_xload_boot", 0);
 362         }
 363
 364         return 0;
 365 }
 366
 367 #if defined(CONFIG_DM_PMIC_DA9063)
 368 /*
 369  * On the aristainetos2c boards the PMIC needs to be initialized,
 370  * because the Ethernet PHY uses a different regulator that is not
 371  * setup per hardware default. This does not influence the other versions
 372  * as this regulator isn't used there at all.
 373  *
 374  * Unfortunately we have not yet a interface to setup all
 375  * values we need.
 376  */
 377 static int setup_pmic_voltages(void)
 378 {
 379         struct udevice *dev;
 380         int off;
 381         int ret;
 382
 383         off = fdt_path_offset(gd->fdt_blob, "pmic0");
 384         if (off < 0) {
 385                 printf("%s: No pmic path offset\n", __func__);
 386                 return off;
 387         }
 388
 389         ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
 390         if (ret) {
 391                 printf("%s: Could not find PMIC\n", __func__);
 392                 return ret;
 393         }
 394
 395         pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
 396         pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
 397         ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
 398         if (ret < 0) {
 399                 printf("%s: error %d get register\n", __func__, ret);
 400                 return ret;
 401         }
 402         ret &= 0xf0;
 403         ret |= 0x09;
 404         pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
 405         pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
 406         pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
 407
 408         return 0;
 409 }
 410 #else
 411 static int setup_pmic_voltages(void)
 412 {
 413         return 0;
 414 }
 415 #endif
 416
 417 int board_late_init(void)
 418 {
 419         int x, y;
 420         int ret;
 421
 422         led_default_state();
 423         splash_get_pos(&x, &y);
 424         bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 425
 426         ret = aristainetos_bootmode_settings();
 427         if (ret)
 428                 return ret;
 429
 430         /* set board_type */
 431         if (gd->board_type == BOARD_TYPE_4)
 432                 env_set("board_type", ARI_BT_4);
 433         else
 434                 env_set("board_type", ARI_BT_7);
 435
 436         if (setup_pmic_voltages())
 437                 printf("Error setup PMIC\n");
 438
 439         return 0;
 440 }
 441
 442 int dram_init(void)
 443 {
 444         gd->ram_size = imx_ddr_size();
 445
 446         return 0;
 447 }
 448
 449 struct display_info_t const displays[] = {
 450         {
 451                 .bus    = -1,
 452                 .addr   = 0,
 453                 .pixfmt = IPU_PIX_FMT_RGB24,
 454                 .detect = NULL,
 455                 .enable = enable_lvds,
 456                 .mode   = {
 457                         .name           = "lb07wv8",
 458                         .refresh        = 60,
 459                         .xres           = 800,
 460                         .yres           = 480,
 461                         .pixclock       = 30066,
 462                         .left_margin    = 88,
 463                         .right_margin   = 88,
 464                         .upper_margin   = 20,
 465                         .lower_margin   = 20,
 466                         .hsync_len      = 80,
 467                         .vsync_len      = 5,
 468                         .sync           = FB_SYNC_EXT,
 469                         .vmode          = FB_VMODE_NONINTERLACED
 470                 }
 471         }
 472 };
 473 size_t display_count = ARRAY_SIZE(displays);
 474
 475 int board_init(void)
 476 {
 477         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 478
 479         /* address of boot parameters */
 480         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 481
 482         setup_board_gpio();
 483         setup_display();
 484
 485         /* GPIO_1 for USB_OTG_ID */
 486         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 487         return 0;
 488 }
 489
 490 int board_fit_config_name_match(const char *name)
 491 {
 492         if (gd->board_type == BOARD_TYPE_4 &&
 493             strchr(name, 0x34))
 494                 return 0;
 495
 496         if (gd->board_type == BOARD_TYPE_7 &&
 497             strchr(name, 0x37))
 498                 return 0;
 499
 500         return -1;
 501 }
 502
 503 static void do_board_detect(void)
 504 {
 505         int ret;
 506         char s[30];
 507
 508         /* default use board type 7 */
 509         gd->board_type = BOARD_TYPE_7;
 510         if (env_init())
 511                 return;
 512
 513         ret = env_get_f("panel", s, sizeof(s));
 514         if (ret < 0)
 515                 return;
 516
 517         if (!strncmp("lg4573", s, 6))
 518                 gd->board_type = BOARD_TYPE_4;
 519 }
 520
 521 #ifdef CONFIG_DTB_RESELECT
 522 int embedded_dtb_select(void)
 523 {
 524         int rescan;
 525
 526         do_board_detect();
 527         fdtdec_resetup(&rescan);
 528
 529         return 0;
 530 }
 531 #endif
 532
 533 enum env_location env_get_location(enum env_operation op, int prio)
 534 {
 535         if (op == ENVOP_SAVE || op == ENVOP_ERASE)
 536                 return ENVL_SPI_FLASH;
 537
 538         switch (prio) {
 539         case 0:
 540                 return ENVL_NOWHERE;
 541
 542         case 1:
 543                 return ENVL_SPI_FLASH;
 544
 545         default:
 546                 return ENVL_UNKNOWN;
 547         }
 548
 549         return ENVL_UNKNOWN;
 550 }