1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * Author: Fabio Estevam <fabio.estevam@freescale.com>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <linux/errno.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/sys_proto.h>
27 #include <i2c_eeprom.h>
36 DECLARE_GLOBAL_DATA_PTR;
43 #define ARI_BT_4 "aristainetos2_4@2"
44 #define ARI_BT_7 "aristainetos2_7@1"
46 int board_phy_config(struct phy_device *phydev)
48 /* control data pad skew - devaddr = 0x02, register = 0x04 */
49 ksz9031_phy_extended_write(phydev, 0x02,
50 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
51 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
52 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
53 ksz9031_phy_extended_write(phydev, 0x02,
54 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
55 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
56 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
57 ksz9031_phy_extended_write(phydev, 0x02,
58 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
59 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
60 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
61 ksz9031_phy_extended_write(phydev, 0x02,
62 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
63 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
65 if (phydev->drv->config)
66 phydev->drv->config(phydev);
71 static int rotate_logo_one(unsigned char *out, unsigned char *in)
75 for (i = 0; i < BMP_LOGO_WIDTH; i++)
76 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
77 out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
78 in[i * BMP_LOGO_WIDTH + j];
83 * Rotate the BMP_LOGO (only)
84 * Will only work, if the logo is square, as
85 * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
87 void rotate_logo(int rotations)
89 unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
90 struct bmp_header *header;
91 unsigned char *in_logo;
94 if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
97 header = (struct bmp_header *)bmp_logo_bitmap;
98 in_logo = bmp_logo_bitmap + header->data_offset;
100 /* one 90 degree rotation */
101 if (rotations == 1 || rotations == 2 || rotations == 3)
102 rotate_logo_one(out_logo, in_logo);
104 /* second 90 degree rotation */
105 if (rotations == 2 || rotations == 3)
106 rotate_logo_one(in_logo, out_logo);
108 /* third 90 degree rotation */
110 rotate_logo_one(out_logo, in_logo);
112 /* copy result back to original array */
113 if (rotations == 1 || rotations == 3)
114 for (i = 0; i < BMP_LOGO_WIDTH; i++)
115 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
116 in_logo[i * BMP_LOGO_WIDTH + j] =
117 out_logo[i * BMP_LOGO_WIDTH + j];
120 static void enable_lvds(struct display_info_t const *dev)
122 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
123 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
125 s32 timeout = 100000;
128 reg = readl(&ccm->analog_pll_video);
129 reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
130 writel(reg, &ccm->analog_pll_video);
132 /* set PLL5 to 232720000Hz */
133 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
134 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
135 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
136 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
137 writel(reg, &ccm->analog_pll_video);
139 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
140 &ccm->analog_pll_video_num);
141 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
142 &ccm->analog_pll_video_denom);
144 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
145 writel(reg, &ccm->analog_pll_video);
148 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
151 printf("Warning: video pll lock timeout!\n");
153 reg = readl(&ccm->analog_pll_video);
154 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
155 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
156 writel(reg, &ccm->analog_pll_video);
158 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
159 reg = readl(&ccm->cs2cdr);
160 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
161 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
162 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
163 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
164 writel(reg, &ccm->cs2cdr);
166 reg = readl(&ccm->cscmr2);
167 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
168 writel(reg, &ccm->cscmr2);
170 reg = readl(&ccm->chsccdr);
171 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
172 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
173 writel(reg, &ccm->chsccdr);
175 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
176 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
177 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
178 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
179 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
180 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
181 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
182 writel(reg, &iomux->gpr[2]);
184 reg = readl(&iomux->gpr[3]);
185 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
186 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
187 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
188 writel(reg, &iomux->gpr[3]);
191 static void enable_spi_display(struct display_info_t const *dev)
193 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
194 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
196 s32 timeout = 100000;
198 #if defined(CONFIG_VIDEO_BMP_LOGO)
199 rotate_logo(3); /* portrait display in landscape mode */
202 reg = readl(&ccm->cs2cdr);
204 /* select pll 5 clock */
205 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
206 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
207 writel(reg, &ccm->cs2cdr);
209 /* set PLL5 to 197994996Hz */
210 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
211 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
212 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
213 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
214 writel(reg, &ccm->analog_pll_video);
216 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
217 &ccm->analog_pll_video_num);
218 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
219 &ccm->analog_pll_video_denom);
221 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
222 writel(reg, &ccm->analog_pll_video);
225 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
228 printf("Warning: video pll lock timeout!\n");
230 reg = readl(&ccm->analog_pll_video);
231 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
232 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
233 writel(reg, &ccm->analog_pll_video);
235 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
236 reg = readl(&ccm->cs2cdr);
237 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
238 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
239 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
240 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
241 writel(reg, &ccm->cs2cdr);
243 reg = readl(&ccm->cscmr2);
244 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
245 writel(reg, &ccm->cscmr2);
247 reg = readl(&ccm->chsccdr);
248 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
249 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
250 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
251 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
252 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
253 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
254 writel(reg, &ccm->chsccdr);
256 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
257 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
258 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
259 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
260 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
261 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
262 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
263 writel(reg, &iomux->gpr[2]);
265 reg = readl(&iomux->gpr[3]);
266 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
267 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
268 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
269 writel(reg, &iomux->gpr[3]);
272 static void setup_display(void)
277 static void set_gpr_register(void)
279 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
281 writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
282 IOMUXC_GPR1_EXC_MON_SLVE |
283 (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
285 &iomuxc_regs->gpr[1]);
286 writel(0x0, &iomuxc_regs->gpr[8]);
287 writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
288 IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
289 &iomuxc_regs->gpr[12]);
292 extern char __bss_start[], __bss_end[];
293 int board_early_init_f(void)
295 select_ldb_di_clock_source(MXC_PLL5_CLK);
299 * clear bss here, so we can use spi driver
300 * before relocation and read Environment
303 memset(__bss_start, 0x00, __bss_end - __bss_start);
308 static void setup_one_led(char *label, int state)
313 ret = led_get_by_label(label, &dev);
315 led_set_state(dev, state);
318 static void setup_board_gpio(void)
320 setup_one_led("led_ena", LEDST_ON);
321 /* switch off Status LEDs */
322 setup_one_led("led_yellow", LEDST_OFF);
323 setup_one_led("led_red", LEDST_OFF);
324 setup_one_led("led_green", LEDST_OFF);
325 setup_one_led("led_blue", LEDST_OFF);
328 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
331 static void aristainetos_run_rescue_command(int reason)
333 char rescue_reason_command[80];
335 sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
336 run_command(rescue_reason_command, 0);
339 static int aristainetos_eeprom(void)
347 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
349 printf("%s: No eeprom0 path offset\n", __func__);
353 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
355 printf("%s: Could not find EEPROM\n", __func__);
359 ret = i2c_set_chip_offset_len(dev, 2);
363 ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
365 printf("%s: Could not read EEPROM\n", __func__);
369 if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
370 rescue_reason = *(uint8_t *)&data[9];
371 memset(&data[3], 0xff, 7);
372 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
373 printf("\nBooting into Rescue System (EEPROM)\n");
374 aristainetos_run_rescue_command(rescue_reason);
375 run_command("run rescue_load_fit rescueboot", 0);
376 } else if (strncmp((char *)data, "DeF", 3) == 0) {
377 memset(data, 0xff, 3);
378 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
379 printf("\nClear u-boot environment (set back to defaults)\n");
380 run_command("run default_env; saveenv; saveenv", 0);
386 static void aristainetos_bootmode_settings(void)
388 struct gpio_desc *desc;
389 struct src *psrc = (struct src *)SRC_BASE_ADDR;
390 unsigned int sbmr1 = readl(&psrc->sbmr1);
396 * Check the boot-source. If booting from NOR Flash,
399 ret = gpio_hog_lookup_name("bootsel0", &desc);
401 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
402 ret = gpio_hog_lookup_name("bootsel1", &desc);
404 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
405 ret = gpio_hog_lookup_name("bootsel2", &desc);
407 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
410 my_bootdelay = env_get("nor_bootdelay");
412 env_set("bootdelay", my_bootdelay);
414 env_set("bootdelay", "-2");
418 env_set("bootmode", "1");
419 printf("SD bootmode jumper set!\n");
421 env_set("bootmode", "0");
424 /* read out some jumper values*/
425 ret = gpio_hog_lookup_name("env_reset", &desc);
427 if (dm_gpio_get_value(desc)) {
428 printf("\nClear env (set back to defaults)\n");
429 run_command("run default_env; saveenv; saveenv", 0);
432 ret = gpio_hog_lookup_name("boot_rescue", &desc);
434 if (dm_gpio_get_value(desc)) {
435 aristainetos_run_rescue_command(16);
436 run_command("run rescue_xload_boot", 0);
441 int board_late_init(void)
446 splash_get_pos(&x, &y);
447 bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
449 aristainetos_bootmode_settings();
452 aristainetos_eeprom();
455 if (gd->board_type == BOARD_TYPE_4)
456 env_set("board_type", ARI_BT_4);
458 env_set("board_type", ARI_BT_7);
465 gd->ram_size = imx_ddr_size();
470 struct display_info_t const displays[] = {
474 .pixfmt = IPU_PIX_FMT_RGB24,
476 .enable = enable_lvds,
490 .vmode = FB_VMODE_NONINTERLACED
493 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
494 (CONFIG_SYS_BOARD_VERSION == 3) || \
495 (CONFIG_SYS_BOARD_VERSION == 4))
499 .pixfmt = IPU_PIX_FMT_RGB24,
501 .enable = enable_spi_display,
514 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
515 FB_SYNC_VERT_HIGH_ACT,
516 .vmode = FB_VMODE_NONINTERLACED
521 size_t display_count = ARRAY_SIZE(displays);
523 iomux_v3_cfg_t nfc_pads[] = {
524 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
525 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
526 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
527 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
528 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
529 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
530 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
531 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
532 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
533 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
534 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
535 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
536 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
537 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
538 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
539 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
542 static void setup_gpmi_nand(void)
544 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
546 /* config gpmi nand iomux */
547 imx_iomux_v3_setup_multiple_pads(nfc_pads,
548 ARRAY_SIZE(nfc_pads));
550 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
551 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
553 /* config gpmi and bch clock to 100 MHz */
554 clrsetbits_le32(&mxc_ccm->cs2cdr,
555 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
556 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
557 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
558 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
559 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
560 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
562 /* enable ENFC_CLK_ROOT clock */
563 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
565 /* enable gpmi and bch clock gating */
566 setbits_le32(&mxc_ccm->CCGR4,
567 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
568 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
569 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
570 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
571 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
573 /* enable apbh clock gating */
574 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
579 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
581 /* address of boot parameters */
582 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
588 /* GPIO_1 for USB_OTG_ID */
589 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
593 int board_fit_config_name_match(const char *name)
595 if (gd->board_type == BOARD_TYPE_4 &&
599 if (gd->board_type == BOARD_TYPE_7 &&
606 static void do_board_detect(void)
611 /* default use board type 7 */
612 gd->board_type = BOARD_TYPE_7;
616 ret = env_get_f("panel", s, sizeof(s));
620 if (!strncmp("lg4573", s, 6))
621 gd->board_type = BOARD_TYPE_4;
624 #ifdef CONFIG_DTB_RESELECT
625 int embedded_dtb_select(void)
630 fdtdec_resetup(&rescan);