board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <linux/fb.h>
  27 #include <ipu_pixfmt.h>
  28 #include <input.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <pwm.h>
  32 #include <dm/root.h>
  33 #include <env.h>
  34 #include <micrel.h>
  35 #include <video.h>
  36 #include <../drivers/video/imx/ipu.h>
  37 #if defined(CONFIG_VIDEO_BMP_LOGO)
  38         #include <bmp_logo.h>
  39 #endif
  40 #include <led.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46
  47 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  49         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  50
  51 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  52
  53 #define DISP_PAD_CTRL   (0x10)
  54
  55 enum {
  56         BOARD_TYPE_4 = 4,
  57         BOARD_TYPE_7 = 7,
  58 };
  59
  60 #define ARI_BT_4 "aristainetos2_4@2"
  61 #define ARI_BT_7 "aristainetos2_7@1"
  62
  63 struct i2c_pads_info i2c_pad_info3 = {
  64         .scl = {
  65                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  66                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  67                 .gp = IMX_GPIO_NR(1, 5)
  68         },
  69         .sda = {
  70                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  71                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  72                 .gp = IMX_GPIO_NR(1, 6)
  73         }
  74 };
  75
  76 struct i2c_pads_info i2c_pad_info4 = {
  77         .scl = {
  78                 .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
  79                 .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
  80                 .gp = IMX_GPIO_NR(1, 7)
  81         },
  82         .sda = {
  83                 .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
  84                 .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
  85                 .gp = IMX_GPIO_NR(1, 8)
  86         }
  87 };
  88
  89 iomux_v3_cfg_t const enet_pads[] = {
  90         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 102         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 103         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 104         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 105 };
 106
 107 static iomux_v3_cfg_t const backlight_pads[] = {
 108         /* backlight PWM brightness control */
 109         MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 110         /* backlight enable */
 111         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 112         /* LCD power enable */
 113         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 114 };
 115
 116 static void setup_iomux_enet(void)
 117 {
 118         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 119 }
 120
 121 static iomux_v3_cfg_t const display_pads[] = {
 122         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
 123         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 124         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 125         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 126         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 127         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 128         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 129         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 130         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 131         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 132         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 133         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 134         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 135         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 136         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 137         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 138         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 139         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 140         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 141         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 142         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 143         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 144         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 145         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 146         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 147         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 148         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 149         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 150 };
 151
 152 int board_phy_config(struct phy_device *phydev)
 153 {
 154         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 155         ksz9031_phy_extended_write(phydev, 0x02,
 156                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 157                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 158         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 159         ksz9031_phy_extended_write(phydev, 0x02,
 160                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 161                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 162         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
 163         ksz9031_phy_extended_write(phydev, 0x02,
 164                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 165                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 166         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 167         ksz9031_phy_extended_write(phydev, 0x02,
 168                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 169                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 170
 171         if (phydev->drv->config)
 172                 phydev->drv->config(phydev);
 173
 174         return 0;
 175 }
 176
 177 int board_eth_init(bd_t *bis)
 178 {
 179         setup_iomux_enet();
 180         return cpu_eth_init(bis);
 181 }
 182
 183 static int rotate_logo_one(unsigned char *out, unsigned char *in)
 184 {
 185         int   i, j;
 186
 187         for (i = 0; i < BMP_LOGO_WIDTH; i++)
 188                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 189                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
 190                         in[i * BMP_LOGO_WIDTH + j];
 191         return 0;
 192 }
 193
 194 /*
 195  * Rotate the BMP_LOGO (only)
 196  * Will only work, if the logo is square, as
 197  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
 198  */
 199 void rotate_logo(int rotations)
 200 {
 201         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
 202         unsigned char *in_logo;
 203         int   i, j;
 204
 205         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 206                 return;
 207
 208         in_logo = bmp_logo_bitmap;
 209
 210         /* one 90 degree rotation */
 211         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 212                 rotate_logo_one(out_logo, in_logo);
 213
 214         /* second 90 degree rotation */
 215         if (rotations == 2  ||  rotations == 3)
 216                 rotate_logo_one(in_logo, out_logo);
 217
 218         /* third 90 degree rotation */
 219         if (rotations == 3)
 220                 rotate_logo_one(out_logo, in_logo);
 221
 222         /* copy result back to original array */
 223         if (rotations == 1  ||  rotations == 3)
 224                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 225                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 226                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 227                                 out_logo[i * BMP_LOGO_WIDTH + j];
 228 }
 229
 230 static void enable_display_power(void)
 231 {
 232         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 233                                          ARRAY_SIZE(backlight_pads));
 234
 235         /* backlight enable */
 236         gpio_request(IMX_GPIO_NR(6, 31), "backlight");
 237         gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
 238         gpio_free(IMX_GPIO_NR(6, 31));
 239         /* LCD power enable */
 240         gpio_request(IMX_GPIO_NR(6, 15), "LCD_power_enable");
 241         gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
 242         gpio_free(IMX_GPIO_NR(6, 15));
 243
 244         /* enable backlight PWM 1 */
 245         if (pwm_init(0, 0, 0))
 246                 goto error;
 247         /* duty cycle 500ns, period: 3000ns */
 248         if (pwm_config(0, 50000, 300000))
 249                 goto error;
 250         if (pwm_enable(0))
 251                 goto error;
 252         return;
 253
 254 error:
 255         puts("error init pwm for backlight\n");
 256 }
 257
 258 static void enable_lvds(struct display_info_t const *dev)
 259 {
 260         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 261         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 262         int reg;
 263         s32 timeout = 100000;
 264
 265         /* set PLL5 clock */
 266         reg = readl(&ccm->analog_pll_video);
 267         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 268         writel(reg, &ccm->analog_pll_video);
 269
 270         /* set PLL5 to 232720000Hz */
 271         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 272         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 273         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 274         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 275         writel(reg, &ccm->analog_pll_video);
 276
 277         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 278                &ccm->analog_pll_video_num);
 279         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 280                &ccm->analog_pll_video_denom);
 281
 282         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 283         writel(reg, &ccm->analog_pll_video);
 284
 285         while (timeout--)
 286                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 287                         break;
 288         if (timeout < 0)
 289                 printf("Warning: video pll lock timeout!\n");
 290
 291         reg = readl(&ccm->analog_pll_video);
 292         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 293         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 294         writel(reg, &ccm->analog_pll_video);
 295
 296         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 297         reg = readl(&ccm->cs2cdr);
 298         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 299                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 300         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 301                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 302         writel(reg, &ccm->cs2cdr);
 303
 304         reg = readl(&ccm->cscmr2);
 305         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 306         writel(reg, &ccm->cscmr2);
 307
 308         reg = readl(&ccm->chsccdr);
 309         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 310                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 311         writel(reg, &ccm->chsccdr);
 312
 313         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 314               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 315               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 316               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 317               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 318               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 319               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 320         writel(reg, &iomux->gpr[2]);
 321
 322         reg = readl(&iomux->gpr[3]);
 323         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 324                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 325                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 326         writel(reg, &iomux->gpr[3]);
 327 }
 328
 329 static void enable_spi_display(struct display_info_t const *dev)
 330 {
 331         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 332         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 333         int reg;
 334         s32 timeout = 100000;
 335
 336 #if defined(CONFIG_VIDEO_BMP_LOGO)
 337         rotate_logo(3);  /* portrait display in landscape mode */
 338 #endif
 339
 340         /*
 341          * set ldb clock to 28341000 Hz calculated through the formula:
 342          * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
 343          * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
 344          * see:
 345          * https://community.freescale.com/thread/308170
 346          */
 347         ipu_set_ldb_clock(28341000);
 348
 349         reg = readl(&ccm->cs2cdr);
 350
 351         /* select pll 5 clock */
 352         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 353                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 354         writel(reg, &ccm->cs2cdr);
 355
 356         /* set PLL5 to 197994996Hz */
 357         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 358         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 359         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 360         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 361         writel(reg, &ccm->analog_pll_video);
 362
 363         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 364                &ccm->analog_pll_video_num);
 365         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 366                &ccm->analog_pll_video_denom);
 367
 368         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 369         writel(reg, &ccm->analog_pll_video);
 370
 371         while (timeout--)
 372                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 373                         break;
 374         if (timeout < 0)
 375                 printf("Warning: video pll lock timeout!\n");
 376
 377         reg = readl(&ccm->analog_pll_video);
 378         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 379         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 380         writel(reg, &ccm->analog_pll_video);
 381
 382         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 383         reg = readl(&ccm->cs2cdr);
 384         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 385                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 386         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 387                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 388         writel(reg, &ccm->cs2cdr);
 389
 390         reg = readl(&ccm->cscmr2);
 391         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 392         writel(reg, &ccm->cscmr2);
 393
 394         reg = readl(&ccm->chsccdr);
 395         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 396                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 397         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 398         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 399         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 400         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 401         writel(reg, &ccm->chsccdr);
 402
 403         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 404               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 405               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 406               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 407               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 408               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 409               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 410         writel(reg, &iomux->gpr[2]);
 411
 412         reg = readl(&iomux->gpr[3]);
 413         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 414                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 415                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 416         writel(reg, &iomux->gpr[3]);
 417
 418         imx_iomux_v3_setup_multiple_pads(display_pads,
 419                                          ARRAY_SIZE(display_pads));
 420 }
 421
 422 static void setup_display(void)
 423 {
 424         enable_ipu_clock();
 425         enable_display_power();
 426 }
 427
 428 static void set_gpr_register(void)
 429 {
 430         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 431
 432         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 433                IOMUXC_GPR1_EXC_MON_SLVE |
 434                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 435                IOMUXC_GPR1_ACT_CS0,
 436                &iomuxc_regs->gpr[1]);
 437         writel(0x0, &iomuxc_regs->gpr[8]);
 438         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 439                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 440                &iomuxc_regs->gpr[12]);
 441 }
 442
 443 extern char __bss_start[], __bss_end[];
 444 int board_early_init_f(void)
 445 {
 446         setup_display();
 447         set_gpr_register();
 448
 449         /*
 450          * clear bss here, so we can use spi driver
 451          * before relocation and read Environment
 452          * from spi flash.
 453          */
 454         memset(__bss_start, 0x00, __bss_end - __bss_start);
 455
 456         return 0;
 457 }
 458
 459 static void setup_i2c4(void)
 460 {
 461         setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 462                   &i2c_pad_info4);
 463 }
 464
 465 static void setup_one_led(char *label, int state)
 466 {
 467         struct udevice *dev;
 468         int ret;
 469
 470         ret = led_get_by_label(label, &dev);
 471         if (ret == 0)
 472                 led_set_state(dev, state);
 473 }
 474
 475 static void setup_board_gpio(void)
 476 {
 477         setup_one_led("led_ena", LEDST_ON);
 478         /* switch off Status LEDs */
 479         setup_one_led("led_yellow", LEDST_OFF);
 480         setup_one_led("led_red", LEDST_OFF);
 481         setup_one_led("led_green", LEDST_OFF);
 482         setup_one_led("led_blue", LEDST_OFF);
 483 }
 484
 485 int board_late_init(void)
 486 {
 487         char *my_bootdelay;
 488         char bootmode = 0;
 489         char const *panel = env_get("panel");
 490         struct gpio_desc *desc;
 491         int ret;
 492
 493         led_default_state();
 494         /*
 495          * Check the boot-source. If booting from NOR Flash,
 496          * disable bootdelay
 497          */
 498         desc = gpio_hog_lookup_name("bootsel0");
 499         if (desc)
 500                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 501         desc = gpio_hog_lookup_name("bootsel1");
 502         if (desc)
 503                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 504         desc = gpio_hog_lookup_name("bootsel2");
 505         if (desc)
 506                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 507
 508         if (bootmode == 7) {
 509                 my_bootdelay = env_get("nor_bootdelay");
 510                 if (my_bootdelay != NULL)
 511                         env_set("bootdelay", my_bootdelay);
 512                 else
 513                         env_set("bootdelay", "-2");
 514         }
 515
 516         /* read out some jumper values*/
 517         ret = gpio_hog_lookup_name("env_reset", &desc);
 518         if (!ret) {
 519                 if (dm_gpio_get_value(desc)) {
 520                         printf("\nClear env (set back to defaults)\n");
 521                         run_command("run default_env; saveenv; saveenv", 0);
 522                 }
 523         }
 524         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 525         if (!ret) {
 526                 if (dm_gpio_get_value(desc)) {
 527                         aristainetos_run_rescue_command(16);
 528                         run_command("run rescue_xload_boot", 0);
 529                 }
 530         }
 531
 532         /* if we have the lg panel, we can initialze it now */
 533         if (panel)
 534                 if (!strcmp(panel, displays[1].mode.name))
 535                         lg4573_spi_startup(CONFIG_LG4573_BUS,
 536                                            CONFIG_LG4573_CS,
 537                                            10000000, SPI_MODE_0);
 538
 539         /* set board_type */
 540         if (gd->board_type == BOARD_TYPE_4)
 541                 env_set("board_type", ARI_BT_4);
 542         else
 543                 env_set("board_type", ARI_BT_7);
 544
 545         return 0;
 546 }
 547
 548 struct i2c_pads_info i2c_pad_info1 = {
 549         .scl = {
 550                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
 551                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 552                 .gp = IMX_GPIO_NR(5, 27)
 553         },
 554         .sda = {
 555                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
 556                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 557                 .gp = IMX_GPIO_NR(5, 26)
 558         }
 559 };
 560
 561 struct i2c_pads_info i2c_pad_info2 = {
 562         .scl = {
 563                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 564                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 565                 .gp = IMX_GPIO_NR(4, 12)
 566         },
 567         .sda = {
 568                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 569                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 570                 .gp = IMX_GPIO_NR(4, 13)
 571         }
 572 };
 573
 574 int dram_init(void)
 575 {
 576         gd->ram_size = imx_ddr_size();
 577
 578         return 0;
 579 }
 580
 581 struct display_info_t const displays[] = {
 582         {
 583                 .bus    = -1,
 584                 .addr   = 0,
 585                 .pixfmt = IPU_PIX_FMT_RGB24,
 586                 .detect = NULL,
 587                 .enable = enable_lvds,
 588                 .mode   = {
 589                         .name           = "lb07wv8",
 590                         .refresh        = 60,
 591                         .xres           = 800,
 592                         .yres           = 480,
 593                         .pixclock       = 30066,
 594                         .left_margin    = 88,
 595                         .right_margin   = 88,
 596                         .upper_margin   = 20,
 597                         .lower_margin   = 20,
 598                         .hsync_len      = 80,
 599                         .vsync_len      = 5,
 600                         .sync           = FB_SYNC_EXT,
 601                         .vmode          = FB_VMODE_NONINTERLACED
 602                 }
 603         }
 604 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
 605         , {
 606                 .bus    = -1,
 607                 .addr   = 0,
 608                 .pixfmt = IPU_PIX_FMT_RGB24,
 609                 .detect = NULL,
 610                 .enable = enable_spi_display,
 611                 .mode   = {
 612                         .name           = "lg4573",
 613                         .refresh        = 57,
 614                         .xres           = 480,
 615                         .yres           = 800,
 616                         .pixclock       = 37037,
 617                         .left_margin    = 59,
 618                         .right_margin   = 10,
 619                         .upper_margin   = 15,
 620                         .lower_margin   = 15,
 621                         .hsync_len      = 10,
 622                         .vsync_len      = 15,
 623                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 624                                           FB_SYNC_VERT_HIGH_ACT,
 625                         .vmode          = FB_VMODE_NONINTERLACED
 626                 }
 627         }
 628 #endif
 629 };
 630 size_t display_count = ARRAY_SIZE(displays);
 631
 632 /* no console on this board */
 633 int board_cfb_skip(void)
 634 {
 635         return 1;
 636 }
 637
 638 iomux_v3_cfg_t nfc_pads[] = {
 639         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 640         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 641         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 642         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 643         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 644         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 645         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 646         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 647         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 648         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 649         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 650         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 651         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 652         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 653         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 654         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 655 };
 656
 657 static void setup_gpmi_nand(void)
 658 {
 659         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 660
 661         /* config gpmi nand iomux */
 662         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 663                                          ARRAY_SIZE(nfc_pads));
 664
 665         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 666         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 667
 668         /* config gpmi and bch clock to 100 MHz */
 669         clrsetbits_le32(&mxc_ccm->cs2cdr,
 670                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 671                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 672                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 673                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 674                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 675                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 676
 677         /* enable ENFC_CLK_ROOT clock */
 678         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 679
 680         /* enable gpmi and bch clock gating */
 681         setbits_le32(&mxc_ccm->CCGR4,
 682                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 683                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 684                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 685                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 686                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 687
 688         /* enable apbh clock gating */
 689         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 690 }
 691
 692 int board_init(void)
 693 {
 694         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 695
 696         /* address of boot parameters */
 697         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 698
 699         setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 700                   &i2c_pad_info1);
 701         setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 702                   &i2c_pad_info2);
 703         setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 704                   &i2c_pad_info3);
 705         setup_i2c4();
 706
 707         setup_board_gpio();
 708         setup_gpmi_nand();
 709
 710         /* GPIO_1 for USB_OTG_ID */
 711         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 712         return 0;
 713 }
 714
 715 int checkboard(void)
 716 {
 717         printf("Board: %s\n", CONFIG_BOARDNAME);
 718         return 0;
 719 }
 720
 721 int board_fit_config_name_match(const char *name)
 722 {
 723         if (gd->board_type == BOARD_TYPE_4 &&
 724             strchr(name, 0x34))
 725                 return 0;
 726
 727         if (gd->board_type == BOARD_TYPE_7 &&
 728             strchr(name, 0x37))
 729                 return 0;
 730
 731         return -1;
 732 }
 733
 734 static void do_board_detect(void)
 735 {
 736         int ret;
 737         char s[30];
 738
 739         /* default use board type 7 */
 740         gd->board_type = BOARD_TYPE_7;
 741         if (env_init())
 742                 return;
 743
 744         ret = env_get_f("panel", s, sizeof(s));
 745         if (ret < 0)
 746                 return;
 747
 748         if (!strncmp("lg4573", s, 6))
 749                 gd->board_type = BOARD_TYPE_4;
 750 }
 751
 752 #ifdef CONFIG_DTB_RESELECT
 753 int embedded_dtb_select(void)
 754 {
 755         int rescan;
 756
 757         do_board_detect();
 758         fdtdec_resetup(&rescan);
 759
 760         return 0;
 761 }
 762 #endif