board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <command.h>
  13 #include <image.h>
  14 #include <init.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <linux/errno.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23 #include <asm/mach-imx/video.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <bmp_logo.h>
  28 #include <dm/root.h>
  29 #include <env.h>
  30 #include <env_internal.h>
  31 #include <i2c_eeprom.h>
  32 #include <i2c.h>
  33 #include <micrel.h>
  34 #include <miiphy.h>
  35 #include <lcd.h>
  36 #include <led.h>
  37 #include <power/pmic.h>
  38 #include <power/regulator.h>
  39 #include <power/da9063_pmic.h>
  40 #include <splash.h>
  41 #include <video_fb.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 enum {
  46         BOARD_TYPE_4 = 4,
  47         BOARD_TYPE_7 = 7,
  48 };
  49
  50 #define ARI_BT_4 "aristainetos2_4@2"
  51 #define ARI_BT_7 "aristainetos2_7@1"
  52
  53 int board_phy_config(struct phy_device *phydev)
  54 {
  55         /* control data pad skew - devaddr = 0x02, register = 0x04 */
  56         ksz9031_phy_extended_write(phydev, 0x02,
  57                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  58                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  59         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  60         ksz9031_phy_extended_write(phydev, 0x02,
  61                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  62                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  63         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  64         ksz9031_phy_extended_write(phydev, 0x02,
  65                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  66                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  67         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  68         ksz9031_phy_extended_write(phydev, 0x02,
  69                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  70                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  71
  72         if (phydev->drv->config)
  73                 phydev->drv->config(phydev);
  74
  75         return 0;
  76 }
  77
  78 static int rotate_logo_one(unsigned char *out, unsigned char *in)
  79 {
  80         int   i, j;
  81
  82         for (i = 0; i < BMP_LOGO_WIDTH; i++)
  83                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  84                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  85                         in[i * BMP_LOGO_WIDTH + j];
  86         return 0;
  87 }
  88
  89 /*
  90  * Rotate the BMP_LOGO (only)
  91  * Will only work, if the logo is square, as
  92  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  93  */
  94 void rotate_logo(int rotations)
  95 {
  96         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  97         struct bmp_header *header;
  98         unsigned char *in_logo;
  99         int   i, j;
 100
 101         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 102                 return;
 103
 104         header = (struct bmp_header *)bmp_logo_bitmap;
 105         in_logo = bmp_logo_bitmap + header->data_offset;
 106
 107         /* one 90 degree rotation */
 108         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 109                 rotate_logo_one(out_logo, in_logo);
 110
 111         /* second 90 degree rotation */
 112         if (rotations == 2  ||  rotations == 3)
 113                 rotate_logo_one(in_logo, out_logo);
 114
 115         /* third 90 degree rotation */
 116         if (rotations == 3)
 117                 rotate_logo_one(out_logo, in_logo);
 118
 119         /* copy result back to original array */
 120         if (rotations == 1  ||  rotations == 3)
 121                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 122                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 123                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 124                                 out_logo[i * BMP_LOGO_WIDTH + j];
 125 }
 126
 127 static void enable_lvds(struct display_info_t const *dev)
 128 {
 129         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 130         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 131         int reg;
 132         s32 timeout = 100000;
 133
 134         /* set PLL5 clock */
 135         reg = readl(&ccm->analog_pll_video);
 136         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 137         writel(reg, &ccm->analog_pll_video);
 138
 139         /* set PLL5 to 232720000Hz */
 140         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 141         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 142         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 143         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 144         writel(reg, &ccm->analog_pll_video);
 145
 146         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 147                &ccm->analog_pll_video_num);
 148         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 149                &ccm->analog_pll_video_denom);
 150
 151         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 152         writel(reg, &ccm->analog_pll_video);
 153
 154         while (timeout--)
 155                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 156                         break;
 157         if (timeout < 0)
 158                 printf("Warning: video pll lock timeout!\n");
 159
 160         reg = readl(&ccm->analog_pll_video);
 161         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 162         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 163         writel(reg, &ccm->analog_pll_video);
 164
 165         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 166         reg = readl(&ccm->cs2cdr);
 167         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 168                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 169         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 170                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 171         writel(reg, &ccm->cs2cdr);
 172
 173         reg = readl(&ccm->cscmr2);
 174         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 175         writel(reg, &ccm->cscmr2);
 176
 177         reg = readl(&ccm->chsccdr);
 178         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 179                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 180         writel(reg, &ccm->chsccdr);
 181
 182         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 183               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 184               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 185               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 186               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 187               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 188               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 189         writel(reg, &iomux->gpr[2]);
 190
 191         reg = readl(&iomux->gpr[3]);
 192         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 193                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 194                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 195         writel(reg, &iomux->gpr[3]);
 196 }
 197
 198 static void setup_display(void)
 199 {
 200         enable_ipu_clock();
 201 }
 202
 203 static void set_gpr_register(void)
 204 {
 205         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 206
 207         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 208                IOMUXC_GPR1_EXC_MON_SLVE |
 209                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 210                IOMUXC_GPR1_ACT_CS0,
 211                &iomuxc_regs->gpr[1]);
 212         writel(0x0, &iomuxc_regs->gpr[8]);
 213         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 214                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 215                &iomuxc_regs->gpr[12]);
 216 }
 217
 218 extern char __bss_start[], __bss_end[];
 219 int board_early_init_f(void)
 220 {
 221         select_ldb_di_clock_source(MXC_PLL5_CLK);
 222         set_gpr_register();
 223
 224         /*
 225          * clear bss here, so we can use spi driver
 226          * before relocation and read Environment
 227          * from spi flash.
 228          */
 229         memset(__bss_start, 0x00, __bss_end - __bss_start);
 230
 231         return 0;
 232 }
 233
 234 static void setup_one_led(char *label, int state)
 235 {
 236         struct udevice *dev;
 237         int ret;
 238
 239         ret = led_get_by_label(label, &dev);
 240         if (ret == 0)
 241                 led_set_state(dev, state);
 242 }
 243
 244 static void setup_board_gpio(void)
 245 {
 246         setup_one_led("led_ena", LEDST_ON);
 247         /* switch off Status LEDs */
 248         setup_one_led("led_yellow", LEDST_OFF);
 249         setup_one_led("led_red", LEDST_OFF);
 250         setup_one_led("led_green", LEDST_OFF);
 251         setup_one_led("led_blue", LEDST_OFF);
 252 }
 253
 254 static void aristainetos_run_rescue_command(int reason)
 255 {
 256         char rescue_reason_command[20];
 257
 258         sprintf(rescue_reason_command, "setenv rreason %d", reason);
 259         run_command(rescue_reason_command, 0);
 260 }
 261
 262 static int aristainetos_bootmode_settings(void)
 263 {
 264         struct gpio_desc *desc;
 265         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 266         unsigned int sbmr1 = readl(&psrc->sbmr1);
 267         char *my_bootdelay;
 268         char bootmode = 0;
 269         int ret;
 270         struct udevice *dev;
 271         int off;
 272         u8 data[0x10];
 273         u8 rescue_reason;
 274
 275         /* jumper controlled reset of the environment */
 276         ret = gpio_hog_lookup_name("env_reset", &desc);
 277         if (!ret) {
 278                 if (dm_gpio_get_value(desc)) {
 279                         printf("\nReset u-boot environment (jumper)\n");
 280                         run_command("run default_env; saveenv; saveenv", 0);
 281                 }
 282         }
 283
 284         off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 285         if (off < 0) {
 286                 printf("%s: No eeprom0 path offset\n", __func__);
 287                 return off;
 288         }
 289
 290         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 291         if (ret) {
 292                 printf("%s: Could not find EEPROM\n", __func__);
 293                 return ret;
 294         }
 295
 296         ret = i2c_set_chip_offset_len(dev, 2);
 297         if (ret)
 298                 return ret;
 299
 300         ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
 301         if (ret) {
 302                 printf("%s: Could not read EEPROM\n", __func__);
 303                 return ret;
 304         }
 305
 306         /* software controlled reset of the environment (EEPROM magic) */
 307         if (strncmp((char *)data, "DeF", 3) == 0) {
 308                 memset(data, 0xff, 3);
 309                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
 310                 printf("\nReset u-boot environment (EEPROM)\n");
 311                 run_command("run default_env; saveenv; saveenv", 0);
 312         }
 313
 314         if (sbmr1 & 0x40) {
 315                 env_set("bootmode", "1");
 316                 printf("SD bootmode jumper set!\n");
 317         } else {
 318                 env_set("bootmode", "0");
 319         }
 320
 321         /*
 322          * Check the boot-source. If booting from NOR Flash,
 323          * disable bootdelay
 324          */
 325         ret = gpio_hog_lookup_name("bootsel0", &desc);
 326         if (!ret)
 327                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 328         ret = gpio_hog_lookup_name("bootsel1", &desc);
 329         if (!ret)
 330                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 331         ret = gpio_hog_lookup_name("bootsel2", &desc);
 332         if (!ret)
 333                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 334
 335         if (bootmode == 7) {
 336                 my_bootdelay = env_get("nor_bootdelay");
 337                 if (my_bootdelay)
 338                         env_set("bootdelay", my_bootdelay);
 339                 else
 340                         env_set("bootdelay", "-2");
 341         }
 342
 343         /* jumper controlled boot of the rescue system */
 344         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 345         if (!ret) {
 346                 if (dm_gpio_get_value(desc)) {
 347                         printf("\nBooting into Rescue System (jumper)\n");
 348                         aristainetos_run_rescue_command(16);
 349                         run_command("run rescue_xload_boot", 0);
 350                 }
 351         }
 352
 353         /* software controlled boot of the rescue system (EEPROM magic) */
 354         if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
 355                 rescue_reason = *(uint8_t *)&data[9];
 356                 memset(&data[3], 0xff, 7);
 357                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
 358                 printf("\nBooting into Rescue System (EEPROM)\n");
 359                 aristainetos_run_rescue_command(rescue_reason);
 360                 run_command("run rescue_xload_boot", 0);
 361         }
 362
 363         return 0;
 364 }
 365
 366 #if defined(CONFIG_DM_PMIC_DA9063)
 367 /*
 368  * On the aristainetos2c boards the PMIC needs to be initialized,
 369  * because the Ethernet PHY uses a different regulator that is not
 370  * setup per hardware default. This does not influence the other versions
 371  * as this regulator isn't used there at all.
 372  *
 373  * Unfortunately we have not yet a interface to setup all
 374  * values we need.
 375  */
 376 static int setup_pmic_voltages(void)
 377 {
 378         struct udevice *dev;
 379         int off;
 380         int ret;
 381
 382         off = fdt_path_offset(gd->fdt_blob, "pmic0");
 383         if (off < 0) {
 384                 printf("%s: No pmic path offset\n", __func__);
 385                 return off;
 386         }
 387
 388         ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
 389         if (ret) {
 390                 printf("%s: Could not find PMIC\n", __func__);
 391                 return ret;
 392         }
 393
 394         pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
 395         pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
 396         ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
 397         if (ret < 0) {
 398                 printf("%s: error %d get register\n", __func__, ret);
 399                 return ret;
 400         }
 401         ret &= 0xf0;
 402         ret |= 0x09;
 403         pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
 404         pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
 405         pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
 406
 407         return 0;
 408 }
 409 #else
 410 static int setup_pmic_voltages(void)
 411 {
 412         return 0;
 413 }
 414 #endif
 415
 416 int board_late_init(void)
 417 {
 418         int x, y;
 419         int ret;
 420
 421         led_default_state();
 422         splash_get_pos(&x, &y);
 423         bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 424
 425         ret = aristainetos_bootmode_settings();
 426         if (ret)
 427                 return ret;
 428
 429         /* set board_type */
 430         if (gd->board_type == BOARD_TYPE_4)
 431                 env_set("board_type", ARI_BT_4);
 432         else
 433                 env_set("board_type", ARI_BT_7);
 434
 435         if (setup_pmic_voltages())
 436                 printf("Error setup PMIC\n");
 437
 438         return 0;
 439 }
 440
 441 int dram_init(void)
 442 {
 443         gd->ram_size = imx_ddr_size();
 444
 445         return 0;
 446 }
 447
 448 struct display_info_t const displays[] = {
 449         {
 450                 .bus    = -1,
 451                 .addr   = 0,
 452                 .pixfmt = IPU_PIX_FMT_RGB24,
 453                 .detect = NULL,
 454                 .enable = enable_lvds,
 455                 .mode   = {
 456                         .name           = "lb07wv8",
 457                         .refresh        = 60,
 458                         .xres           = 800,
 459                         .yres           = 480,
 460                         .pixclock       = 30066,
 461                         .left_margin    = 88,
 462                         .right_margin   = 88,
 463                         .upper_margin   = 20,
 464                         .lower_margin   = 20,
 465                         .hsync_len      = 80,
 466                         .vsync_len      = 5,
 467                         .sync           = FB_SYNC_EXT,
 468                         .vmode          = FB_VMODE_NONINTERLACED
 469                 }
 470         }
 471 };
 472 size_t display_count = ARRAY_SIZE(displays);
 473
 474 int board_init(void)
 475 {
 476         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 477
 478         /* address of boot parameters */
 479         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 480
 481         setup_board_gpio();
 482         setup_display();
 483
 484         /* GPIO_1 for USB_OTG_ID */
 485         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 486         return 0;
 487 }
 488
 489 int board_fit_config_name_match(const char *name)
 490 {
 491         if (gd->board_type == BOARD_TYPE_4 &&
 492             strchr(name, 0x34))
 493                 return 0;
 494
 495         if (gd->board_type == BOARD_TYPE_7 &&
 496             strchr(name, 0x37))
 497                 return 0;
 498
 499         return -1;
 500 }
 501
 502 static void do_board_detect(void)
 503 {
 504         int ret;
 505         char s[30];
 506
 507         /* default use board type 7 */
 508         gd->board_type = BOARD_TYPE_7;
 509         if (env_init())
 510                 return;
 511
 512         ret = env_get_f("panel", s, sizeof(s));
 513         if (ret < 0)
 514                 return;
 515
 516         if (!strncmp("lg4573", s, 6))
 517                 gd->board_type = BOARD_TYPE_4;
 518 }
 519
 520 #ifdef CONFIG_DTB_RESELECT
 521 int embedded_dtb_select(void)
 522 {
 523         int rescan;
 524
 525         do_board_detect();
 526         fdtdec_resetup(&rescan);
 527
 528         return 0;
 529 }
 530 #endif
 531
 532 enum env_location env_get_location(enum env_operation op, int prio)
 533 {
 534         if (op == ENVOP_SAVE || op == ENVOP_ERASE)
 535                 return ENVL_SPI_FLASH;
 536
 537         switch (prio) {
 538         case 0:
 539                 return ENVL_NOWHERE;
 540
 541         case 1:
 542                 return ENVL_SPI_FLASH;
 543
 544         default:
 545                 return ENVL_UNKNOWN;
 546         }
 547
 548         return ENVL_UNKNOWN;
 549 }