Merge branch 'master' of http://www.denx.de/git/u-boot
[platform/kernel/u-boot.git] / board / amcc / yucca / yucca.c
1 /*
2  * (C) Copyright 2006
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  *
23  * Port to AMCC-440SPE Evaluation Board SOP - April 2005
24  *
25  * PCIe supporting routines derived from Linux 440SPe PCIe driver.
26  */
27
28 #include <common.h>
29 #include <ppc4xx.h>
30 #include <asm/processor.h>
31 #include <i2c.h>
32 #include <asm-ppc/io.h>
33
34 #include "yucca.h"
35 #include "../cpu/ppc4xx/440spe_pcie.h"
36
37 #undef PCIE_ENDPOINT
38 /* #define PCIE_ENDPOINT 1 */
39
40 void fpga_init (void);
41
42 void get_sys_info(PPC440_SYS_INFO *board_cfg );
43 int compare_to_true(char *str );
44 char *remove_l_w_space(char *in_str );
45 char *remove_t_w_space(char *in_str );
46 int get_console_port(void);
47 unsigned long ppcMfcpr(unsigned long cpr_reg);
48 unsigned long ppcMfsdr(unsigned long sdr_reg);
49
50 int ppc440spe_init_pcie_rootport(int port);
51 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
52
53 #define DEBUG_ENV
54 #ifdef DEBUG_ENV
55 #define DEBUGF(fmt,args...) printf(fmt ,##args)
56 #else
57 #define DEBUGF(fmt,args...)
58 #endif
59
60 #define FALSE   0
61 #define TRUE    1
62
63 int board_early_init_f (void)
64 {
65 /*----------------------------------------------------------------------------+
66 | Define Boot devices
67 +----------------------------------------------------------------------------*/
68 #define BOOT_FROM_SMALL_FLASH           0x00
69 #define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
70 #define BOOT_FROM_PCI                   0x02
71 #define BOOT_DEVICE_UNKNOWN             0x03
72
73 /*----------------------------------------------------------------------------+
74 | EBC Devices Characteristics
75 |   Peripheral Bank Access Parameters       -   EBC_BxAP
76 |   Peripheral Bank Configuration Register  -   EBC_BxCR
77 +----------------------------------------------------------------------------*/
78
79 /*
80  * Small Flash and FRAM
81  * BU Value
82  * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
83  * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
84  * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
85  */
86 #define EBC_BXAP_SMALL_FLASH            EBC_BXAP_BME_DISABLED   | \
87                                         EBC_BXAP_TWT_ENCODE(7)  | \
88                                         EBC_BXAP_BCE_DISABLE    | \
89                                         EBC_BXAP_BCT_2TRANS     | \
90                                         EBC_BXAP_CSN_ENCODE(0)  | \
91                                         EBC_BXAP_OEN_ENCODE(0)  | \
92                                         EBC_BXAP_WBN_ENCODE(0)  | \
93                                         EBC_BXAP_WBF_ENCODE(0)  | \
94                                         EBC_BXAP_TH_ENCODE(0)   | \
95                                         EBC_BXAP_RE_DISABLED    | \
96                                         EBC_BXAP_SOR_DELAYED    | \
97                                         EBC_BXAP_BEM_WRITEONLY  | \
98                                         EBC_BXAP_PEN_DISABLED
99
100 #define EBC_BXCR_SMALL_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
101                                         EBC_BXCR_BS_16MB                | \
102                                         EBC_BXCR_BU_RW                  | \
103                                         EBC_BXCR_BW_8BIT
104
105 #define EBC_BXCR_SMALL_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xe7000000) | \
106                                         EBC_BXCR_BS_16MB                | \
107                                         EBC_BXCR_BU_RW                  | \
108                                         EBC_BXCR_BW_8BIT
109
110 /*
111  * Large Flash and SRAM
112  * BU Value
113  * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
114  * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
115  * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
116 */
117 #define EBC_BXAP_LARGE_FLASH            EBC_BXAP_BME_DISABLED   | \
118                                         EBC_BXAP_TWT_ENCODE(7)  | \
119                                         EBC_BXAP_BCE_DISABLE    | \
120                                         EBC_BXAP_BCT_2TRANS     | \
121                                         EBC_BXAP_CSN_ENCODE(0)  | \
122                                         EBC_BXAP_OEN_ENCODE(0)  | \
123                                         EBC_BXAP_WBN_ENCODE(0)  | \
124                                         EBC_BXAP_WBF_ENCODE(0)  | \
125                                         EBC_BXAP_TH_ENCODE(0)   | \
126                                         EBC_BXAP_RE_DISABLED    | \
127                                         EBC_BXAP_SOR_DELAYED    | \
128                                         EBC_BXAP_BEM_WRITEONLY  | \
129                                         EBC_BXAP_PEN_DISABLED
130
131 #define EBC_BXCR_LARGE_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
132                                         EBC_BXCR_BS_16MB                | \
133                                         EBC_BXCR_BU_RW                  | \
134                                         EBC_BXCR_BW_16BIT
135
136 #define EBC_BXCR_LARGE_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xE7000000) | \
137                                         EBC_BXCR_BS_16MB                | \
138                                         EBC_BXCR_BU_RW                  | \
139                                         EBC_BXCR_BW_16BIT
140
141 /*
142  * FPGA
143  * BU value :
144  * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
145  * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
146  */
147 #define EBC_BXAP_FPGA                   EBC_BXAP_BME_DISABLED   | \
148                                         EBC_BXAP_TWT_ENCODE(11) | \
149                                         EBC_BXAP_BCE_DISABLE    | \
150                                         EBC_BXAP_BCT_2TRANS     | \
151                                         EBC_BXAP_CSN_ENCODE(10) | \
152                                         EBC_BXAP_OEN_ENCODE(1)  | \
153                                         EBC_BXAP_WBN_ENCODE(1)  | \
154                                         EBC_BXAP_WBF_ENCODE(1)  | \
155                                         EBC_BXAP_TH_ENCODE(1)   | \
156                                         EBC_BXAP_RE_DISABLED    | \
157                                         EBC_BXAP_SOR_DELAYED    | \
158                                         EBC_BXAP_BEM_RW         | \
159                                         EBC_BXAP_PEN_DISABLED
160
161 #define EBC_BXCR_FPGA_CS1               EBC_BXCR_BAS_ENCODE(0xe2000000) | \
162                                         EBC_BXCR_BS_1MB                 | \
163                                         EBC_BXCR_BU_RW                  | \
164                                         EBC_BXCR_BW_16BIT
165
166          unsigned long mfr;
167         /*
168          * Define Variables for EBC initialization depending on BOOTSTRAP option
169          */
170         unsigned long sdr0_pinstp, sdr0_sdstp1 ;
171         unsigned long bootstrap_settings, ebc_data_width, boot_selection;
172         int computed_boot_device = BOOT_DEVICE_UNKNOWN;
173
174         /*-------------------------------------------------------------------+
175          | Initialize EBC CONFIG -
176          | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
177          | default value :
178          |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
179          |
180          +-------------------------------------------------------------------*/
181         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
182                         EBC_CFG_PTD_ENABLE |
183                         EBC_CFG_RTC_16PERCLK |
184                         EBC_CFG_ATC_PREVIOUS |
185                         EBC_CFG_DTC_PREVIOUS |
186                         EBC_CFG_CTC_PREVIOUS |
187                         EBC_CFG_OEO_PREVIOUS |
188                         EBC_CFG_EMC_DEFAULT |
189                         EBC_CFG_PME_DISABLE |
190                         EBC_CFG_PR_16);
191
192         /*-------------------------------------------------------------------+
193          |
194          |  PART 1 : Initialize EBC Bank 1
195          |  ==============================
196          | Bank1 is always associated to the EPLD.
197          | It has to be initialized prior to other banks settings computation
198          | since some board registers values may be needed to determine the
199          | boot type
200          |
201          +-------------------------------------------------------------------*/
202         mtebc(pb1ap, EBC_BXAP_FPGA);
203         mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
204
205         /*-------------------------------------------------------------------+
206          |
207          |  PART 2 : Determine which boot device was selected
208          |  =================================================
209          |
210          |  Read Pin Strap Register in PPC440SPe
211          |  Result can either be :
212          |   - Boot strap = boot from EBC 8bits     => Small Flash
213          |   - Boot strap = boot from PCI
214          |   - Boot strap = IIC
215          |  In case of boot from IIC, read Serial Device Strap Register1
216          |
217          |  Result can either be :
218          |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
219          |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
220          |   - Boot from PCI
221          |
222          +-------------------------------------------------------------------*/
223         /* Read Pin Strap Register in PPC440SP */
224         sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
225         bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
226
227         switch (bootstrap_settings) {
228                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
229                         /*
230                          * Strapping Option A
231                          * Boot from EBC - 8 bits , Small Flash
232                          */
233                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
234                         break;
235                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
236                         /*
237                          * Strappping Option B
238                          * Boot from PCI
239                          */
240                         computed_boot_device = BOOT_FROM_PCI;
241                         break;
242                 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
243                 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
244                         /*
245                          * Strapping Option C or D
246                          * Boot Settings in IIC EEprom address 0x50 or 0x54
247                          * Read Serial Device Strap Register1 in PPC440SPe
248                          */
249                         sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
250                         boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
251                         ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
252
253                         switch (boot_selection) {
254                                 case SDR0_SDSTP1_ERPN_EBC:
255                                         switch (ebc_data_width) {
256                                                 case SDR0_SDSTP1_EBCW_16_BITS:
257                                                         computed_boot_device =
258                                                                 BOOT_FROM_LARGE_FLASH_OR_SRAM;
259                                                         break;
260                                                 case SDR0_SDSTP1_EBCW_8_BITS :
261                                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
262                                                         break;
263                                         }
264                                         break;
265
266                                 case SDR0_SDSTP1_ERPN_PCI:
267                                         computed_boot_device = BOOT_FROM_PCI;
268                                         break;
269                                 default:
270                                         /* should not occure */
271                                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
272                         }
273                         break;
274                 default:
275                         /* should not be */
276                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
277                         break;
278         }
279
280         /*-------------------------------------------------------------------+
281          |
282          |  PART 3 : Compute EBC settings depending on selected boot device
283          |  ======   ======================================================
284          |
285          | Resulting EBC init will be among following configurations :
286          |
287          |  - Boot from EBC 8bits => boot from Small Flash selected
288          |            EBC-CS0     = Small Flash
289          |            EBC-CS2     = Large Flash and SRAM
290          |
291          |  - Boot from EBC 16bits => boot from Large Flash or SRAM
292          |            EBC-CS0     = Large Flash or SRAM
293          |            EBC-CS2     = Small Flash
294          |
295          |  - Boot from PCI
296          |            EBC-CS0     = not initialized to avoid address contention
297          |            EBC-CS2     = same as boot from Small Flash selected
298          |
299          +-------------------------------------------------------------------*/
300         unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
301         unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
302
303         switch (computed_boot_device) {
304                 /*-------------------------------------------------------------------*/
305                 case BOOT_FROM_PCI:
306                 /*-------------------------------------------------------------------*/
307                         /*
308                          * By Default CS2 is affected to LARGE Flash
309                          * do not initialize SMALL FLASH to avoid address contention
310                          * Large Flash
311                          */
312                         ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
313                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
314                         break;
315
316                 /*-------------------------------------------------------------------*/
317                 case BOOT_FROM_SMALL_FLASH:
318                 /*-------------------------------------------------------------------*/
319                         ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
320                         ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
321
322                         /*
323                          * Large Flash or SRAM
324                          */
325                         /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
326                         ebc0_cs2_bxap_value = 0x048ff240;
327                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
328                         break;
329
330                 /*-------------------------------------------------------------------*/
331                 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
332                 /*-------------------------------------------------------------------*/
333                         ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
334                         ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
335
336                         /* Small flash */
337                         ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
338                         ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
339                         break;
340
341                 /*-------------------------------------------------------------------*/
342                 default:
343                 /*-------------------------------------------------------------------*/
344                         /* BOOT_DEVICE_UNKNOWN */
345                         break;
346         }
347
348         mtebc(pb0ap, ebc0_cs0_bxap_value);
349         mtebc(pb0cr, ebc0_cs0_bxcr_value);
350         mtebc(pb2ap, ebc0_cs2_bxap_value);
351         mtebc(pb2cr, ebc0_cs2_bxcr_value);
352
353         /*--------------------------------------------------------------------+
354          | Interrupt controller setup for the AMCC 440SPe Evaluation board.
355          +--------------------------------------------------------------------+
356         +---------------------------------------------------------------------+
357         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
358         +---------+-----------------------------------+-------+-------+-------+
359         | IRQ 00  | UART0                             | High  | Level | Non   |
360         | IRQ 01  | UART1                             | High  | Level | Non   |
361         | IRQ 02  | IIC0                              | High  | Level | Non   |
362         | IRQ 03  | IIC1                              | High  | Level | Non   |
363         | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
364         | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
365         | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
366         | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
367         | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
368         | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
369         | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
370         | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
371         | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
372         | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
373         | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
374         | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
375         | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
376         | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
377         | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
378         | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
379         | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
380         | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
381         | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
382         | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
383         | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
384         | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
385         | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
386         | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
387         | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
388         | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
389         | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
390         | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
391         |----------------------------------------------------------------------
392         | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
393         | IRQ 33  | MAL Serr                          | High  | Level | Non   |
394         | IRQ 34  | MAL Txde                          | High  | Level | Non   |
395         | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
396         | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
397         | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
398         | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
399         | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
400         | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
401         | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
402         | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
403         | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
404         | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
405         | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
406         | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
407         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
408         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
409         | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
410         | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
411         | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
412         | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
413         | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
414         | IRQ 54  | DMA Error                         | High  | Level | Non   |
415         | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
416         | IRQ 56  | Serial ROM                        | High  | Level | Non   |
417         | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
418         | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
419         | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
420         | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
421         | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
422         | IRQ 62  | Reserved                          | High  | Level | Non   |
423         | IRQ 63  | XOR                               | High  | Level | Non   |
424         |----------------------------------------------------------------------
425         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
426         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
427         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
428         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
429         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
430         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
431         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
432         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
433         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
434         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
435         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
436         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
437         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
438         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
439         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
440         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
441         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
442         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
443         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
444         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
445         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
446         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
447         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
448         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
449         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
450         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
451         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
452         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
453         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
454         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
455         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
456         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
457         |---------------------------------------------------------------------
458         | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
459         | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
460         | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
461         | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
462         | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
463         | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
464         | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
465         | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
466         | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
467         | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
468         | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
469         | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
470         | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
471         | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
472         | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
473         | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
474         | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
475         | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
476         | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
477         | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
478         | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
479         | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
480         | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
481         | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
482         | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
483         | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
484         | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
485         | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
486         | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
487         | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
488         | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
489         | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
490         +---------+-----------------------------------+-------+-------+------*/
491         /*--------------------------------------------------------------------+
492          | Put UICs in PowerPC440SPemode.
493          | Initialise UIC registers.  Clear all interrupts.  Disable all
494          | interrupts.
495          | Set critical interrupt values.  Set interrupt polarities.  Set
496          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
497          | interrupts again.
498          +-------------------------------------------------------------------*/
499         mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
500         mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
501         mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
502                                          * interrupts */
503         mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
504         mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
505         mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
506                                          * priority */
507         mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
508         mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
509
510         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
511         mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
512         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
513                                          * interrupts */
514         mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
515         mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
516         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
517                                          * priority */
518         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
519         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
520
521         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
522         mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
523         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
524                                          * interrupts */
525         mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
526         mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
527         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
528                                          * priority */
529         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
530         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
531
532         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
533         mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
534                                          * cascade to be checked */
535         mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
536                                          * interrupts */
537         mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
538         mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
539         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
540                                          * priority */
541         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
542         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
543
544         /* SDR0_MFR should be part of Ethernet init */
545         mfsdr (sdr_mfr, mfr);
546         mfr &= ~SDR0_MFR_ECS_MASK;
547         /*mtsdr(sdr_mfr, mfr);*/
548         fpga_init();
549
550         return 0;
551 }
552
553 int checkboard (void)
554 {
555         char *s = getenv("serial#");
556
557         printf("Board: Yucca - AMCC 440SPe Evaluation Board");
558         if (s != NULL) {
559                 puts(", serial# ");
560                 puts(s);
561         }
562         putc('\n');
563
564         return 0;
565 }
566
567 static long int yucca_probe_for_dimms(void)
568 {
569         int     dimm_installed[MAXDIMMS];
570         int     dimm_num, result;
571         int     dimms_found = 0;
572         uchar   dimm_addr = IIC0_DIMM0_ADDR;
573         uchar   dimm_spd_data[MAX_SPD_BYTES];
574
575         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
576                 /* check if there is a chip at the dimm address */
577                 switch (dimm_num) {
578                         case 0:
579                                 dimm_addr = IIC0_DIMM0_ADDR;
580                                 break;
581                         case 1:
582                                 dimm_addr = IIC0_DIMM1_ADDR;
583                                 break;
584                 }
585
586                 result = i2c_probe(dimm_addr);
587
588                 memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
589                 if (result == 0) {
590                         /* read first byte of SPD data, if there is any data */
591                         result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
592
593                         if (result == 0) {
594                                 result = dimm_spd_data[0];
595                                 result = result > MAX_SPD_BYTES ?
596                                                 MAX_SPD_BYTES : result;
597                                 result = i2c_read(dimm_addr, 0, 1,
598                                                         dimm_spd_data, result);
599                         }
600                 }
601
602                 if ((result == 0) &&
603                     (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
604                         dimm_installed[dimm_num] = TRUE;
605                         dimms_found++;
606                         debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
607                 } else {
608                         dimm_installed[dimm_num] = FALSE;
609                         debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
610                 }
611         }
612
613         if (dimms_found == 0) {
614                 printf("ERROR - No memory installed.  Install a DDR-SDRAM DIMM.\n\n");
615                 hang();
616         }
617
618         if (dimm_installed[0] != TRUE) {
619                 printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
620                 printf("        Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
621                 hang();
622         }
623
624         return dimms_found;
625 }
626
627 /*************************************************************************
628  * init SDRAM controller with fixed value
629  * the initialization values are for 2x MICRON DDR2
630  * PN: MT18HTF6472DY-53EB2
631  * 512MB, DDR2, 533, CL4, ECC, REG
632  ************************************************************************/
633 static long int fixed_sdram(void)
634 {
635         long int yucca_dimms = 0;
636
637         yucca_dimms = yucca_probe_for_dimms();
638
639         /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT  */
640         mtdcr( 0x10, 0x00000021 );
641         mtdcr( 0x11, 0x84000000 );
642
643         /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2      */
644         mtdcr( 0x10, 0x00000020 );
645         mtdcr( 0x11, 0x2D122000 );
646
647         /* SET MCIF0_CODT   Die Termination On  */
648         mtdcr( 0x10, 0x00000026 );
649         if (yucca_dimms == 2)
650                 mtdcr( 0x11, 0x2A800021 );
651         else if (yucca_dimms == 1)
652                 mtdcr( 0x11, 0x02800021 );
653
654         /* On-Die Termination for Bank 0        */
655         mtdcr( 0x10, 0x00000022 );
656         if (yucca_dimms == 2)
657                 mtdcr( 0x11, 0x18000000 );
658         else if (yucca_dimms == 1)
659                 mtdcr( 0x11, 0x06000000 );
660
661         /*      On-Die Termination for Bank 1   */
662         mtdcr( 0x10, 0x00000023 );
663         if (yucca_dimms == 2)
664                 mtdcr( 0x11, 0x18000000 );
665         else if (yucca_dimms == 1)
666                 mtdcr( 0x11, 0x01800000 );
667
668         /*      On-Die Termination for Bank 2   */
669         mtdcr( 0x10, 0x00000024 );
670         if (yucca_dimms == 2)
671                 mtdcr( 0x11, 0x01800000 );
672         else if (yucca_dimms == 1)
673                 mtdcr( 0x11, 0x00000000 );
674
675         /*      On-Die Termination for Bank 3   */
676         mtdcr( 0x10, 0x00000025 );
677         if (yucca_dimms == 2)
678                 mtdcr( 0x11, 0x01800000 );
679         else if (yucca_dimms == 1)
680                 mtdcr( 0x11, 0x00000000 );
681
682         /* Refresh Time register (0x30) Refresh every 7.8125uS  */
683         mtdcr( 0x10, 0x00000030 );
684         mtdcr( 0x11, 0x08200000 );
685
686         /* SET MCIF0_MMODE       CL 4   */
687         mtdcr( 0x10, 0x00000088 );
688         mtdcr( 0x11, 0x00000642 );
689
690         /* MCIF0_MEMODE */
691         mtdcr( 0x10, 0x00000089 );
692         mtdcr( 0x11, 0x00000004 );
693
694         /*SET MCIF0_MB0CF       */
695         mtdcr( 0x10, 0x00000040 );
696         mtdcr( 0x11, 0x00000201 );
697
698         /* SET MCIF0_MB1CF      */
699         mtdcr( 0x10, 0x00000044 );
700         mtdcr( 0x11, 0x00000201 );
701
702         /* SET MCIF0_MB2CF      */
703         mtdcr( 0x10, 0x00000048 );
704         if (yucca_dimms == 2)
705                 mtdcr( 0x11, 0x00000201 );
706         else if (yucca_dimms == 1)
707                 mtdcr( 0x11, 0x00000000 );
708
709         /* SET MCIF0_MB3CF      */
710         mtdcr( 0x10, 0x0000004c );
711         if (yucca_dimms == 2)
712                 mtdcr( 0x11, 0x00000201 );
713         else if (yucca_dimms == 1)
714                 mtdcr( 0x11, 0x00000000 );
715
716         /* SET MCIF0_INITPLR0  # NOP            */
717         mtdcr( 0x10, 0x00000050 );
718         mtdcr( 0x11, 0xB5380000 );
719
720         /* SET MCIF0_INITPLR1  # PRE            */
721         mtdcr( 0x10, 0x00000051 );
722         mtdcr( 0x11, 0x82100400 );
723
724         /* SET MCIF0_INITPLR2  # EMR2           */
725         mtdcr( 0x10, 0x00000052 );
726         mtdcr( 0x11, 0x80820000 );
727
728         /* SET MCIF0_INITPLR3  # EMR3           */
729         mtdcr( 0x10, 0x00000053 );
730         mtdcr( 0x11, 0x80830000 );
731
732         /* SET MCIF0_INITPLR4  # EMR DLL ENABLE */
733         mtdcr( 0x10, 0x00000054 );
734         mtdcr( 0x11, 0x80810000 );
735
736         /* SET MCIF0_INITPLR5  # MR DLL RESET   */
737         mtdcr( 0x10, 0x00000055 );
738         mtdcr( 0x11, 0x80800542 );
739
740         /* SET MCIF0_INITPLR6  # PRE            */
741         mtdcr( 0x10, 0x00000056 );
742         mtdcr( 0x11, 0x82100400 );
743
744         /* SET MCIF0_INITPLR7  # Refresh        */
745         mtdcr( 0x10, 0x00000057 );
746         mtdcr( 0x11, 0x8A080000 );
747
748         /* SET MCIF0_INITPLR8  # Refresh        */
749         mtdcr( 0x10, 0x00000058 );
750         mtdcr( 0x11, 0x8A080000 );
751
752         /* SET MCIF0_INITPLR9  # Refresh        */
753         mtdcr( 0x10, 0x00000059 );
754         mtdcr( 0x11, 0x8A080000 );
755
756         /* SET MCIF0_INITPLR10 # Refresh        */
757         mtdcr( 0x10, 0x0000005A );
758         mtdcr( 0x11, 0x8A080000 );
759
760         /* SET MCIF0_INITPLR11 # MR             */
761         mtdcr( 0x10, 0x0000005B );
762         mtdcr( 0x11, 0x80800442 );
763
764         /* SET MCIF0_INITPLR12 # EMR OCD Default*/
765         mtdcr( 0x10, 0x0000005C );
766         mtdcr( 0x11, 0x80810380 );
767
768         /* SET MCIF0_INITPLR13 # EMR OCD Exit   */
769         mtdcr( 0x10, 0x0000005D );
770         mtdcr( 0x11, 0x80810000 );
771
772         /* 0x80: Adv Addr clock by 180 deg      */
773         mtdcr( 0x10, 0x00000080 );
774         mtdcr( 0x11, 0x80000000 );
775
776         /* 0x21: Exit self refresh, set DC_EN   */
777         mtdcr( 0x10, 0x00000021 );
778         mtdcr( 0x11, 0x28000000 );
779
780         /* 0x81: Write DQS Adv 90 + Fractional DQS Delay        */
781         mtdcr( 0x10, 0x00000081 );
782         mtdcr( 0x11, 0x80000800 );
783
784         /* MCIF0_SDTR1  */
785         mtdcr( 0x10, 0x00000085 );
786         mtdcr( 0x11, 0x80201000 );
787
788         /* MCIF0_SDTR2  */
789         mtdcr( 0x10, 0x00000086 );
790         mtdcr( 0x11, 0x42103242 );
791
792         /* MCIF0_SDTR3  */
793         mtdcr( 0x10, 0x00000087 );
794         mtdcr( 0x11, 0x0C100D14 );
795
796         /* SET MQ0_B0BAS  base addr 00000000 / 256MB    */
797         mtdcr( 0x40, 0x0000F800 );
798
799         /* SET MQ0_B1BAS  base addr 10000000 / 256MB    */
800         mtdcr( 0x41, 0x0400F800 );
801
802         /* SET MQ0_B2BAS  base addr 20000000 / 256MB    */
803         if (yucca_dimms == 2)
804                 mtdcr( 0x42, 0x0800F800 );
805         else if (yucca_dimms == 1)
806                 mtdcr( 0x42, 0x00000000 );
807
808         /* SET MQ0_B3BAS  base addr 30000000 / 256MB    */
809         if (yucca_dimms == 2)
810                 mtdcr( 0x43, 0x0C00F800 );
811         else if (yucca_dimms == 1)
812                 mtdcr( 0x43, 0x00000000 );
813
814         /* SDRAM_RQDC   */
815         mtdcr( 0x10, 0x00000070 );
816         mtdcr( 0x11, 0x8000003F );
817
818         /* SDRAM_RDCC   */
819         mtdcr( 0x10, 0x00000078 );
820         mtdcr( 0x11, 0x80000000 );
821
822         /* SDRAM_RFDC   */
823         mtdcr( 0x10, 0x00000074 );
824         mtdcr( 0x11, 0x00000220 );
825
826         return (yucca_dimms * 512) << 20;
827 }
828
829 long int initdram (int board_type)
830 {
831         long dram_size = 0;
832
833         dram_size = fixed_sdram();
834
835         return dram_size;
836 }
837
838 #if defined(CFG_DRAM_TEST)
839 int testdram (void)
840 {
841         uint *pstart = (uint *) 0x00000000;
842         uint *pend = (uint *) 0x08000000;
843         uint *p;
844
845         for (p = pstart; p < pend; p++)
846                 *p = 0xaaaaaaaa;
847
848         for (p = pstart; p < pend; p++) {
849                 if (*p != 0xaaaaaaaa) {
850                         printf ("SDRAM test fails at: %08x\n", (uint) p);
851                         return 1;
852                 }
853         }
854
855         for (p = pstart; p < pend; p++)
856                 *p = 0x55555555;
857
858         for (p = pstart; p < pend; p++) {
859                 if (*p != 0x55555555) {
860                         printf ("SDRAM test fails at: %08x\n", (uint) p);
861                         return 1;
862                 }
863         }
864         return 0;
865 }
866 #endif
867
868 /*************************************************************************
869  *  pci_pre_init
870  *
871  *  This routine is called just prior to registering the hose and gives
872  *  the board the opportunity to check things. Returning a value of zero
873  *  indicates that things are bad & PCI initialization should be aborted.
874  *
875  *      Different boards may wish to customize the pci controller structure
876  *      (add regions, override default access routines, etc) or perform
877  *      certain pre-initialization actions.
878  *
879  ************************************************************************/
880 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
881 int pci_pre_init(struct pci_controller * hose )
882 {
883         unsigned long strap;
884
885         /*-------------------------------------------------------------------+
886          *      The yucca board is always configured as the host & requires the
887          *      PCI arbiter to be enabled.
888          *-------------------------------------------------------------------*/
889         mfsdr(sdr_sdstp1, strap);
890         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
891                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
892                 return 0;
893         }
894
895         return 1;
896 }
897 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
898
899 /*************************************************************************
900  *  pci_target_init
901  *
902  *      The bootstrap configuration provides default settings for the pci
903  *      inbound map (PIM). But the bootstrap config choices are limited and
904  *      may not be sufficient for a given board.
905  *
906  ************************************************************************/
907 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
908 void pci_target_init(struct pci_controller * hose )
909 {
910         DECLARE_GLOBAL_DATA_PTR;
911
912         /*-------------------------------------------------------------------+
913          * Disable everything
914          *-------------------------------------------------------------------*/
915         out32r( PCIX0_PIM0SA, 0 ); /* disable */
916         out32r( PCIX0_PIM1SA, 0 ); /* disable */
917         out32r( PCIX0_PIM2SA, 0 ); /* disable */
918         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
919
920         /*-------------------------------------------------------------------+
921          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
922          * strapping options to not support sizes such as 128/256 MB.
923          *-------------------------------------------------------------------*/
924         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
925         out32r( PCIX0_PIM0LAH, 0 );
926         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
927         out32r( PCIX0_BAR0, 0 );
928
929         /*-------------------------------------------------------------------+
930          * Program the board's subsystem id/vendor id
931          *-------------------------------------------------------------------*/
932         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
933         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
934
935         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
936 }
937 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
938
939 #if defined(CONFIG_PCI)
940 /*************************************************************************
941  *  is_pci_host
942  *
943  *      This routine is called to determine if a pci scan should be
944  *      performed. With various hardware environments (especially cPCI and
945  *      PPMC) it's insufficient to depend on the state of the arbiter enable
946  *      bit in the strap register, or generic host/adapter assumptions.
947  *
948  *      Rather than hard-code a bad assumption in the general 440 code, the
949  *      440 pci code requires the board to decide at runtime.
950  *
951  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
952  *
953  *
954  ************************************************************************/
955 int is_pci_host(struct pci_controller *hose)
956 {
957         /* The yucca board is always configured as host. */
958         return 1;
959 }
960
961
962 int yucca_pcie_card_present(int port)
963 {
964         u16 reg;
965
966         reg = in_be16((u16 *)FPGA_REG1C);
967         switch(port) {
968         case 0:
969                 return !(reg & FPGA_REG1C_PE0_PRSNT);
970         case 1:
971                 return !(reg & FPGA_REG1C_PE1_PRSNT);
972         case 2:
973                 return !(reg & FPGA_REG1C_PE2_PRSNT);
974         default:
975                 return 0;
976         }
977 }
978
979 /*
980  * For the given slot, set rootpoint mode, send power to the slot,
981  * turn on the green LED and turn off the yellow LED, enable the clock
982  * and turn off reset.
983  */
984 void yucca_setup_pcie_fpga_rootpoint(int port)
985 {
986         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
987
988         switch(port) {
989         case 0:
990                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
991                 endpoint    = 0;
992                 power       = FPGA_REG1A_PE0_PWRON;
993                 green_led   = FPGA_REG1A_PE0_GLED;
994                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
995                 yellow_led  = FPGA_REG1A_PE0_YLED;
996                 reset_off   = FPGA_REG1C_PE0_PERST;
997                 break;
998         case 1:
999                 rootpoint   = 0;
1000                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
1001                 power       = FPGA_REG1A_PE1_PWRON;
1002                 green_led   = FPGA_REG1A_PE1_GLED;
1003                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
1004                 yellow_led  = FPGA_REG1A_PE1_YLED;
1005                 reset_off   = FPGA_REG1C_PE1_PERST;
1006                 break;
1007         case 2:
1008                 rootpoint   = 0;
1009                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
1010                 power       = FPGA_REG1A_PE2_PWRON;
1011                 green_led   = FPGA_REG1A_PE2_GLED;
1012                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
1013                 yellow_led  = FPGA_REG1A_PE2_YLED;
1014                 reset_off   = FPGA_REG1C_PE2_PERST;
1015                 break;
1016
1017         default:
1018                 return;
1019         }
1020
1021         out_be16((u16 *)FPGA_REG1A,
1022                  ~(power | clock | green_led) &
1023                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
1024
1025         out_be16((u16 *)FPGA_REG1C,
1026                  ~(endpoint | reset_off) &
1027                  (rootpoint | in_be16((u16 *)FPGA_REG1C)));
1028         /*
1029          * Leave device in reset for a while after powering on the
1030          * slot to give it a chance to initialize.
1031          */
1032         udelay(250 * 1000);
1033
1034         out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
1035 }
1036 /*
1037  * For the given slot, set endpoint mode, send power to the slot,
1038  * turn on the green LED and turn off the yellow LED, enable the clock
1039  * .In end point mode reset bit is  read only.
1040  */
1041 void yucca_setup_pcie_fpga_endpoint(int port)
1042 {
1043         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
1044
1045         switch(port) {
1046         case 0:
1047                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
1048                 endpoint    = 0;
1049                 power       = FPGA_REG1A_PE0_PWRON;
1050                 green_led   = FPGA_REG1A_PE0_GLED;
1051                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
1052                 yellow_led  = FPGA_REG1A_PE0_YLED;
1053                 reset_off   = FPGA_REG1C_PE0_PERST;
1054                 break;
1055         case 1:
1056                 rootpoint   = 0;
1057                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
1058                 power       = FPGA_REG1A_PE1_PWRON;
1059                 green_led   = FPGA_REG1A_PE1_GLED;
1060                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
1061                 yellow_led  = FPGA_REG1A_PE1_YLED;
1062                 reset_off   = FPGA_REG1C_PE1_PERST;
1063                 break;
1064         case 2:
1065                 rootpoint   = 0;
1066                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
1067                 power       = FPGA_REG1A_PE2_PWRON;
1068                 green_led   = FPGA_REG1A_PE2_GLED;
1069                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
1070                 yellow_led  = FPGA_REG1A_PE2_YLED;
1071                 reset_off   = FPGA_REG1C_PE2_PERST;
1072                 break;
1073
1074         default:
1075                 return;
1076         }
1077
1078         out_be16((u16 *)FPGA_REG1A,
1079                  ~(power | clock | green_led) &
1080                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
1081
1082         out_be16((u16 *)FPGA_REG1C,
1083                  ~(rootpoint | reset_off) &
1084                  (endpoint | in_be16((u16 *)FPGA_REG1C)));
1085 }
1086
1087
1088
1089 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
1090
1091 void pcie_setup_hoses(void)
1092 {
1093         struct pci_controller *hose;
1094         int i, bus;
1095
1096         /*
1097          * assume we're called after the PCIX hose is initialized, which takes
1098          * bus ID 0 and therefore start numbering PCIe's from 1.
1099          */
1100         bus = 1;
1101         for (i = 0; i <= 2; i++) {
1102                 /* Check for yucca card presence */
1103                 if (!yucca_pcie_card_present(i))
1104                         continue;
1105
1106 #ifdef PCIE_ENDPOINT
1107                 yucca_setup_pcie_fpga_endpoint(i);
1108                 if (ppc440spe_init_pcie_endport(i)) {
1109 #else
1110                 yucca_setup_pcie_fpga_rootpoint(i);
1111                 if (ppc440spe_init_pcie_rootport(i)) {
1112 #endif
1113                         printf("PCIE%d: initialization failed\n", i);
1114                         continue;
1115                 }
1116
1117                 hose = &pcie_hose[i];
1118                 hose->first_busno = bus;
1119                 hose->last_busno  = bus;
1120                 bus++;
1121
1122                 /* setup mem resource */
1123                 pci_set_region(hose->regions + 0,
1124                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
1125                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
1126                         CFG_PCIE_MEMSIZE,
1127                         PCI_REGION_MEM
1128                         );
1129                 hose->region_count = 1;
1130                 pci_register_hose(hose);
1131
1132 #ifdef PCIE_ENDPOINT
1133                 ppc440spe_setup_pcie_endpoint(hose, i);
1134                 /*
1135                  * Reson for no scanning is endpoint can not generate
1136                  * upstream configuration accesses.
1137                  */
1138 #else
1139                 ppc440spe_setup_pcie_rootpoint(hose, i);
1140                 /*
1141                  * Config access can only go down stream
1142                  */
1143                 hose->last_busno = pci_hose_scan(hose);
1144 #endif
1145         }
1146 }
1147 #endif  /* defined(CONFIG_PCI) */
1148
1149 int misc_init_f (void)
1150 {
1151         uint reg;
1152 #if defined(CONFIG_STRESS)
1153         uint i ;
1154         uint disp;
1155 #endif
1156
1157         out16(FPGA_REG10, (in16(FPGA_REG10) &
1158                         ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
1159                                 FPGA_REG10_10MHZ_ENABLE |
1160                                 FPGA_REG10_100MHZ_ENABLE |
1161                                 FPGA_REG10_GIGABIT_ENABLE |
1162                                 FPGA_REG10_FULL_DUPLEX );
1163
1164         udelay(10000);  /* wait 10ms */
1165
1166         out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
1167
1168         /* minimal init for PCIe */
1169         /* pci express 0 Endpoint Mode */
1170         mfsdr(SDR0_PE0DLPSET, reg);
1171         reg &= (~0x00400000);
1172         mtsdr(SDR0_PE0DLPSET, reg);
1173         /* pci express 1 Rootpoint  Mode */
1174         mfsdr(SDR0_PE1DLPSET, reg);
1175         reg |= 0x00400000;
1176         mtsdr(SDR0_PE1DLPSET, reg);
1177         /* pci express 2 Rootpoint  Mode */
1178         mfsdr(SDR0_PE2DLPSET, reg);
1179         reg |= 0x00400000;
1180         mtsdr(SDR0_PE2DLPSET, reg);
1181
1182         out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
1183                                 ~FPGA_REG1C_PE0_ROOTPOINT &
1184                                 ~FPGA_REG1C_PE1_ENDPOINT  &
1185                                 ~FPGA_REG1C_PE2_ENDPOINT));
1186
1187 #if defined(CONFIG_STRESS)
1188         /*
1189          * all this setting done by linux only needed by stress an charac. test
1190          * procedure
1191          * PCIe 1 Rootpoint PCIe2 Endpoint
1192          * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1193          * Power Level
1194          */
1195         for (i = 0, disp = 0; i < 8; i++, disp += 3) {
1196                 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
1197                 reg |= 0x33000000;
1198                 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
1199         }
1200
1201         /*
1202          * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1203          * Power Level
1204          */
1205         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
1206                 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
1207                 reg |= 0x33000000;
1208                 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
1209         }
1210
1211         /*
1212          * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1213          * Power Level
1214          */
1215         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
1216                 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1217                 reg |= 0x33000000;
1218                 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1219         }
1220
1221         reg = 0x21242222;
1222         mtsdr(SDR0_PE2UTLSET1, reg);
1223         reg = 0x11000000;
1224         mtsdr(SDR0_PE2UTLSET2, reg);
1225         /* pci express 1 Endpoint  Mode */
1226         reg = 0x00004000;
1227         mtsdr(SDR0_PE2DLPSET, reg);
1228
1229         mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
1230 #endif
1231         return 0;
1232 }
1233
1234 void fpga_init(void)
1235 {
1236         /*
1237          * by default sdram access is disabled by fpga
1238          */
1239         out16(FPGA_REG10, (in16 (FPGA_REG10) |
1240                                 FPGA_REG10_SDRAM_ENABLE |
1241                                 FPGA_REG10_ENABLE_DISPLAY ));
1242
1243         return;
1244 }
1245
1246 #ifdef CONFIG_POST
1247 /*
1248  * Returns 1 if keys pressed to start the power-on long-running tests
1249  * Called from board_init_f().
1250  */
1251 int post_hotkeys_pressed(void)
1252 {
1253         return (ctrlc());
1254 }
1255 #endif
1256
1257 /*---------------------------------------------------------------------------+
1258  | onboard_pci_arbiter_selected => from EPLD
1259  +---------------------------------------------------------------------------*/
1260 int onboard_pci_arbiter_selected(int core_pci)
1261 {
1262 #if 0
1263         unsigned long onboard_pci_arbiter_sel;
1264
1265         onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1266
1267         if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1268                 return (BOARD_OPTION_SELECTED);
1269         else
1270 #endif
1271         return (BOARD_OPTION_NOT_SELECTED);
1272 }
1273
1274 /*---------------------------------------------------------------------------+
1275  | ppcMfcpr.
1276  +---------------------------------------------------------------------------*/
1277 unsigned long ppcMfcpr(unsigned long cpr_reg)
1278 {
1279         unsigned long msr;
1280         unsigned long cpr_cfgaddr_temp;
1281         unsigned long cpr_value;
1282
1283         msr = (mfmsr () & ~(MSR_EE));
1284         cpr_cfgaddr_temp =  mfdcr(CPR0_CFGADDR);
1285         mtdcr(CPR0_CFGADDR, cpr_reg);
1286         cpr_value =  mfdcr(CPR0_CFGDATA);
1287         mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
1288         mtmsr(msr);
1289
1290         return (cpr_value);
1291 }
1292
1293 /*----------------------------------------------------------------------------+
1294 | Indirect Access of the System DCR's (SDR)
1295 | ppcMfsdr
1296 +----------------------------------------------------------------------------*/
1297 unsigned long ppcMfsdr(unsigned long sdr_reg)
1298 {
1299         unsigned long msr;
1300         unsigned long sdr_cfgaddr_temp;
1301         unsigned long sdr_value;
1302
1303         msr = (mfmsr () & ~(MSR_EE));
1304         sdr_cfgaddr_temp =  mfdcr(SDR0_CFGADDR);
1305         mtdcr(SDR0_CFGADDR, sdr_reg);
1306         sdr_value =  mfdcr(SDR0_CFGDATA);
1307         mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
1308         mtmsr(msr);
1309
1310         return (sdr_value);
1311 }