board/amcc/yucca/yucca.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Port to AMCC-440SPE Evaluation Board SOP - April 2005
  24  *
  25  * PCIe supporting routines derived from Linux 440SPe PCIe driver.
  26  */
  27
  28 #include <common.h>
  29 #include <ppc4xx.h>
  30 #include <asm/processor.h>
  31 #include <i2c.h>
  32 #include <asm-ppc/io.h>
  33
  34 #include "yucca.h"
  35
  36 void fpga_init (void);
  37
  38 void get_sys_info(PPC440_SYS_INFO *board_cfg );
  39 int compare_to_true(char *str );
  40 char *remove_l_w_space(char *in_str );
  41 char *remove_t_w_space(char *in_str );
  42 int get_console_port(void);
  43 unsigned long ppcMfcpr(unsigned long cpr_reg);
  44 unsigned long ppcMfsdr(unsigned long sdr_reg);
  45
  46 int ppc440spe_init_pcie_rootport(int port);
  47 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
  48
  49 #define DEBUG_ENV
  50 #ifdef DEBUG_ENV
  51 #define DEBUGF(fmt,args...) printf(fmt ,##args)
  52 #else
  53 #define DEBUGF(fmt,args...)
  54 #endif
  55
  56 #define FALSE   0
  57 #define TRUE    1
  58
  59 int board_early_init_f (void)
  60 {
  61 /*----------------------------------------------------------------------------+
  62 | Define Boot devices
  63 +----------------------------------------------------------------------------*/
  64 #define BOOT_FROM_SMALL_FLASH           0x00
  65 #define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
  66 #define BOOT_FROM_PCI                   0x02
  67 #define BOOT_DEVICE_UNKNOWN             0x03
  68
  69 /*----------------------------------------------------------------------------+
  70 | EBC Devices Characteristics
  71 |   Peripheral Bank Access Parameters       -   EBC_BxAP
  72 |   Peripheral Bank Configuration Register  -   EBC_BxCR
  73 +----------------------------------------------------------------------------*/
  74
  75 /*
  76  * Small Flash and FRAM
  77  * BU Value
  78  * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
  79  * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
  80  * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
  81  */
  82 #define EBC_BXAP_SMALL_FLASH            EBC_BXAP_BME_DISABLED   | \
  83                                         EBC_BXAP_TWT_ENCODE(7)  | \
  84                                         EBC_BXAP_BCE_DISABLE    | \
  85                                         EBC_BXAP_BCT_2TRANS     | \
  86                                         EBC_BXAP_CSN_ENCODE(0)  | \
  87                                         EBC_BXAP_OEN_ENCODE(0)  | \
  88                                         EBC_BXAP_WBN_ENCODE(0)  | \
  89                                         EBC_BXAP_WBF_ENCODE(0)  | \
  90                                         EBC_BXAP_TH_ENCODE(0)   | \
  91                                         EBC_BXAP_RE_DISABLED    | \
  92                                         EBC_BXAP_SOR_DELAYED    | \
  93                                         EBC_BXAP_BEM_WRITEONLY  | \
  94                                         EBC_BXAP_PEN_DISABLED
  95
  96 #define EBC_BXCR_SMALL_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
  97                                         EBC_BXCR_BS_16MB                | \
  98                                         EBC_BXCR_BU_RW                  | \
  99                                         EBC_BXCR_BW_8BIT
 100
 101 #define EBC_BXCR_SMALL_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xe7000000) | \
 102                                         EBC_BXCR_BS_16MB                | \
 103                                         EBC_BXCR_BU_RW                  | \
 104                                         EBC_BXCR_BW_8BIT
 105
 106 /*
 107  * Large Flash and SRAM
 108  * BU Value
 109  * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 110  * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
 111  * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
 112 */
 113 #define EBC_BXAP_LARGE_FLASH            EBC_BXAP_BME_DISABLED   | \
 114                                         EBC_BXAP_TWT_ENCODE(7)  | \
 115                                         EBC_BXAP_BCE_DISABLE    | \
 116                                         EBC_BXAP_BCT_2TRANS     | \
 117                                         EBC_BXAP_CSN_ENCODE(0)  | \
 118                                         EBC_BXAP_OEN_ENCODE(0)  | \
 119                                         EBC_BXAP_WBN_ENCODE(0)  | \
 120                                         EBC_BXAP_WBF_ENCODE(0)  | \
 121                                         EBC_BXAP_TH_ENCODE(0)   | \
 122                                         EBC_BXAP_RE_DISABLED    | \
 123                                         EBC_BXAP_SOR_DELAYED    | \
 124                                         EBC_BXAP_BEM_WRITEONLY  | \
 125                                         EBC_BXAP_PEN_DISABLED
 126
 127 #define EBC_BXCR_LARGE_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
 128                                         EBC_BXCR_BS_16MB                | \
 129                                         EBC_BXCR_BU_RW                  | \
 130                                         EBC_BXCR_BW_16BIT
 131
 132 #define EBC_BXCR_LARGE_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xE7000000) | \
 133                                         EBC_BXCR_BS_16MB                | \
 134                                         EBC_BXCR_BU_RW                  | \
 135                                         EBC_BXCR_BW_16BIT
 136
 137 /*
 138  * FPGA
 139  * BU value :
 140  * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
 141  * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
 142  */
 143 #define EBC_BXAP_FPGA                   EBC_BXAP_BME_DISABLED   | \
 144                                         EBC_BXAP_TWT_ENCODE(11) | \
 145                                         EBC_BXAP_BCE_DISABLE    | \
 146                                         EBC_BXAP_BCT_2TRANS     | \
 147                                         EBC_BXAP_CSN_ENCODE(10) | \
 148                                         EBC_BXAP_OEN_ENCODE(1)  | \
 149                                         EBC_BXAP_WBN_ENCODE(1)  | \
 150                                         EBC_BXAP_WBF_ENCODE(1)  | \
 151                                         EBC_BXAP_TH_ENCODE(1)   | \
 152                                         EBC_BXAP_RE_DISABLED    | \
 153                                         EBC_BXAP_SOR_DELAYED    | \
 154                                         EBC_BXAP_BEM_RW         | \
 155                                         EBC_BXAP_PEN_DISABLED
 156
 157 #define EBC_BXCR_FPGA_CS1               EBC_BXCR_BAS_ENCODE(0xe2000000) | \
 158                                         EBC_BXCR_BS_1MB                 | \
 159                                         EBC_BXCR_BU_RW                  | \
 160                                         EBC_BXCR_BW_16BIT
 161
 162          unsigned long mfr;
 163         /*
 164          * Define Variables for EBC initialization depending on BOOTSTRAP option
 165          */
 166         unsigned long sdr0_pinstp, sdr0_sdstp1 ;
 167         unsigned long bootstrap_settings, ebc_data_width, boot_selection;
 168         int computed_boot_device = BOOT_DEVICE_UNKNOWN;
 169
 170         /*-------------------------------------------------------------------+
 171          | Initialize EBC CONFIG -
 172          | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 173          | default value :
 174          |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 175          |
 176          +-------------------------------------------------------------------*/
 177         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
 178                         EBC_CFG_PTD_ENABLE |
 179                         EBC_CFG_RTC_16PERCLK |
 180                         EBC_CFG_ATC_PREVIOUS |
 181                         EBC_CFG_DTC_PREVIOUS |
 182                         EBC_CFG_CTC_PREVIOUS |
 183                         EBC_CFG_OEO_PREVIOUS |
 184                         EBC_CFG_EMC_DEFAULT |
 185                         EBC_CFG_PME_DISABLE |
 186                         EBC_CFG_PR_16);
 187
 188         /*-------------------------------------------------------------------+
 189          |
 190          |  PART 1 : Initialize EBC Bank 1
 191          |  ==============================
 192          | Bank1 is always associated to the EPLD.
 193          | It has to be initialized prior to other banks settings computation
 194          | since some board registers values may be needed to determine the
 195          | boot type
 196          |
 197          +-------------------------------------------------------------------*/
 198         mtebc(pb1ap, EBC_BXAP_FPGA);
 199         mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
 200
 201         /*-------------------------------------------------------------------+
 202          |
 203          |  PART 2 : Determine which boot device was selected
 204          |  =================================================
 205          |
 206          |  Read Pin Strap Register in PPC440SPe
 207          |  Result can either be :
 208          |   - Boot strap = boot from EBC 8bits     => Small Flash
 209          |   - Boot strap = boot from PCI
 210          |   - Boot strap = IIC
 211          |  In case of boot from IIC, read Serial Device Strap Register1
 212          |
 213          |  Result can either be :
 214          |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
 215          |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
 216          |   - Boot from PCI
 217          |
 218          +-------------------------------------------------------------------*/
 219         /* Read Pin Strap Register in PPC440SP */
 220         sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
 221         bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
 222
 223         switch (bootstrap_settings) {
 224                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
 225                         /*
 226                          * Strapping Option A
 227                          * Boot from EBC - 8 bits , Small Flash
 228                          */
 229                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 230                         break;
 231                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
 232                         /*
 233                          * Strappping Option B
 234                          * Boot from PCI
 235                          */
 236                         computed_boot_device = BOOT_FROM_PCI;
 237                         break;
 238                 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
 239                 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
 240                         /*
 241                          * Strapping Option C or D
 242                          * Boot Settings in IIC EEprom address 0x50 or 0x54
 243                          * Read Serial Device Strap Register1 in PPC440SPe
 244                          */
 245                         sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
 246                         boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
 247                         ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
 248
 249                         switch (boot_selection) {
 250                                 case SDR0_SDSTP1_ERPN_EBC:
 251                                         switch (ebc_data_width) {
 252                                                 case SDR0_SDSTP1_EBCW_16_BITS:
 253                                                         computed_boot_device =
 254                                                                 BOOT_FROM_LARGE_FLASH_OR_SRAM;
 255                                                         break;
 256                                                 case SDR0_SDSTP1_EBCW_8_BITS :
 257                                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 258                                                         break;
 259                                         }
 260                                         break;
 261
 262                                 case SDR0_SDSTP1_ERPN_PCI:
 263                                         computed_boot_device = BOOT_FROM_PCI;
 264                                         break;
 265                                 default:
 266                                         /* should not occure */
 267                                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 268                         }
 269                         break;
 270                 default:
 271                         /* should not be */
 272                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 273                         break;
 274         }
 275
 276         /*-------------------------------------------------------------------+
 277          |
 278          |  PART 3 : Compute EBC settings depending on selected boot device
 279          |  ======   ======================================================
 280          |
 281          | Resulting EBC init will be among following configurations :
 282          |
 283          |  - Boot from EBC 8bits => boot from Small Flash selected
 284          |            EBC-CS0     = Small Flash
 285          |            EBC-CS2     = Large Flash and SRAM
 286          |
 287          |  - Boot from EBC 16bits => boot from Large Flash or SRAM
 288          |            EBC-CS0     = Large Flash or SRAM
 289          |            EBC-CS2     = Small Flash
 290          |
 291          |  - Boot from PCI
 292          |            EBC-CS0     = not initialized to avoid address contention
 293          |            EBC-CS2     = same as boot from Small Flash selected
 294          |
 295          +-------------------------------------------------------------------*/
 296         unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
 297         unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
 298
 299         switch (computed_boot_device) {
 300                 /*-------------------------------------------------------------------*/
 301                 case BOOT_FROM_PCI:
 302                 /*-------------------------------------------------------------------*/
 303                         /*
 304                          * By Default CS2 is affected to LARGE Flash
 305                          * do not initialize SMALL FLASH to avoid address contention
 306                          * Large Flash
 307                          */
 308                         ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
 309                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 310                         break;
 311
 312                 /*-------------------------------------------------------------------*/
 313                 case BOOT_FROM_SMALL_FLASH:
 314                 /*-------------------------------------------------------------------*/
 315                         ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
 316                         ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
 317
 318                         /*
 319                          * Large Flash or SRAM
 320                          */
 321                         /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
 322                         ebc0_cs2_bxap_value = 0x048ff240;
 323                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 324                         break;
 325
 326                 /*-------------------------------------------------------------------*/
 327                 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 328                 /*-------------------------------------------------------------------*/
 329                         ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
 330                         ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
 331
 332                         /* Small flash */
 333                         ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
 334                         ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
 335                         break;
 336
 337                 /*-------------------------------------------------------------------*/
 338                 default:
 339                 /*-------------------------------------------------------------------*/
 340                         /* BOOT_DEVICE_UNKNOWN */
 341                         break;
 342         }
 343
 344         mtebc(pb0ap, ebc0_cs0_bxap_value);
 345         mtebc(pb0cr, ebc0_cs0_bxcr_value);
 346         mtebc(pb2ap, ebc0_cs2_bxap_value);
 347         mtebc(pb2cr, ebc0_cs2_bxcr_value);
 348
 349         /*--------------------------------------------------------------------+
 350          | Interrupt controller setup for the AMCC 440SPe Evaluation board.
 351          +--------------------------------------------------------------------+
 352         +---------------------------------------------------------------------+
 353         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
 354         +---------+-----------------------------------+-------+-------+-------+
 355         | IRQ 00  | UART0                             | High  | Level | Non   |
 356         | IRQ 01  | UART1                             | High  | Level | Non   |
 357         | IRQ 02  | IIC0                              | High  | Level | Non   |
 358         | IRQ 03  | IIC1                              | High  | Level | Non   |
 359         | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
 360         | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
 361         | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
 362         | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
 363         | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
 364         | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
 365         | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
 366         | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
 367         | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
 368         | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
 369         | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
 370         | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
 371         | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
 372         | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
 373         | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
 374         | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
 375         | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
 376         | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
 377         | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
 378         | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
 379         | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
 380         | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
 381         | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
 382         | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
 383         | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
 384         | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
 385         | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
 386         | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
 387         |----------------------------------------------------------------------
 388         | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
 389         | IRQ 33  | MAL Serr                          | High  | Level | Non   |
 390         | IRQ 34  | MAL Txde                          | High  | Level | Non   |
 391         | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
 392         | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
 393         | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
 394         | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
 395         | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
 396         | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
 397         | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
 398         | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
 399         | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
 400         | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
 401         | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
 402         | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
 403         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
 404         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
 405         | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
 406         | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
 407         | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
 408         | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
 409         | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
 410         | IRQ 54  | DMA Error                         | High  | Level | Non   |
 411         | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
 412         | IRQ 56  | Serial ROM                        | High  | Level | Non   |
 413         | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
 414         | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
 415         | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
 416         | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
 417         | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
 418         | IRQ 62  | Reserved                          | High  | Level | Non   |
 419         | IRQ 63  | XOR                               | High  | Level | Non   |
 420         |----------------------------------------------------------------------
 421         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
 422         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
 423         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 424         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 425         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
 426         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 427         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
 428         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
 429         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
 430         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
 431         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 432         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 433         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
 434         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 435         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
 436         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
 437         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
 438         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
 439         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 440         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 441         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
 442         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 443         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
 444         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
 445         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
 446         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 447         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 448         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 449         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 450         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 451         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
 452         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
 453         |---------------------------------------------------------------------
 454         | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
 455         | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
 456         | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
 457         | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
 458         | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
 459         | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
 460         | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
 461         | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
 462         | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
 463         | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
 464         | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
 465         | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
 466         | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
 467         | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
 468         | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
 469         | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
 470         | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
 471         | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
 472         | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
 473         | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
 474         | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
 475         | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
 476         | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
 477         | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
 478         | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
 479         | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
 480         | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
 481         | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
 482         | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
 483         | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
 484         | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
 485         | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
 486         +---------+-----------------------------------+-------+-------+------*/
 487         /*--------------------------------------------------------------------+
 488          | Put UICs in PowerPC440SPemode.
 489          | Initialise UIC registers.  Clear all interrupts.  Disable all
 490          | interrupts.
 491          | Set critical interrupt values.  Set interrupt polarities.  Set
 492          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 493          | interrupts again.
 494          +-------------------------------------------------------------------*/
 495         mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
 496         mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
 497         mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
 498                                          * interrupts */
 499         mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
 500         mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
 501         mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 502                                          * priority */
 503         mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
 504         mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
 505
 506         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
 507         mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
 508         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
 509                                          * interrupts */
 510         mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
 511         mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
 512         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 513                                          * priority */
 514         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
 515         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
 516
 517         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
 518         mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
 519         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
 520                                          * interrupts */
 521         mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
 522         mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
 523         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 524                                          * priority */
 525         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
 526         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
 527
 528         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
 529         mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
 530                                          * cascade to be checked */
 531         mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
 532                                          * interrupts */
 533         mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
 534         mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
 535         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 536                                          * priority */
 537         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
 538         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
 539
 540         /* SDR0_MFR should be part of Ethernet init */
 541         mfsdr (sdr_mfr, mfr);
 542         mfr &= ~SDR0_MFR_ECS_MASK;
 543         /*mtsdr(sdr_mfr, mfr);*/
 544         fpga_init();
 545
 546         return 0;
 547 }
 548
 549 int checkboard (void)
 550 {
 551         char *s = getenv("serial#");
 552
 553         printf("Board: Yucca - AMCC 440SPe Evaluation Board");
 554         if (s != NULL) {
 555                 puts(", serial# ");
 556                 puts(s);
 557         }
 558         putc('\n');
 559
 560         return 0;
 561 }
 562
 563 static long int yucca_probe_for_dimms(void)
 564 {
 565         long int        dimm_installed[MAXDIMMS];
 566         long int        dimm_num, probe_result;
 567         long int        dimms_found = 0;
 568         uchar           dimm_addr = IIC0_DIMM0_ADDR;
 569
 570         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
 571                 /* check if there is a chip at the dimm address */
 572                 switch (dimm_num) {
 573                         case 0:
 574                                 dimm_addr = IIC0_DIMM0_ADDR;
 575                                 break;
 576                         case 1:
 577                                 dimm_addr = IIC0_DIMM1_ADDR;
 578                                 break;
 579                 }
 580                 probe_result = i2c_probe(dimm_addr);
 581
 582                 if (probe_result == 0) {
 583                         dimm_installed[dimm_num] = TRUE;
 584                         dimms_found++;
 585                         debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num);
 586                 } else {
 587                         dimm_installed[dimm_num] = FALSE;
 588                         debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
 589                 }
 590         }
 591
 592         if (dimms_found == 0) {
 593                 printf("ERROR - No memory installed.  Install a DDR-SDRAM DIMM.\n\n");
 594                 hang();
 595         }
 596
 597         if (dimm_installed[0] != TRUE) {
 598                 printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
 599                 printf("        Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
 600                 hang();
 601         }
 602
 603         return dimms_found;
 604 }
 605
 606 /*************************************************************************
 607  * init SDRAM controller with fixed value
 608  * the initialization values are for 2x MICRON DDR2
 609  * PN: MT18HTF6472DY-53EB2
 610  * 512MB, DDR2, 533, CL4, ECC, REG
 611  ************************************************************************/
 612 static long int fixed_sdram(void)
 613 {
 614         long int yucca_dimms = 0;
 615
 616         yucca_dimms = yucca_probe_for_dimms();
 617
 618         /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT  */
 619         mtdcr( 0x10, 0x00000021 );
 620         mtdcr( 0x11, 0x84000000 );
 621
 622         /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2      */
 623         mtdcr( 0x10, 0x00000020 );
 624         mtdcr( 0x11, 0x2D122000 );
 625
 626         /* SET MCIF0_CODT   Die Termination On  */
 627         mtdcr( 0x10, 0x00000026 );
 628         if (yucca_dimms == 2)
 629                 mtdcr( 0x11, 0x2A800021 );
 630         else if (yucca_dimms == 1)
 631                 mtdcr( 0x11, 0x02800021 );
 632
 633         /* On-Die Termination for Bank 0        */
 634         mtdcr( 0x10, 0x00000022 );
 635         if (yucca_dimms == 2)
 636                 mtdcr( 0x11, 0x18000000 );
 637         else if (yucca_dimms == 1)
 638                 mtdcr( 0x11, 0x06000000 );
 639
 640         /*      On-Die Termination for Bank 1   */
 641         mtdcr( 0x10, 0x00000023 );
 642         if (yucca_dimms == 2)
 643                 mtdcr( 0x11, 0x18000000 );
 644         else if (yucca_dimms == 1)
 645                 mtdcr( 0x11, 0x01800000 );
 646
 647         /*      On-Die Termination for Bank 2   */
 648         mtdcr( 0x10, 0x00000024 );
 649         if (yucca_dimms == 2)
 650                 mtdcr( 0x11, 0x01800000 );
 651         else if (yucca_dimms == 1)
 652                 mtdcr( 0x11, 0x00000000 );
 653
 654         /*      On-Die Termination for Bank 3   */
 655         mtdcr( 0x10, 0x00000025 );
 656         if (yucca_dimms == 2)
 657                 mtdcr( 0x11, 0x01800000 );
 658         else if (yucca_dimms == 1)
 659                 mtdcr( 0x11, 0x00000000 );
 660
 661         /* Refresh Time register (0x30) Refresh every 7.8125uS  */
 662         mtdcr( 0x10, 0x00000030 );
 663         mtdcr( 0x11, 0x08200000 );
 664
 665         /* SET MCIF0_MMODE       CL 4   */
 666         mtdcr( 0x10, 0x00000088 );
 667         mtdcr( 0x11, 0x00000642 );
 668
 669         /* MCIF0_MEMODE */
 670         mtdcr( 0x10, 0x00000089 );
 671         mtdcr( 0x11, 0x00000004 );
 672
 673         /*SET MCIF0_MB0CF       */
 674         mtdcr( 0x10, 0x00000040 );
 675         mtdcr( 0x11, 0x00000201 );
 676
 677         /* SET MCIF0_MB1CF      */
 678         mtdcr( 0x10, 0x00000044 );
 679         mtdcr( 0x11, 0x00000201 );
 680
 681         /* SET MCIF0_MB2CF      */
 682         mtdcr( 0x10, 0x00000048 );
 683         if (yucca_dimms == 2)
 684                 mtdcr( 0x11, 0x00000201 );
 685         else if (yucca_dimms == 1)
 686                 mtdcr( 0x11, 0x00000000 );
 687
 688         /* SET MCIF0_MB3CF      */
 689         mtdcr( 0x10, 0x0000004c );
 690         if (yucca_dimms == 2)
 691                 mtdcr( 0x11, 0x00000201 );
 692         else if (yucca_dimms == 1)
 693                 mtdcr( 0x11, 0x00000000 );
 694
 695         /* SET MCIF0_INITPLR0  # NOP            */
 696         mtdcr( 0x10, 0x00000050 );
 697         mtdcr( 0x11, 0xB5380000 );
 698
 699         /* SET MCIF0_INITPLR1  # PRE            */
 700         mtdcr( 0x10, 0x00000051 );
 701         mtdcr( 0x11, 0x82100400 );
 702
 703         /* SET MCIF0_INITPLR2  # EMR2           */
 704         mtdcr( 0x10, 0x00000052 );
 705         mtdcr( 0x11, 0x80820000 );
 706
 707         /* SET MCIF0_INITPLR3  # EMR3           */
 708         mtdcr( 0x10, 0x00000053 );
 709         mtdcr( 0x11, 0x80830000 );
 710
 711         /* SET MCIF0_INITPLR4  # EMR DLL ENABLE */
 712         mtdcr( 0x10, 0x00000054 );
 713         mtdcr( 0x11, 0x80810000 );
 714
 715         /* SET MCIF0_INITPLR5  # MR DLL RESET   */
 716         mtdcr( 0x10, 0x00000055 );
 717         mtdcr( 0x11, 0x80800542 );
 718
 719         /* SET MCIF0_INITPLR6  # PRE            */
 720         mtdcr( 0x10, 0x00000056 );
 721         mtdcr( 0x11, 0x82100400 );
 722
 723         /* SET MCIF0_INITPLR7  # Refresh        */
 724         mtdcr( 0x10, 0x00000057 );
 725         mtdcr( 0x11, 0x8A080000 );
 726
 727         /* SET MCIF0_INITPLR8  # Refresh        */
 728         mtdcr( 0x10, 0x00000058 );
 729         mtdcr( 0x11, 0x8A080000 );
 730
 731         /* SET MCIF0_INITPLR9  # Refresh        */
 732         mtdcr( 0x10, 0x00000059 );
 733         mtdcr( 0x11, 0x8A080000 );
 734
 735         /* SET MCIF0_INITPLR10 # Refresh        */
 736         mtdcr( 0x10, 0x0000005A );
 737         mtdcr( 0x11, 0x8A080000 );
 738
 739         /* SET MCIF0_INITPLR11 # MR             */
 740         mtdcr( 0x10, 0x0000005B );
 741         mtdcr( 0x11, 0x80800442 );
 742
 743         /* SET MCIF0_INITPLR12 # EMR OCD Default*/
 744         mtdcr( 0x10, 0x0000005C );
 745         mtdcr( 0x11, 0x80810380 );
 746
 747         /* SET MCIF0_INITPLR13 # EMR OCD Exit   */
 748         mtdcr( 0x10, 0x0000005D );
 749         mtdcr( 0x11, 0x80810000 );
 750
 751         /* 0x80: Adv Addr clock by 180 deg      */
 752         mtdcr( 0x10, 0x00000080 );
 753         mtdcr( 0x11, 0x80000000 );
 754
 755         /* 0x21: Exit self refresh, set DC_EN   */
 756         mtdcr( 0x10, 0x00000021 );
 757         mtdcr( 0x11, 0x28000000 );
 758
 759         /* 0x81: Write DQS Adv 90 + Fractional DQS Delay        */
 760         mtdcr( 0x10, 0x00000081 );
 761         mtdcr( 0x11, 0x80000800 );
 762
 763         /* MCIF0_SDTR1  */
 764         mtdcr( 0x10, 0x00000085 );
 765         mtdcr( 0x11, 0x80201000 );
 766
 767         /* MCIF0_SDTR2  */
 768         mtdcr( 0x10, 0x00000086 );
 769         mtdcr( 0x11, 0x42103242 );
 770
 771         /* MCIF0_SDTR3  */
 772         mtdcr( 0x10, 0x00000087 );
 773         mtdcr( 0x11, 0x0C100D14 );
 774
 775         /* SET MQ0_B0BAS  base addr 00000000 / 256MB    */
 776         mtdcr( 0x40, 0x0000F800 );
 777
 778         /* SET MQ0_B1BAS  base addr 10000000 / 256MB    */
 779         mtdcr( 0x41, 0x0400F800 );
 780
 781         /* SET MQ0_B2BAS  base addr 20000000 / 256MB    */
 782         if (yucca_dimms == 2)
 783                 mtdcr( 0x42, 0x0800F800 );
 784         else if (yucca_dimms == 1)
 785                 mtdcr( 0x42, 0x00000000 );
 786
 787         /* SET MQ0_B3BAS  base addr 30000000 / 256MB    */
 788         if (yucca_dimms == 2)
 789                 mtdcr( 0x43, 0x0C00F800 );
 790         else if (yucca_dimms == 1)
 791                 mtdcr( 0x43, 0x00000000 );
 792
 793         /* SDRAM_RQDC   */
 794         mtdcr( 0x10, 0x00000070 );
 795         mtdcr( 0x11, 0x8000003F );
 796
 797         /* SDRAM_RDCC   */
 798         mtdcr( 0x10, 0x00000078 );
 799         mtdcr( 0x11, 0x80000000 );
 800
 801         /* SDRAM_RFDC   */
 802         mtdcr( 0x10, 0x00000074 );
 803         mtdcr( 0x11, 0x00000220 );
 804
 805         return (yucca_dimms * 512) << 20;
 806 }
 807
 808 long int initdram (int board_type)
 809 {
 810         long dram_size = 0;
 811
 812         dram_size = fixed_sdram();
 813
 814         return dram_size;
 815 }
 816
 817 #if defined(CFG_DRAM_TEST)
 818 int testdram (void)
 819 {
 820         uint *pstart = (uint *) 0x00000000;
 821         uint *pend = (uint *) 0x08000000;
 822         uint *p;
 823
 824         for (p = pstart; p < pend; p++)
 825                 *p = 0xaaaaaaaa;
 826
 827         for (p = pstart; p < pend; p++) {
 828                 if (*p != 0xaaaaaaaa) {
 829                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 830                         return 1;
 831                 }
 832         }
 833
 834         for (p = pstart; p < pend; p++)
 835                 *p = 0x55555555;
 836
 837         for (p = pstart; p < pend; p++) {
 838                 if (*p != 0x55555555) {
 839                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 840                         return 1;
 841                 }
 842         }
 843         return 0;
 844 }
 845 #endif
 846
 847 /*************************************************************************
 848  *  pci_pre_init
 849  *
 850  *  This routine is called just prior to registering the hose and gives
 851  *  the board the opportunity to check things. Returning a value of zero
 852  *  indicates that things are bad & PCI initialization should be aborted.
 853  *
 854  *      Different boards may wish to customize the pci controller structure
 855  *      (add regions, override default access routines, etc) or perform
 856  *      certain pre-initialization actions.
 857  *
 858  ************************************************************************/
 859 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 860 int pci_pre_init(struct pci_controller * hose )
 861 {
 862         unsigned long strap;
 863
 864         /*-------------------------------------------------------------------+
 865          *      The yucca board is always configured as the host & requires the
 866          *      PCI arbiter to be enabled.
 867          *-------------------------------------------------------------------*/
 868         mfsdr(sdr_sdstp1, strap);
 869         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
 870                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 871                 return 0;
 872         }
 873
 874         return 1;
 875 }
 876 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 877
 878 /*************************************************************************
 879  *  pci_target_init
 880  *
 881  *      The bootstrap configuration provides default settings for the pci
 882  *      inbound map (PIM). But the bootstrap config choices are limited and
 883  *      may not be sufficient for a given board.
 884  *
 885  ************************************************************************/
 886 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 887 void pci_target_init(struct pci_controller * hose )
 888 {
 889         DECLARE_GLOBAL_DATA_PTR;
 890
 891         /*-------------------------------------------------------------------+
 892          * Disable everything
 893          *-------------------------------------------------------------------*/
 894         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 895         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 896         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 897         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 898
 899         /*-------------------------------------------------------------------+
 900          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 901          * strapping options to not support sizes such as 128/256 MB.
 902          *-------------------------------------------------------------------*/
 903         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 904         out32r( PCIX0_PIM0LAH, 0 );
 905         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 906         out32r( PCIX0_BAR0, 0 );
 907
 908         /*-------------------------------------------------------------------+
 909          * Program the board's subsystem id/vendor id
 910          *-------------------------------------------------------------------*/
 911         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 912         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 913
 914         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 915 }
 916 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 917
 918 #if defined(CONFIG_PCI)
 919 /*************************************************************************
 920  *  is_pci_host
 921  *
 922  *      This routine is called to determine if a pci scan should be
 923  *      performed. With various hardware environments (especially cPCI and
 924  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 925  *      bit in the strap register, or generic host/adapter assumptions.
 926  *
 927  *      Rather than hard-code a bad assumption in the general 440 code, the
 928  *      440 pci code requires the board to decide at runtime.
 929  *
 930  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 931  *
 932  *
 933  ************************************************************************/
 934 int is_pci_host(struct pci_controller *hose)
 935 {
 936         /* The yucca board is always configured as host. */
 937         return 1;
 938 }
 939
 940
 941 int yucca_pcie_card_present(int port)
 942 {
 943         u16 reg;
 944
 945         reg = in_be16((u16 *)FPGA_REG1C);
 946         switch(port) {
 947         case 0:
 948                 return !(reg & FPGA_REG1C_PE0_PRSNT);
 949         case 1:
 950                 return !(reg & FPGA_REG1C_PE1_PRSNT);
 951         case 2:
 952                 return !(reg & FPGA_REG1C_PE2_PRSNT);
 953         default:
 954                 return 0;
 955         }
 956 }
 957
 958 /*
 959  * For the given slot, set rootpoint mode, send power to the slot,
 960  * turn on the green LED and turn off the yellow LED, enable the clock
 961  * and turn off reset.
 962  */
 963 void yucca_setup_pcie_fpga_rootpoint(int port)
 964 {
 965         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 966
 967         switch(port) {
 968         case 0:
 969                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 970                 endpoint    = 0;
 971                 power       = FPGA_REG1A_PE0_PWRON;
 972                 green_led   = FPGA_REG1A_PE0_GLED;
 973                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 974                 yellow_led  = FPGA_REG1A_PE0_YLED;
 975                 reset_off   = FPGA_REG1C_PE0_PERST;
 976                 break;
 977         case 1:
 978                 rootpoint   = 0;
 979                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 980                 power       = FPGA_REG1A_PE1_PWRON;
 981                 green_led   = FPGA_REG1A_PE1_GLED;
 982                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 983                 yellow_led  = FPGA_REG1A_PE1_YLED;
 984                 reset_off   = FPGA_REG1C_PE1_PERST;
 985                 break;
 986         case 2:
 987                 rootpoint   = 0;
 988                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 989                 power       = FPGA_REG1A_PE2_PWRON;
 990                 green_led   = FPGA_REG1A_PE2_GLED;
 991                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 992                 yellow_led  = FPGA_REG1A_PE2_YLED;
 993                 reset_off   = FPGA_REG1C_PE2_PERST;
 994                 break;
 995
 996         default:
 997                 return;
 998         }
 999
1000         out_be16((u16 *)FPGA_REG1A,
1001                  ~(power | clock | green_led) &
1002                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
1003
1004         out_be16((u16 *)FPGA_REG1C,
1005                  ~(endpoint | reset_off) &
1006                  (rootpoint | in_be16((u16 *)FPGA_REG1C)));
1007         /*
1008          * Leave device in reset for a while after powering on the
1009          * slot to give it a chance to initialize.
1010          */
1011         udelay(250 * 1000);
1012
1013         out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
1014 }
1015
1016
1017 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
1018
1019 void pcie_setup_hoses(void)
1020 {
1021         struct pci_controller *hose;
1022         int i, bus;
1023
1024         /*
1025          * assume we're called after the PCIX hose is initialized, which takes
1026          * bus ID 0 and therefore start numbering PCIe's from 1.
1027          */
1028         bus = 1;
1029         for (i = 0; i <= 2; i++) {
1030                 /* Check for yucca card presence */
1031                 if (!yucca_pcie_card_present(i))
1032                         continue;
1033
1034                 yucca_setup_pcie_fpga_rootpoint(i);
1035
1036                 if (ppc440spe_init_pcie_rootport(i)) {
1037                         printf("PCIE%d: initialization failed\n", i);
1038                         continue;
1039                 }
1040
1041                 hose = &pcie_hose[i];
1042                 hose->first_busno = bus;
1043                 hose->last_busno  = bus;
1044                 bus++;
1045
1046                 /* setup mem resource */
1047                 pci_set_region(hose->regions + 0,
1048                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
1049                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
1050                         CFG_PCIE_MEMSIZE,
1051                         PCI_REGION_MEM
1052                         );
1053                 hose->region_count = 1;
1054                 pci_register_hose(hose);
1055
1056                 ppc440spe_setup_pcie(hose, i);
1057                 hose->last_busno = pci_hose_scan(hose);
1058         }
1059 }
1060 #endif  /* defined(CONFIG_PCI) */
1061
1062 int misc_init_f (void)
1063 {
1064         uint reg;
1065 #if defined(CONFIG_STRESS)
1066         uint i ;
1067         uint disp;
1068 #endif
1069
1070         out16(FPGA_REG10, (in16(FPGA_REG10) &
1071                         ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
1072                                 FPGA_REG10_10MHZ_ENABLE |
1073                                 FPGA_REG10_100MHZ_ENABLE |
1074                                 FPGA_REG10_GIGABIT_ENABLE |
1075                                 FPGA_REG10_FULL_DUPLEX );
1076
1077         udelay(10000);  /* wait 10ms */
1078
1079         out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
1080
1081         /* minimal init for PCIe */
1082         /* pci express 0 Endpoint Mode */
1083         mfsdr(SDR0_PE0DLPSET, reg);
1084         reg &= (~0x00400000);
1085         mtsdr(SDR0_PE0DLPSET, reg);
1086         /* pci express 1 Rootpoint  Mode */
1087         mfsdr(SDR0_PE1DLPSET, reg);
1088         reg |= 0x00400000;
1089         mtsdr(SDR0_PE1DLPSET, reg);
1090         /* pci express 2 Rootpoint  Mode */
1091         mfsdr(SDR0_PE2DLPSET, reg);
1092         reg |= 0x00400000;
1093         mtsdr(SDR0_PE2DLPSET, reg);
1094
1095         out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
1096                                 ~FPGA_REG1C_PE0_ROOTPOINT &
1097                                 ~FPGA_REG1C_PE1_ENDPOINT  &
1098                                 ~FPGA_REG1C_PE2_ENDPOINT));
1099
1100 #if defined(CONFIG_STRESS)
1101         /*
1102          * all this setting done by linux only needed by stress an charac. test
1103          * procedure
1104          * PCIe 1 Rootpoint PCIe2 Endpoint
1105          * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1106          * Power Level
1107          */
1108         for (i = 0, disp = 0; i < 8; i++, disp += 3) {
1109                 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
1110                 reg |= 0x33000000;
1111                 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
1112         }
1113
1114         /*
1115          * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1116          * Power Level
1117          */
1118         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
1119                 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
1120                 reg |= 0x33000000;
1121                 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
1122         }
1123
1124         /*
1125          * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1126          * Power Level
1127          */
1128         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
1129                 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1130                 reg |= 0x33000000;
1131                 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1132         }
1133
1134         reg = 0x21242222;
1135         mtsdr(SDR0_PE2UTLSET1, reg);
1136         reg = 0x11000000;
1137         mtsdr(SDR0_PE2UTLSET2, reg);
1138         /* pci express 1 Endpoint  Mode */
1139         reg = 0x00004000;
1140         mtsdr(SDR0_PE2DLPSET, reg);
1141
1142         mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
1143 #endif
1144         return 0;
1145 }
1146
1147 void fpga_init(void)
1148 {
1149         /*
1150          * by default sdram access is disabled by fpga
1151          */
1152         out16(FPGA_REG10, (in16 (FPGA_REG10) |
1153                                 FPGA_REG10_SDRAM_ENABLE |
1154                                 FPGA_REG10_ENABLE_DISPLAY ));
1155
1156         return;
1157 }
1158
1159 #ifdef CONFIG_POST
1160 /*
1161  * Returns 1 if keys pressed to start the power-on long-running tests
1162  * Called from board_init_f().
1163  */
1164 int post_hotkeys_pressed(void)
1165 {
1166         return (ctrlc());
1167 }
1168 #endif
1169
1170 /*---------------------------------------------------------------------------+
1171  | onboard_pci_arbiter_selected => from EPLD
1172  +---------------------------------------------------------------------------*/
1173 int onboard_pci_arbiter_selected(int core_pci)
1174 {
1175 #if 0
1176         unsigned long onboard_pci_arbiter_sel;
1177
1178         onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1179
1180         if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1181                 return (BOARD_OPTION_SELECTED);
1182         else
1183 #endif
1184         return (BOARD_OPTION_NOT_SELECTED);
1185 }
1186
1187 /*---------------------------------------------------------------------------+
1188  | ppcMfcpr.
1189  +---------------------------------------------------------------------------*/
1190 unsigned long ppcMfcpr(unsigned long cpr_reg)
1191 {
1192         unsigned long msr;
1193         unsigned long cpr_cfgaddr_temp;
1194         unsigned long cpr_value;
1195
1196         msr = (mfmsr () & ~(MSR_EE));
1197         cpr_cfgaddr_temp =  mfdcr(CPR0_CFGADDR);
1198         mtdcr(CPR0_CFGADDR, cpr_reg);
1199         cpr_value =  mfdcr(CPR0_CFGDATA);
1200         mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
1201         mtmsr(msr);
1202
1203         return (cpr_value);
1204 }
1205
1206 /*----------------------------------------------------------------------------+
1207 | Indirect Access of the System DCR's (SDR)
1208 | ppcMfsdr
1209 +----------------------------------------------------------------------------*/
1210 unsigned long ppcMfsdr(unsigned long sdr_reg)
1211 {
1212         unsigned long msr;
1213         unsigned long sdr_cfgaddr_temp;
1214         unsigned long sdr_value;
1215
1216         msr = (mfmsr () & ~(MSR_EE));
1217         sdr_cfgaddr_temp =  mfdcr(SDR0_CFGADDR);
1218         mtdcr(SDR0_CFGADDR, sdr_reg);
1219         sdr_value =  mfdcr(SDR0_CFGDATA);
1220         mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
1221         mtmsr(msr);
1222
1223         return (sdr_value);
1224 }