3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Port to AMCC-440SPE Evaluation Board SOP - April 2005
25 * PCIe supporting routines derived from Linux 440SPe PCIe driver.
30 #include <asm/processor.h>
32 #include <asm-ppc/io.h>
36 void fpga_init (void);
38 void get_sys_info(PPC440_SYS_INFO *board_cfg );
39 int compare_to_true(char *str );
40 char *remove_l_w_space(char *in_str );
41 char *remove_t_w_space(char *in_str );
42 int get_console_port(void);
43 unsigned long ppcMfcpr(unsigned long cpr_reg);
44 unsigned long ppcMfsdr(unsigned long sdr_reg);
46 int ppc440spe_init_pcie_rootport(int port);
47 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
51 #define DEBUGF(fmt,args...) printf(fmt ,##args)
53 #define DEBUGF(fmt,args...)
59 int board_early_init_f (void)
61 /*----------------------------------------------------------------------------+
63 +----------------------------------------------------------------------------*/
64 #define BOOT_FROM_SMALL_FLASH 0x00
65 #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
66 #define BOOT_FROM_PCI 0x02
67 #define BOOT_DEVICE_UNKNOWN 0x03
69 /*----------------------------------------------------------------------------+
70 | EBC Devices Characteristics
71 | Peripheral Bank Access Parameters - EBC_BxAP
72 | Peripheral Bank Configuration Register - EBC_BxCR
73 +----------------------------------------------------------------------------*/
76 * Small Flash and FRAM
78 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
79 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
80 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
82 #define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
83 EBC_BXAP_TWT_ENCODE(7) | \
84 EBC_BXAP_BCE_DISABLE | \
85 EBC_BXAP_BCT_2TRANS | \
86 EBC_BXAP_CSN_ENCODE(0) | \
87 EBC_BXAP_OEN_ENCODE(0) | \
88 EBC_BXAP_WBN_ENCODE(0) | \
89 EBC_BXAP_WBF_ENCODE(0) | \
90 EBC_BXAP_TH_ENCODE(0) | \
91 EBC_BXAP_RE_DISABLED | \
92 EBC_BXAP_SOR_DELAYED | \
93 EBC_BXAP_BEM_WRITEONLY | \
96 #define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
101 #define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
107 * Large Flash and SRAM
109 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
110 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
111 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
113 #define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
114 EBC_BXAP_TWT_ENCODE(7) | \
115 EBC_BXAP_BCE_DISABLE | \
116 EBC_BXAP_BCT_2TRANS | \
117 EBC_BXAP_CSN_ENCODE(0) | \
118 EBC_BXAP_OEN_ENCODE(0) | \
119 EBC_BXAP_WBN_ENCODE(0) | \
120 EBC_BXAP_WBF_ENCODE(0) | \
121 EBC_BXAP_TH_ENCODE(0) | \
122 EBC_BXAP_RE_DISABLED | \
123 EBC_BXAP_SOR_DELAYED | \
124 EBC_BXAP_BEM_WRITEONLY | \
125 EBC_BXAP_PEN_DISABLED
127 #define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
132 #define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
140 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
141 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
143 #define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
144 EBC_BXAP_TWT_ENCODE(11) | \
145 EBC_BXAP_BCE_DISABLE | \
146 EBC_BXAP_BCT_2TRANS | \
147 EBC_BXAP_CSN_ENCODE(10) | \
148 EBC_BXAP_OEN_ENCODE(1) | \
149 EBC_BXAP_WBN_ENCODE(1) | \
150 EBC_BXAP_WBF_ENCODE(1) | \
151 EBC_BXAP_TH_ENCODE(1) | \
152 EBC_BXAP_RE_DISABLED | \
153 EBC_BXAP_SOR_DELAYED | \
155 EBC_BXAP_PEN_DISABLED
157 #define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
164 * Define Variables for EBC initialization depending on BOOTSTRAP option
166 unsigned long sdr0_pinstp, sdr0_sdstp1 ;
167 unsigned long bootstrap_settings, ebc_data_width, boot_selection;
168 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
170 /*-------------------------------------------------------------------+
171 | Initialize EBC CONFIG -
172 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
174 | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
176 +-------------------------------------------------------------------*/
177 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
179 EBC_CFG_RTC_16PERCLK |
180 EBC_CFG_ATC_PREVIOUS |
181 EBC_CFG_DTC_PREVIOUS |
182 EBC_CFG_CTC_PREVIOUS |
183 EBC_CFG_OEO_PREVIOUS |
184 EBC_CFG_EMC_DEFAULT |
185 EBC_CFG_PME_DISABLE |
188 /*-------------------------------------------------------------------+
190 | PART 1 : Initialize EBC Bank 1
191 | ==============================
192 | Bank1 is always associated to the EPLD.
193 | It has to be initialized prior to other banks settings computation
194 | since some board registers values may be needed to determine the
197 +-------------------------------------------------------------------*/
198 mtebc(pb1ap, EBC_BXAP_FPGA);
199 mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
201 /*-------------------------------------------------------------------+
203 | PART 2 : Determine which boot device was selected
204 | =================================================
206 | Read Pin Strap Register in PPC440SPe
207 | Result can either be :
208 | - Boot strap = boot from EBC 8bits => Small Flash
209 | - Boot strap = boot from PCI
211 | In case of boot from IIC, read Serial Device Strap Register1
213 | Result can either be :
214 | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
215 | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
218 +-------------------------------------------------------------------*/
219 /* Read Pin Strap Register in PPC440SP */
220 sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
221 bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
223 switch (bootstrap_settings) {
224 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
227 * Boot from EBC - 8 bits , Small Flash
229 computed_boot_device = BOOT_FROM_SMALL_FLASH;
231 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
233 * Strappping Option B
236 computed_boot_device = BOOT_FROM_PCI;
238 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
239 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
241 * Strapping Option C or D
242 * Boot Settings in IIC EEprom address 0x50 or 0x54
243 * Read Serial Device Strap Register1 in PPC440SPe
245 sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
246 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
247 ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
249 switch (boot_selection) {
250 case SDR0_SDSTP1_ERPN_EBC:
251 switch (ebc_data_width) {
252 case SDR0_SDSTP1_EBCW_16_BITS:
253 computed_boot_device =
254 BOOT_FROM_LARGE_FLASH_OR_SRAM;
256 case SDR0_SDSTP1_EBCW_8_BITS :
257 computed_boot_device = BOOT_FROM_SMALL_FLASH;
262 case SDR0_SDSTP1_ERPN_PCI:
263 computed_boot_device = BOOT_FROM_PCI;
266 /* should not occure */
267 computed_boot_device = BOOT_DEVICE_UNKNOWN;
272 computed_boot_device = BOOT_DEVICE_UNKNOWN;
276 /*-------------------------------------------------------------------+
278 | PART 3 : Compute EBC settings depending on selected boot device
279 | ====== ======================================================
281 | Resulting EBC init will be among following configurations :
283 | - Boot from EBC 8bits => boot from Small Flash selected
284 | EBC-CS0 = Small Flash
285 | EBC-CS2 = Large Flash and SRAM
287 | - Boot from EBC 16bits => boot from Large Flash or SRAM
288 | EBC-CS0 = Large Flash or SRAM
289 | EBC-CS2 = Small Flash
292 | EBC-CS0 = not initialized to avoid address contention
293 | EBC-CS2 = same as boot from Small Flash selected
295 +-------------------------------------------------------------------*/
296 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
297 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
299 switch (computed_boot_device) {
300 /*-------------------------------------------------------------------*/
302 /*-------------------------------------------------------------------*/
304 * By Default CS2 is affected to LARGE Flash
305 * do not initialize SMALL FLASH to avoid address contention
308 ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
309 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
312 /*-------------------------------------------------------------------*/
313 case BOOT_FROM_SMALL_FLASH:
314 /*-------------------------------------------------------------------*/
315 ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
316 ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
319 * Large Flash or SRAM
321 /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
322 ebc0_cs2_bxap_value = 0x048ff240;
323 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
326 /*-------------------------------------------------------------------*/
327 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
328 /*-------------------------------------------------------------------*/
329 ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
330 ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
333 ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
334 ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
337 /*-------------------------------------------------------------------*/
339 /*-------------------------------------------------------------------*/
340 /* BOOT_DEVICE_UNKNOWN */
344 mtebc(pb0ap, ebc0_cs0_bxap_value);
345 mtebc(pb0cr, ebc0_cs0_bxcr_value);
346 mtebc(pb2ap, ebc0_cs2_bxap_value);
347 mtebc(pb2cr, ebc0_cs2_bxcr_value);
349 /*--------------------------------------------------------------------+
350 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
351 +--------------------------------------------------------------------+
352 +---------------------------------------------------------------------+
353 |Interrupt| Source | Pol. | Sensi.| Crit. |
354 +---------+-----------------------------------+-------+-------+-------+
355 | IRQ 00 | UART0 | High | Level | Non |
356 | IRQ 01 | UART1 | High | Level | Non |
357 | IRQ 02 | IIC0 | High | Level | Non |
358 | IRQ 03 | IIC1 | High | Level | Non |
359 | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
360 | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
361 | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
362 | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
363 | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
364 | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
365 | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
366 | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
367 | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
368 | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
369 | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
370 | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
371 | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
372 | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
373 | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
374 | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
375 | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
376 | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
377 | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
378 | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
379 | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
380 | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
381 | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
382 | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
383 | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
384 | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
385 | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
386 | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
387 |----------------------------------------------------------------------
388 | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
389 | IRQ 33 | MAL Serr | High | Level | Non |
390 | IRQ 34 | MAL Txde | High | Level | Non |
391 | IRQ 35 | MAL Rxde | High | Level | Non |
392 | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
393 | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
394 | IRQ 38 | MAL TX EOB | High | Level | Non |
395 | IRQ 39 | MAL RX EOB | High | Level | Non |
396 | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
397 | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
398 | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
399 | IRQ 43 | L2 Cache | Risin | Edge | Non |
400 | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
401 | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
402 | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
403 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
404 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
405 | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
406 | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
407 | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
408 | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
409 | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
410 | IRQ 54 | DMA Error | High | Level | Non |
411 | IRQ 55 | DMA I2O Error | High | Level | Non |
412 | IRQ 56 | Serial ROM | High | Level | Non |
413 | IRQ 57 | PCIX0 Error | High | Edge | Non |
414 | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
415 | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
416 | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
417 | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
418 | IRQ 62 | Reserved | High | Level | Non |
419 | IRQ 63 | XOR | High | Level | Non |
420 |----------------------------------------------------------------------
421 | IRQ 64 | PE0 AL | High | Level | Non |
422 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
423 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
424 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
425 | IRQ 68 | PE0 TCR | High | Level | Non |
426 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
427 | IRQ 70 | PE0 DCR Error | High | Level | Non |
428 | IRQ 71 | Reserved | N/A | N/A | Non |
429 | IRQ 72 | PE1 AL | High | Level | Non |
430 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
431 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
432 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
433 | IRQ 76 | PE1 TCR | High | Level | Non |
434 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
435 | IRQ 78 | PE1 DCR Error | High | Level | Non |
436 | IRQ 79 | Reserved | N/A | N/A | Non |
437 | IRQ 80 | PE2 AL | High | Level | Non |
438 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
439 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
440 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
441 | IRQ 84 | PE2 TCR | High | Level | Non |
442 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
443 | IRQ 86 | PE2 DCR Error | High | Level | Non |
444 | IRQ 87 | Reserved | N/A | N/A | Non |
445 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
446 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
447 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
448 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
449 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
450 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
451 | IRQ 94 | Reserved | N/A | N/A | Non |
452 | IRQ 95 | Reserved | N/A | N/A | Non |
453 |---------------------------------------------------------------------
454 | IRQ 96 | PE0 INTA | High | Level | Non |
455 | IRQ 97 | PE0 INTB | High | Level | Non |
456 | IRQ 98 | PE0 INTC | High | Level | Non |
457 | IRQ 99 | PE0 INTD | High | Level | Non |
458 | IRQ 100 | PE1 INTA | High | Level | Non |
459 | IRQ 101 | PE1 INTB | High | Level | Non |
460 | IRQ 102 | PE1 INTC | High | Level | Non |
461 | IRQ 103 | PE1 INTD | High | Level | Non |
462 | IRQ 104 | PE2 INTA | High | Level | Non |
463 | IRQ 105 | PE2 INTB | High | Level | Non |
464 | IRQ 106 | PE2 INTC | High | Level | Non |
465 | IRQ 107 | PE2 INTD | Risin | Edge | Non |
466 | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
467 | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
468 | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
469 | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
470 | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
471 | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
472 | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
473 | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
474 | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
475 | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
476 | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
477 | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
478 | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
479 | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
480 | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
481 | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
482 | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
483 | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
484 | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
485 | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
486 +---------+-----------------------------------+-------+-------+------*/
487 /*--------------------------------------------------------------------+
488 | Put UICs in PowerPC440SPemode.
489 | Initialise UIC registers. Clear all interrupts. Disable all
491 | Set critical interrupt values. Set interrupt polarities. Set
492 | interrupt trigger levels. Make bit 0 High priority. Clear all
494 +-------------------------------------------------------------------*/
495 mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
496 mtdcr (uic3er, 0x00000000); /* disable all interrupts */
497 mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
499 mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
500 mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
501 mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
503 mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
504 mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
506 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
507 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
508 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
510 mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
511 mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
512 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
514 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
515 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
517 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
518 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
519 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
521 mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
522 mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
523 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
525 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
526 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
528 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
529 mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
530 * cascade to be checked */
531 mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
533 mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
534 mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
535 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
537 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
538 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
540 /* SDR0_MFR should be part of Ethernet init */
541 mfsdr (sdr_mfr, mfr);
542 mfr &= ~SDR0_MFR_ECS_MASK;
543 /*mtsdr(sdr_mfr, mfr);*/
549 int checkboard (void)
551 char *s = getenv("serial#");
553 printf("Board: Yucca - AMCC 440SPe Evaluation Board");
563 static long int yucca_probe_for_dimms(void)
565 int dimm_installed[MAXDIMMS];
566 int dimm_num, result;
568 uchar dimm_addr = IIC0_DIMM0_ADDR;
569 uchar dimm_spd_data[MAX_SPD_BYTES];
571 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
572 /* check if there is a chip at the dimm address */
575 dimm_addr = IIC0_DIMM0_ADDR;
578 dimm_addr = IIC0_DIMM1_ADDR;
582 result = i2c_probe(dimm_addr);
584 memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
586 /* read first byte of SPD data, if there is any data */
587 result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
590 result = dimm_spd_data[0];
591 result = result > MAX_SPD_BYTES ?
592 MAX_SPD_BYTES : result;
593 result = i2c_read(dimm_addr, 0, 1,
594 dimm_spd_data, result);
599 (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
600 dimm_installed[dimm_num] = TRUE;
602 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
604 dimm_installed[dimm_num] = FALSE;
605 debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
609 if (dimms_found == 0) {
610 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
614 if (dimm_installed[0] != TRUE) {
615 printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
616 printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
623 /*************************************************************************
624 * init SDRAM controller with fixed value
625 * the initialization values are for 2x MICRON DDR2
626 * PN: MT18HTF6472DY-53EB2
627 * 512MB, DDR2, 533, CL4, ECC, REG
628 ************************************************************************/
629 static long int fixed_sdram(void)
631 long int yucca_dimms = 0;
633 yucca_dimms = yucca_probe_for_dimms();
635 /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */
636 mtdcr( 0x10, 0x00000021 );
637 mtdcr( 0x11, 0x84000000 );
639 /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */
640 mtdcr( 0x10, 0x00000020 );
641 mtdcr( 0x11, 0x2D122000 );
643 /* SET MCIF0_CODT Die Termination On */
644 mtdcr( 0x10, 0x00000026 );
645 if (yucca_dimms == 2)
646 mtdcr( 0x11, 0x2A800021 );
647 else if (yucca_dimms == 1)
648 mtdcr( 0x11, 0x02800021 );
650 /* On-Die Termination for Bank 0 */
651 mtdcr( 0x10, 0x00000022 );
652 if (yucca_dimms == 2)
653 mtdcr( 0x11, 0x18000000 );
654 else if (yucca_dimms == 1)
655 mtdcr( 0x11, 0x06000000 );
657 /* On-Die Termination for Bank 1 */
658 mtdcr( 0x10, 0x00000023 );
659 if (yucca_dimms == 2)
660 mtdcr( 0x11, 0x18000000 );
661 else if (yucca_dimms == 1)
662 mtdcr( 0x11, 0x01800000 );
664 /* On-Die Termination for Bank 2 */
665 mtdcr( 0x10, 0x00000024 );
666 if (yucca_dimms == 2)
667 mtdcr( 0x11, 0x01800000 );
668 else if (yucca_dimms == 1)
669 mtdcr( 0x11, 0x00000000 );
671 /* On-Die Termination for Bank 3 */
672 mtdcr( 0x10, 0x00000025 );
673 if (yucca_dimms == 2)
674 mtdcr( 0x11, 0x01800000 );
675 else if (yucca_dimms == 1)
676 mtdcr( 0x11, 0x00000000 );
678 /* Refresh Time register (0x30) Refresh every 7.8125uS */
679 mtdcr( 0x10, 0x00000030 );
680 mtdcr( 0x11, 0x08200000 );
682 /* SET MCIF0_MMODE CL 4 */
683 mtdcr( 0x10, 0x00000088 );
684 mtdcr( 0x11, 0x00000642 );
687 mtdcr( 0x10, 0x00000089 );
688 mtdcr( 0x11, 0x00000004 );
691 mtdcr( 0x10, 0x00000040 );
692 mtdcr( 0x11, 0x00000201 );
694 /* SET MCIF0_MB1CF */
695 mtdcr( 0x10, 0x00000044 );
696 mtdcr( 0x11, 0x00000201 );
698 /* SET MCIF0_MB2CF */
699 mtdcr( 0x10, 0x00000048 );
700 if (yucca_dimms == 2)
701 mtdcr( 0x11, 0x00000201 );
702 else if (yucca_dimms == 1)
703 mtdcr( 0x11, 0x00000000 );
705 /* SET MCIF0_MB3CF */
706 mtdcr( 0x10, 0x0000004c );
707 if (yucca_dimms == 2)
708 mtdcr( 0x11, 0x00000201 );
709 else if (yucca_dimms == 1)
710 mtdcr( 0x11, 0x00000000 );
712 /* SET MCIF0_INITPLR0 # NOP */
713 mtdcr( 0x10, 0x00000050 );
714 mtdcr( 0x11, 0xB5380000 );
716 /* SET MCIF0_INITPLR1 # PRE */
717 mtdcr( 0x10, 0x00000051 );
718 mtdcr( 0x11, 0x82100400 );
720 /* SET MCIF0_INITPLR2 # EMR2 */
721 mtdcr( 0x10, 0x00000052 );
722 mtdcr( 0x11, 0x80820000 );
724 /* SET MCIF0_INITPLR3 # EMR3 */
725 mtdcr( 0x10, 0x00000053 );
726 mtdcr( 0x11, 0x80830000 );
728 /* SET MCIF0_INITPLR4 # EMR DLL ENABLE */
729 mtdcr( 0x10, 0x00000054 );
730 mtdcr( 0x11, 0x80810000 );
732 /* SET MCIF0_INITPLR5 # MR DLL RESET */
733 mtdcr( 0x10, 0x00000055 );
734 mtdcr( 0x11, 0x80800542 );
736 /* SET MCIF0_INITPLR6 # PRE */
737 mtdcr( 0x10, 0x00000056 );
738 mtdcr( 0x11, 0x82100400 );
740 /* SET MCIF0_INITPLR7 # Refresh */
741 mtdcr( 0x10, 0x00000057 );
742 mtdcr( 0x11, 0x8A080000 );
744 /* SET MCIF0_INITPLR8 # Refresh */
745 mtdcr( 0x10, 0x00000058 );
746 mtdcr( 0x11, 0x8A080000 );
748 /* SET MCIF0_INITPLR9 # Refresh */
749 mtdcr( 0x10, 0x00000059 );
750 mtdcr( 0x11, 0x8A080000 );
752 /* SET MCIF0_INITPLR10 # Refresh */
753 mtdcr( 0x10, 0x0000005A );
754 mtdcr( 0x11, 0x8A080000 );
756 /* SET MCIF0_INITPLR11 # MR */
757 mtdcr( 0x10, 0x0000005B );
758 mtdcr( 0x11, 0x80800442 );
760 /* SET MCIF0_INITPLR12 # EMR OCD Default*/
761 mtdcr( 0x10, 0x0000005C );
762 mtdcr( 0x11, 0x80810380 );
764 /* SET MCIF0_INITPLR13 # EMR OCD Exit */
765 mtdcr( 0x10, 0x0000005D );
766 mtdcr( 0x11, 0x80810000 );
768 /* 0x80: Adv Addr clock by 180 deg */
769 mtdcr( 0x10, 0x00000080 );
770 mtdcr( 0x11, 0x80000000 );
772 /* 0x21: Exit self refresh, set DC_EN */
773 mtdcr( 0x10, 0x00000021 );
774 mtdcr( 0x11, 0x28000000 );
776 /* 0x81: Write DQS Adv 90 + Fractional DQS Delay */
777 mtdcr( 0x10, 0x00000081 );
778 mtdcr( 0x11, 0x80000800 );
781 mtdcr( 0x10, 0x00000085 );
782 mtdcr( 0x11, 0x80201000 );
785 mtdcr( 0x10, 0x00000086 );
786 mtdcr( 0x11, 0x42103242 );
789 mtdcr( 0x10, 0x00000087 );
790 mtdcr( 0x11, 0x0C100D14 );
792 /* SET MQ0_B0BAS base addr 00000000 / 256MB */
793 mtdcr( 0x40, 0x0000F800 );
795 /* SET MQ0_B1BAS base addr 10000000 / 256MB */
796 mtdcr( 0x41, 0x0400F800 );
798 /* SET MQ0_B2BAS base addr 20000000 / 256MB */
799 if (yucca_dimms == 2)
800 mtdcr( 0x42, 0x0800F800 );
801 else if (yucca_dimms == 1)
802 mtdcr( 0x42, 0x00000000 );
804 /* SET MQ0_B3BAS base addr 30000000 / 256MB */
805 if (yucca_dimms == 2)
806 mtdcr( 0x43, 0x0C00F800 );
807 else if (yucca_dimms == 1)
808 mtdcr( 0x43, 0x00000000 );
811 mtdcr( 0x10, 0x00000070 );
812 mtdcr( 0x11, 0x8000003F );
815 mtdcr( 0x10, 0x00000078 );
816 mtdcr( 0x11, 0x80000000 );
819 mtdcr( 0x10, 0x00000074 );
820 mtdcr( 0x11, 0x00000220 );
822 return (yucca_dimms * 512) << 20;
825 long int initdram (int board_type)
829 dram_size = fixed_sdram();
834 #if defined(CFG_DRAM_TEST)
837 uint *pstart = (uint *) 0x00000000;
838 uint *pend = (uint *) 0x08000000;
841 for (p = pstart; p < pend; p++)
844 for (p = pstart; p < pend; p++) {
845 if (*p != 0xaaaaaaaa) {
846 printf ("SDRAM test fails at: %08x\n", (uint) p);
851 for (p = pstart; p < pend; p++)
854 for (p = pstart; p < pend; p++) {
855 if (*p != 0x55555555) {
856 printf ("SDRAM test fails at: %08x\n", (uint) p);
864 /*************************************************************************
867 * This routine is called just prior to registering the hose and gives
868 * the board the opportunity to check things. Returning a value of zero
869 * indicates that things are bad & PCI initialization should be aborted.
871 * Different boards may wish to customize the pci controller structure
872 * (add regions, override default access routines, etc) or perform
873 * certain pre-initialization actions.
875 ************************************************************************/
876 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
877 int pci_pre_init(struct pci_controller * hose )
881 /*-------------------------------------------------------------------+
882 * The yucca board is always configured as the host & requires the
883 * PCI arbiter to be enabled.
884 *-------------------------------------------------------------------*/
885 mfsdr(sdr_sdstp1, strap);
886 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
887 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
893 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
895 /*************************************************************************
898 * The bootstrap configuration provides default settings for the pci
899 * inbound map (PIM). But the bootstrap config choices are limited and
900 * may not be sufficient for a given board.
902 ************************************************************************/
903 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
904 void pci_target_init(struct pci_controller * hose )
906 DECLARE_GLOBAL_DATA_PTR;
908 /*-------------------------------------------------------------------+
910 *-------------------------------------------------------------------*/
911 out32r( PCIX0_PIM0SA, 0 ); /* disable */
912 out32r( PCIX0_PIM1SA, 0 ); /* disable */
913 out32r( PCIX0_PIM2SA, 0 ); /* disable */
914 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
916 /*-------------------------------------------------------------------+
917 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
918 * strapping options to not support sizes such as 128/256 MB.
919 *-------------------------------------------------------------------*/
920 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
921 out32r( PCIX0_PIM0LAH, 0 );
922 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
923 out32r( PCIX0_BAR0, 0 );
925 /*-------------------------------------------------------------------+
926 * Program the board's subsystem id/vendor id
927 *-------------------------------------------------------------------*/
928 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
929 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
931 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
933 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
935 #if defined(CONFIG_PCI)
936 /*************************************************************************
939 * This routine is called to determine if a pci scan should be
940 * performed. With various hardware environments (especially cPCI and
941 * PPMC) it's insufficient to depend on the state of the arbiter enable
942 * bit in the strap register, or generic host/adapter assumptions.
944 * Rather than hard-code a bad assumption in the general 440 code, the
945 * 440 pci code requires the board to decide at runtime.
947 * Return 0 for adapter mode, non-zero for host (monarch) mode.
950 ************************************************************************/
951 int is_pci_host(struct pci_controller *hose)
953 /* The yucca board is always configured as host. */
958 int yucca_pcie_card_present(int port)
962 reg = in_be16((u16 *)FPGA_REG1C);
965 return !(reg & FPGA_REG1C_PE0_PRSNT);
967 return !(reg & FPGA_REG1C_PE1_PRSNT);
969 return !(reg & FPGA_REG1C_PE2_PRSNT);
976 * For the given slot, set rootpoint mode, send power to the slot,
977 * turn on the green LED and turn off the yellow LED, enable the clock
978 * and turn off reset.
980 void yucca_setup_pcie_fpga_rootpoint(int port)
982 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
986 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
988 power = FPGA_REG1A_PE0_PWRON;
989 green_led = FPGA_REG1A_PE0_GLED;
990 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
991 yellow_led = FPGA_REG1A_PE0_YLED;
992 reset_off = FPGA_REG1C_PE0_PERST;
996 endpoint = FPGA_REG1C_PE1_ENDPOINT;
997 power = FPGA_REG1A_PE1_PWRON;
998 green_led = FPGA_REG1A_PE1_GLED;
999 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
1000 yellow_led = FPGA_REG1A_PE1_YLED;
1001 reset_off = FPGA_REG1C_PE1_PERST;
1005 endpoint = FPGA_REG1C_PE2_ENDPOINT;
1006 power = FPGA_REG1A_PE2_PWRON;
1007 green_led = FPGA_REG1A_PE2_GLED;
1008 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
1009 yellow_led = FPGA_REG1A_PE2_YLED;
1010 reset_off = FPGA_REG1C_PE2_PERST;
1017 out_be16((u16 *)FPGA_REG1A,
1018 ~(power | clock | green_led) &
1019 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
1021 out_be16((u16 *)FPGA_REG1C,
1022 ~(endpoint | reset_off) &
1023 (rootpoint | in_be16((u16 *)FPGA_REG1C)));
1025 * Leave device in reset for a while after powering on the
1026 * slot to give it a chance to initialize.
1030 out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
1034 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
1036 void pcie_setup_hoses(void)
1038 struct pci_controller *hose;
1042 * assume we're called after the PCIX hose is initialized, which takes
1043 * bus ID 0 and therefore start numbering PCIe's from 1.
1046 for (i = 0; i <= 2; i++) {
1047 /* Check for yucca card presence */
1048 if (!yucca_pcie_card_present(i))
1051 yucca_setup_pcie_fpga_rootpoint(i);
1053 if (ppc440spe_init_pcie_rootport(i)) {
1054 printf("PCIE%d: initialization failed\n", i);
1058 hose = &pcie_hose[i];
1059 hose->first_busno = bus;
1060 hose->last_busno = bus;
1063 /* setup mem resource */
1064 pci_set_region(hose->regions + 0,
1065 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
1066 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
1070 hose->region_count = 1;
1071 pci_register_hose(hose);
1073 ppc440spe_setup_pcie(hose, i);
1074 hose->last_busno = pci_hose_scan(hose);
1077 #endif /* defined(CONFIG_PCI) */
1079 int misc_init_f (void)
1082 #if defined(CONFIG_STRESS)
1087 out16(FPGA_REG10, (in16(FPGA_REG10) &
1088 ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
1089 FPGA_REG10_10MHZ_ENABLE |
1090 FPGA_REG10_100MHZ_ENABLE |
1091 FPGA_REG10_GIGABIT_ENABLE |
1092 FPGA_REG10_FULL_DUPLEX );
1094 udelay(10000); /* wait 10ms */
1096 out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
1098 /* minimal init for PCIe */
1099 /* pci express 0 Endpoint Mode */
1100 mfsdr(SDR0_PE0DLPSET, reg);
1101 reg &= (~0x00400000);
1102 mtsdr(SDR0_PE0DLPSET, reg);
1103 /* pci express 1 Rootpoint Mode */
1104 mfsdr(SDR0_PE1DLPSET, reg);
1106 mtsdr(SDR0_PE1DLPSET, reg);
1107 /* pci express 2 Rootpoint Mode */
1108 mfsdr(SDR0_PE2DLPSET, reg);
1110 mtsdr(SDR0_PE2DLPSET, reg);
1112 out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
1113 ~FPGA_REG1C_PE0_ROOTPOINT &
1114 ~FPGA_REG1C_PE1_ENDPOINT &
1115 ~FPGA_REG1C_PE2_ENDPOINT));
1117 #if defined(CONFIG_STRESS)
1119 * all this setting done by linux only needed by stress an charac. test
1121 * PCIe 1 Rootpoint PCIe2 Endpoint
1122 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1125 for (i = 0, disp = 0; i < 8; i++, disp += 3) {
1126 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
1128 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
1132 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1135 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
1136 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
1138 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
1142 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1145 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
1146 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1148 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1152 mtsdr(SDR0_PE2UTLSET1, reg);
1154 mtsdr(SDR0_PE2UTLSET2, reg);
1155 /* pci express 1 Endpoint Mode */
1157 mtsdr(SDR0_PE2DLPSET, reg);
1159 mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
1164 void fpga_init(void)
1167 * by default sdram access is disabled by fpga
1169 out16(FPGA_REG10, (in16 (FPGA_REG10) |
1170 FPGA_REG10_SDRAM_ENABLE |
1171 FPGA_REG10_ENABLE_DISPLAY ));
1178 * Returns 1 if keys pressed to start the power-on long-running tests
1179 * Called from board_init_f().
1181 int post_hotkeys_pressed(void)
1187 /*---------------------------------------------------------------------------+
1188 | onboard_pci_arbiter_selected => from EPLD
1189 +---------------------------------------------------------------------------*/
1190 int onboard_pci_arbiter_selected(int core_pci)
1193 unsigned long onboard_pci_arbiter_sel;
1195 onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1197 if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1198 return (BOARD_OPTION_SELECTED);
1201 return (BOARD_OPTION_NOT_SELECTED);
1204 /*---------------------------------------------------------------------------+
1206 +---------------------------------------------------------------------------*/
1207 unsigned long ppcMfcpr(unsigned long cpr_reg)
1210 unsigned long cpr_cfgaddr_temp;
1211 unsigned long cpr_value;
1213 msr = (mfmsr () & ~(MSR_EE));
1214 cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR);
1215 mtdcr(CPR0_CFGADDR, cpr_reg);
1216 cpr_value = mfdcr(CPR0_CFGDATA);
1217 mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
1223 /*----------------------------------------------------------------------------+
1224 | Indirect Access of the System DCR's (SDR)
1226 +----------------------------------------------------------------------------*/
1227 unsigned long ppcMfsdr(unsigned long sdr_reg)
1230 unsigned long sdr_cfgaddr_temp;
1231 unsigned long sdr_value;
1233 msr = (mfmsr () & ~(MSR_EE));
1234 sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR);
1235 mtdcr(SDR0_CFGADDR, sdr_reg);
1236 sdr_value = mfdcr(SDR0_CFGDATA);
1237 mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);