board/amcc/yosemite/yosemite.c

   1 /*
   2  *
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <ppc4xx.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  30
  31 int board_early_init_f(void)
  32 {
  33         register uint reg;
  34
  35         /*--------------------------------------------------------------------
  36          * Setup the external bus controller/chip selects
  37          *-------------------------------------------------------------------*/
  38         mtdcr(ebccfga, xbcfg);
  39         reg = mfdcr(ebccfgd);
  40         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  41
  42         /*--------------------------------------------------------------------
  43          * Setup the GPIO pins
  44          *-------------------------------------------------------------------*/
  45         /*CPLD cs */
  46         /*setup Address lines for flash size 64Meg. */
  47         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  48         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  49         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  50
  51         /*setup emac */
  52         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  53         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  54         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  55         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  56         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  57
  58         /*UART1 */
  59         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  60         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  61         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  62
  63         /* external interrupts IRQ0...3 */
  64         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  65         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
  66         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  67
  68 #ifdef CONFIG_440EP
  69         /*setup USB 2.0 */
  70         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  71         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  72         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  73         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  74         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  75 #endif
  76
  77         /*--------------------------------------------------------------------
  78          * Setup the interrupt controller polarities, triggers, etc.
  79          *-------------------------------------------------------------------*/
  80         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  81         mtdcr(uic0er, 0x00000000);      /* disable all */
  82         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
  83         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
  84         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
  85         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
  86         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  87
  88         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  89         mtdcr(uic1er, 0x00000000);      /* disable all */
  90         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  91         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
  92         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
  93         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
  94         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  95
  96         /*--------------------------------------------------------------------
  97          * Setup other serial configuration
  98          *-------------------------------------------------------------------*/
  99         mfsdr(sdr_pci0, reg);
 100         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
 101         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 102         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 103
 104         /*clear tmrclk divisor */
 105         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 106
 107         /*enable ethernet */
 108         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 109
 110 #ifdef CONFIG_440EP
 111         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 112         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 113 #endif
 114
 115         /*get rid of flash write protect */
 116         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 117
 118         return 0;
 119 }
 120
 121 int misc_init_r (void)
 122 {
 123         uint pbcr;
 124         int size_val = 0;
 125
 126         /* Re-do sizing to get full correct info */
 127         mtdcr(ebccfga, pb0cr);
 128         pbcr = mfdcr(ebccfgd);
 129         switch (gd->bd->bi_flashsize) {
 130         case 1 << 20:
 131                 size_val = 0;
 132                 break;
 133         case 2 << 20:
 134                 size_val = 1;
 135                 break;
 136         case 4 << 20:
 137                 size_val = 2;
 138                 break;
 139         case 8 << 20:
 140                 size_val = 3;
 141                 break;
 142         case 16 << 20:
 143                 size_val = 4;
 144                 break;
 145         case 32 << 20:
 146                 size_val = 5;
 147                 break;
 148         case 64 << 20:
 149                 size_val = 6;
 150                 break;
 151         case 128 << 20:
 152                 size_val = 7;
 153                 break;
 154         }
 155         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 156         mtdcr(ebccfga, pb0cr);
 157         mtdcr(ebccfgd, pbcr);
 158
 159         /* adjust flash start and offset */
 160         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 161         gd->bd->bi_flashoffset = 0;
 162
 163         /* Monitor protection ON by default */
 164         (void)flash_protect(FLAG_PROTECT_SET,
 165                             -CFG_MONITOR_LEN,
 166                             0xffffffff,
 167                             &flash_info[0]);
 168
 169         return 0;
 170 }
 171
 172 int checkboard(void)
 173 {
 174         char *s = getenv("serial#");
 175         u8 rev;
 176         u8 val;
 177
 178 #ifdef CONFIG_440EP
 179         printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
 180 #else
 181         printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 182 #endif
 183
 184         rev = *(u8 *)(CFG_CPLD + 0);
 185         val = *(u8 *)(CFG_CPLD + 5) & 0x01;
 186         printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 187
 188         if (s != NULL) {
 189                 puts(", serial# ");
 190                 puts(s);
 191         }
 192         putc('\n');
 193
 194         return (0);
 195 }
 196
 197 /*************************************************************************
 198  *  sdram_init -- doesn't use serial presence detect.
 199  *
 200  *  Assumes:    256 MB, ECC, non-registered
 201  *              PLB @ 133 MHz
 202  *
 203  ************************************************************************/
 204 #define NUM_TRIES 64
 205 #define NUM_READS 10
 206
 207 void sdram_tr1_set(int ram_address, int* tr1_value)
 208 {
 209         int i;
 210         int j, k;
 211         volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 212         int first_good = -1, last_bad = 0x1ff;
 213
 214         unsigned long test[NUM_TRIES] = {
 215                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 216                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 217                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 218                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 219                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 220                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 221                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 222                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 223                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 224                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 225                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 226                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 227                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 228                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 229                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 230                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 231
 232         /* go through all possible SDRAM0_TR1[RDCT] values */
 233         for (i=0; i<=0x1ff; i++) {
 234                 /* set the current value for TR1 */
 235                 mtsdram(mem_tr1, (0x80800800 | i));
 236
 237                 /* write values */
 238                 for (j=0; j<NUM_TRIES; j++) {
 239                         ram_pointer[j] = test[j];
 240
 241                         /* clear any cache at ram location */
 242                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 243                 }
 244
 245                 /* read values back */
 246                 for (j=0; j<NUM_TRIES; j++) {
 247                         for (k=0; k<NUM_READS; k++) {
 248                                 /* clear any cache at ram location */
 249                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 250
 251                                 if (ram_pointer[j] != test[j])
 252                                         break;
 253                         }
 254
 255                         /* read error */
 256                         if (k != NUM_READS) {
 257                                 break;
 258                         }
 259                 }
 260
 261                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 262                 if (j == NUM_TRIES) {
 263                         if (first_good == -1)
 264                                 first_good = i;         /* found beginning of window */
 265                 } else { /* bad read */
 266                         /* if we have not had a good read then don't care */
 267                         if(first_good != -1) {
 268                                 /* first failure after a good read */
 269                                 last_bad = i-1;
 270                                 break;
 271                         }
 272                 }
 273         }
 274
 275         /* return the current value for TR1 */
 276         *tr1_value = (first_good + last_bad) / 2;
 277 }
 278
 279 void sdram_init(void)
 280 {
 281         register uint reg;
 282         int tr1_bank1, tr1_bank2;
 283
 284         /*--------------------------------------------------------------------
 285          * Setup some default
 286          *------------------------------------------------------------------*/
 287         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 288         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 289         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 290         mtsdram(mem_clktr, 0x40000000); /* ?? */
 291         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 292
 293         /*clear this first, if the DDR is enabled by a debugger
 294           then you can not make changes. */
 295         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 296
 297         /*--------------------------------------------------------------------
 298          * Setup for board-specific specific mem
 299          *------------------------------------------------------------------*/
 300         /*
 301          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 302          */
 303         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 304         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 305
 306         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 307         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 308         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 309         mtsdram(mem_cfg0, 0x30000000);  /* Disable EEC */
 310         udelay(400);            /* Delay 200 usecs (min)            */
 311
 312         /*--------------------------------------------------------------------
 313          * Enable the controller, then wait for DCEN to complete
 314          *------------------------------------------------------------------*/
 315         mtsdram(mem_cfg0, 0x80000000);  /* Enable */
 316
 317         for (;;) {
 318                 mfsdram(mem_mcsts, reg);
 319                 if (reg & 0x80000000)
 320                         break;
 321         }
 322
 323         sdram_tr1_set(0x00000000, &tr1_bank1);
 324         sdram_tr1_set(0x08000000, &tr1_bank2);
 325         mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
 326 }
 327
 328 /*************************************************************************
 329  *  long int initdram
 330  *
 331  ************************************************************************/
 332 long int initdram(int board)
 333 {
 334         sdram_init();
 335         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 336 }
 337
 338 #if defined(CFG_DRAM_TEST)
 339 int testdram(void)
 340 {
 341         unsigned long *mem = (unsigned long *)0;
 342         const unsigned long kend = (1024 / sizeof(unsigned long));
 343         unsigned long k, n;
 344
 345         mtmsr(0);
 346
 347         for (k = 0; k < CFG_KBYTES_SDRAM;
 348              ++k, mem += (1024 / sizeof(unsigned long))) {
 349                 if ((k & 1023) == 0) {
 350                         printf("%3d MB\r", k / 1024);
 351                 }
 352
 353                 memset(mem, 0xaaaaaaaa, 1024);
 354                 for (n = 0; n < kend; ++n) {
 355                         if (mem[n] != 0xaaaaaaaa) {
 356                                 printf("SDRAM test fails at: %08x\n",
 357                                        (uint) & mem[n]);
 358                                 return 1;
 359                         }
 360                 }
 361
 362                 memset(mem, 0x55555555, 1024);
 363                 for (n = 0; n < kend; ++n) {
 364                         if (mem[n] != 0x55555555) {
 365                                 printf("SDRAM test fails at: %08x\n",
 366                                        (uint) & mem[n]);
 367                                 return 1;
 368                         }
 369                 }
 370         }
 371         printf("SDRAM test passes\n");
 372         return 0;
 373 }
 374 #endif
 375
 376 /*************************************************************************
 377  *  pci_pre_init
 378  *
 379  *  This routine is called just prior to registering the hose and gives
 380  *  the board the opportunity to check things. Returning a value of zero
 381  *  indicates that things are bad & PCI initialization should be aborted.
 382  *
 383  *      Different boards may wish to customize the pci controller structure
 384  *      (add regions, override default access routines, etc) or perform
 385  *      certain pre-initialization actions.
 386  *
 387  ************************************************************************/
 388 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 389 int pci_pre_init(struct pci_controller *hose)
 390 {
 391         unsigned long addr;
 392
 393         /*-------------------------------------------------------------------------+
 394           | Set priority for all PLB3 devices to 0.
 395           | Set PLB3 arbiter to fair mode.
 396           +-------------------------------------------------------------------------*/
 397         mfsdr(sdr_amp1, addr);
 398         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 399         addr = mfdcr(plb3_acr);
 400         mtdcr(plb3_acr, addr | 0x80000000);
 401
 402         /*-------------------------------------------------------------------------+
 403           | Set priority for all PLB4 devices to 0.
 404           +-------------------------------------------------------------------------*/
 405         mfsdr(sdr_amp0, addr);
 406         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 407         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 408         mtdcr(plb4_acr, addr);
 409
 410         /*-------------------------------------------------------------------------+
 411           | Set Nebula PLB4 arbiter to fair mode.
 412           +-------------------------------------------------------------------------*/
 413         /* Segment0 */
 414         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 415         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 416         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 417         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 418         mtdcr(plb0_acr, addr);
 419
 420         /* Segment1 */
 421         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 422         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 423         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 424         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 425         mtdcr(plb1_acr, addr);
 426
 427         return 1;
 428 }
 429 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 430
 431 /*************************************************************************
 432  *  pci_target_init
 433  *
 434  *      The bootstrap configuration provides default settings for the pci
 435  *      inbound map (PIM). But the bootstrap config choices are limited and
 436  *      may not be sufficient for a given board.
 437  *
 438  ************************************************************************/
 439 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 440 void pci_target_init(struct pci_controller *hose)
 441 {
 442         /*--------------------------------------------------------------------------+
 443          * Set up Direct MMIO registers
 444          *--------------------------------------------------------------------------*/
 445         /*--------------------------------------------------------------------------+
 446           | PowerPC440 EP PCI Master configuration.
 447           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 448           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 449           |   Use byte reversed out routines to handle endianess.
 450           | Make this region non-prefetchable.
 451           +--------------------------------------------------------------------------*/
 452         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 453         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 454         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 455         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 456         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 457
 458         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 459         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 460         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 461         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 462         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 463
 464         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 465         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 466         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 467         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 468
 469         /*--------------------------------------------------------------------------+
 470          * Set up Configuration registers
 471          *--------------------------------------------------------------------------*/
 472
 473         /* Program the board's subsystem id/vendor id */
 474         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 475                               CFG_PCI_SUBSYS_VENDORID);
 476         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 477
 478         /* Configure command register as bus master */
 479         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 480
 481         /* 240nS PCI clock */
 482         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 483
 484         /* No error reporting */
 485         pci_write_config_word(0, PCI_ERREN, 0);
 486
 487         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 488
 489 }
 490 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 491
 492 /*************************************************************************
 493  *  pci_master_init
 494  *
 495  ************************************************************************/
 496 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 497 void pci_master_init(struct pci_controller *hose)
 498 {
 499         unsigned short temp_short;
 500
 501         /*--------------------------------------------------------------------------+
 502           | Write the PowerPC440 EP PCI Configuration regs.
 503           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 504           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 505           +--------------------------------------------------------------------------*/
 506         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 507         pci_write_config_word(0, PCI_COMMAND,
 508                               temp_short | PCI_COMMAND_MASTER |
 509                               PCI_COMMAND_MEMORY);
 510 }
 511 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 512
 513 /*************************************************************************
 514  *  is_pci_host
 515  *
 516  *      This routine is called to determine if a pci scan should be
 517  *      performed. With various hardware environments (especially cPCI and
 518  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 519  *      bit in the strap register, or generic host/adapter assumptions.
 520  *
 521  *      Rather than hard-code a bad assumption in the general 440 code, the
 522  *      440 pci code requires the board to decide at runtime.
 523  *
 524  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 525  *
 526  *
 527  ************************************************************************/
 528 #if defined(CONFIG_PCI)
 529 int is_pci_host(struct pci_controller *hose)
 530 {
 531         /* Bamboo is always configured as host. */
 532         return (1);
 533 }
 534 #endif                          /* defined(CONFIG_PCI) */
 535
 536 /*************************************************************************
 537  *  hw_watchdog_reset
 538  *
 539  *      This routine is called to reset (keep alive) the watchdog timer
 540  *
 541  ************************************************************************/
 542 #if defined(CONFIG_HW_WATCHDOG)
 543 void hw_watchdog_reset(void)
 544 {
 545
 546 }
 547 #endif
 548
 549 void board_reset(void)
 550 {
 551         /* give reset to BCSR */
 552         *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
 553 }