board/amcc/yosemite/yosemite.c

   1 /*
   2  *
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <ppc4xx.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  30
  31 int board_early_init_f(void)
  32 {
  33         register uint reg;
  34
  35         /*--------------------------------------------------------------------
  36          * Setup the external bus controller/chip selects
  37          *-------------------------------------------------------------------*/
  38         mtdcr(ebccfga, xbcfg);
  39         reg = mfdcr(ebccfgd);
  40         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  41
  42         /*--------------------------------------------------------------------
  43          * Setup the GPIO pins
  44          *-------------------------------------------------------------------*/
  45         /*CPLD cs */
  46         /*setup Address lines for flash size 64Meg. */
  47         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  48         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  49         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  50
  51         /*setup emac */
  52         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  53         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  54         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  55         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  56         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  57
  58         /*UART1 */
  59         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  60         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  61         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  62
  63         /* external interrupts IRQ0...3 */
  64         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  65         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
  66         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  67
  68         /*setup USB 2.0 */
  69         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  70         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  71         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  72         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  73         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  74
  75         /*--------------------------------------------------------------------
  76          * Setup the interrupt controller polarities, triggers, etc.
  77          *-------------------------------------------------------------------*/
  78         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  79         mtdcr(uic0er, 0x00000000);      /* disable all */
  80         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
  81         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
  82         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
  83         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
  84         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  85
  86         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  87         mtdcr(uic1er, 0x00000000);      /* disable all */
  88         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  89         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
  90         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
  91         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
  92         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  93
  94         /*--------------------------------------------------------------------
  95          * Setup other serial configuration
  96          *-------------------------------------------------------------------*/
  97         mfsdr(sdr_pci0, reg);
  98         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
  99         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 100         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 101
 102         /*clear tmrclk divisor */
 103         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 104
 105         /*enable ethernet */
 106         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 107
 108         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 109         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 110
 111         /*get rid of flash write protect */
 112         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 113
 114         return 0;
 115 }
 116
 117 int misc_init_r (void)
 118 {
 119         uint pbcr;
 120         int size_val = 0;
 121
 122         /* Re-do sizing to get full correct info */
 123         mtdcr(ebccfga, pb0cr);
 124         pbcr = mfdcr(ebccfgd);
 125         switch (gd->bd->bi_flashsize) {
 126         case 1 << 20:
 127                 size_val = 0;
 128                 break;
 129         case 2 << 20:
 130                 size_val = 1;
 131                 break;
 132         case 4 << 20:
 133                 size_val = 2;
 134                 break;
 135         case 8 << 20:
 136                 size_val = 3;
 137                 break;
 138         case 16 << 20:
 139                 size_val = 4;
 140                 break;
 141         case 32 << 20:
 142                 size_val = 5;
 143                 break;
 144         case 64 << 20:
 145                 size_val = 6;
 146                 break;
 147         case 128 << 20:
 148                 size_val = 7;
 149                 break;
 150         }
 151         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 152         mtdcr(ebccfga, pb0cr);
 153         mtdcr(ebccfgd, pbcr);
 154
 155         /* adjust flash start and offset */
 156         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 157         gd->bd->bi_flashoffset = 0;
 158
 159         /* Monitor protection ON by default */
 160         (void)flash_protect(FLAG_PROTECT_SET,
 161                             -CFG_MONITOR_LEN,
 162                             0xffffffff,
 163                             &flash_info[0]);
 164
 165         return 0;
 166 }
 167
 168 int checkboard(void)
 169 {
 170         char *s = getenv("serial#");
 171         u8 rev;
 172         u8 val;
 173
 174         printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
 175
 176         rev = *(u8 *)(CFG_CPLD + 0);
 177         val = *(u8 *)(CFG_CPLD + 5) & 0x01;
 178         printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 179
 180         if (s != NULL) {
 181                 puts(", serial# ");
 182                 puts(s);
 183         }
 184         putc('\n');
 185
 186         return (0);
 187 }
 188
 189 /*************************************************************************
 190  *  sdram_init -- doesn't use serial presence detect.
 191  *
 192  *  Assumes:    256 MB, ECC, non-registered
 193  *              PLB @ 133 MHz
 194  *
 195  ************************************************************************/
 196 #define NUM_TRIES 64
 197 #define NUM_READS 10
 198
 199 void sdram_tr1_set(int ram_address, int* tr1_value)
 200 {
 201         int i;
 202         int j, k;
 203         volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 204         int first_good = -1, last_bad = 0x1ff;
 205
 206         unsigned long test[NUM_TRIES] = {
 207                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 208                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 209                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 210                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 211                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 212                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 213                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 214                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 215                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 216                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 217                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 218                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 219                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 220                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 221                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 222                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 223
 224         /* go through all possible SDRAM0_TR1[RDCT] values */
 225         for (i=0; i<=0x1ff; i++) {
 226                 /* set the current value for TR1 */
 227                 mtsdram(mem_tr1, (0x80800800 | i));
 228
 229                 /* write values */
 230                 for (j=0; j<NUM_TRIES; j++) {
 231                         ram_pointer[j] = test[j];
 232
 233                         /* clear any cache at ram location */
 234                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 235                 }
 236
 237                 /* read values back */
 238                 for (j=0; j<NUM_TRIES; j++) {
 239                         for (k=0; k<NUM_READS; k++) {
 240                                 /* clear any cache at ram location */
 241                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 242
 243                                 if (ram_pointer[j] != test[j])
 244                                         break;
 245                         }
 246
 247                         /* read error */
 248                         if (k != NUM_READS) {
 249                                 break;
 250                         }
 251                 }
 252
 253                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 254                 if (j == NUM_TRIES) {
 255                         if (first_good == -1)
 256                                 first_good = i;         /* found beginning of window */
 257                 } else { /* bad read */
 258                         /* if we have not had a good read then don't care */
 259                         if(first_good != -1) {
 260                                 /* first failure after a good read */
 261                                 last_bad = i-1;
 262                                 break;
 263                         }
 264                 }
 265         }
 266
 267         /* return the current value for TR1 */
 268         *tr1_value = (first_good + last_bad) / 2;
 269 }
 270
 271 void sdram_init(void)
 272 {
 273         register uint reg;
 274         int tr1_bank1, tr1_bank2;
 275
 276         /*--------------------------------------------------------------------
 277          * Setup some default
 278          *------------------------------------------------------------------*/
 279         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 280         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 281         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 282         mtsdram(mem_clktr, 0x40000000); /* ?? */
 283         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 284
 285         /*clear this first, if the DDR is enabled by a debugger
 286           then you can not make changes. */
 287         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 288
 289         /*--------------------------------------------------------------------
 290          * Setup for board-specific specific mem
 291          *------------------------------------------------------------------*/
 292         /*
 293          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 294          */
 295         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 296         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 297
 298         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 299         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 300         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 301         mtsdram(mem_cfg0, 0x30000000);  /* Disable EEC */
 302         udelay(400);            /* Delay 200 usecs (min)            */
 303
 304         /*--------------------------------------------------------------------
 305          * Enable the controller, then wait for DCEN to complete
 306          *------------------------------------------------------------------*/
 307         mtsdram(mem_cfg0, 0x80000000);  /* Enable */
 308
 309         for (;;) {
 310                 mfsdram(mem_mcsts, reg);
 311                 if (reg & 0x80000000)
 312                         break;
 313         }
 314
 315         sdram_tr1_set(0x00000000, &tr1_bank1);
 316         sdram_tr1_set(0x08000000, &tr1_bank2);
 317         mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
 318 }
 319
 320 /*************************************************************************
 321  *  long int initdram
 322  *
 323  ************************************************************************/
 324 long int initdram(int board)
 325 {
 326         sdram_init();
 327         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 328 }
 329
 330 #if defined(CFG_DRAM_TEST)
 331 int testdram(void)
 332 {
 333         unsigned long *mem = (unsigned long *)0;
 334         const unsigned long kend = (1024 / sizeof(unsigned long));
 335         unsigned long k, n;
 336
 337         mtmsr(0);
 338
 339         for (k = 0; k < CFG_KBYTES_SDRAM;
 340              ++k, mem += (1024 / sizeof(unsigned long))) {
 341                 if ((k & 1023) == 0) {
 342                         printf("%3d MB\r", k / 1024);
 343                 }
 344
 345                 memset(mem, 0xaaaaaaaa, 1024);
 346                 for (n = 0; n < kend; ++n) {
 347                         if (mem[n] != 0xaaaaaaaa) {
 348                                 printf("SDRAM test fails at: %08x\n",
 349                                        (uint) & mem[n]);
 350                                 return 1;
 351                         }
 352                 }
 353
 354                 memset(mem, 0x55555555, 1024);
 355                 for (n = 0; n < kend; ++n) {
 356                         if (mem[n] != 0x55555555) {
 357                                 printf("SDRAM test fails at: %08x\n",
 358                                        (uint) & mem[n]);
 359                                 return 1;
 360                         }
 361                 }
 362         }
 363         printf("SDRAM test passes\n");
 364         return 0;
 365 }
 366 #endif
 367
 368 /*************************************************************************
 369  *  pci_pre_init
 370  *
 371  *  This routine is called just prior to registering the hose and gives
 372  *  the board the opportunity to check things. Returning a value of zero
 373  *  indicates that things are bad & PCI initialization should be aborted.
 374  *
 375  *      Different boards may wish to customize the pci controller structure
 376  *      (add regions, override default access routines, etc) or perform
 377  *      certain pre-initialization actions.
 378  *
 379  ************************************************************************/
 380 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 381 int pci_pre_init(struct pci_controller *hose)
 382 {
 383         unsigned long addr;
 384
 385         /*-------------------------------------------------------------------------+
 386           | Set priority for all PLB3 devices to 0.
 387           | Set PLB3 arbiter to fair mode.
 388           +-------------------------------------------------------------------------*/
 389         mfsdr(sdr_amp1, addr);
 390         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 391         addr = mfdcr(plb3_acr);
 392         mtdcr(plb3_acr, addr | 0x80000000);
 393
 394         /*-------------------------------------------------------------------------+
 395           | Set priority for all PLB4 devices to 0.
 396           +-------------------------------------------------------------------------*/
 397         mfsdr(sdr_amp0, addr);
 398         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 399         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 400         mtdcr(plb4_acr, addr);
 401
 402         /*-------------------------------------------------------------------------+
 403           | Set Nebula PLB4 arbiter to fair mode.
 404           +-------------------------------------------------------------------------*/
 405         /* Segment0 */
 406         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 407         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 408         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 409         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 410         mtdcr(plb0_acr, addr);
 411
 412         /* Segment1 */
 413         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 414         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 415         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 416         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 417         mtdcr(plb1_acr, addr);
 418
 419         return 1;
 420 }
 421 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 422
 423 /*************************************************************************
 424  *  pci_target_init
 425  *
 426  *      The bootstrap configuration provides default settings for the pci
 427  *      inbound map (PIM). But the bootstrap config choices are limited and
 428  *      may not be sufficient for a given board.
 429  *
 430  ************************************************************************/
 431 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 432 void pci_target_init(struct pci_controller *hose)
 433 {
 434         /*--------------------------------------------------------------------------+
 435          * Set up Direct MMIO registers
 436          *--------------------------------------------------------------------------*/
 437         /*--------------------------------------------------------------------------+
 438           | PowerPC440 EP PCI Master configuration.
 439           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 440           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 441           |   Use byte reversed out routines to handle endianess.
 442           | Make this region non-prefetchable.
 443           +--------------------------------------------------------------------------*/
 444         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 445         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 446         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 447         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 448         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 449
 450         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 451         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 452         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 453         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 454         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 455
 456         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 457         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 458         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 459         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 460
 461         /*--------------------------------------------------------------------------+
 462          * Set up Configuration registers
 463          *--------------------------------------------------------------------------*/
 464
 465         /* Program the board's subsystem id/vendor id */
 466         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 467                               CFG_PCI_SUBSYS_VENDORID);
 468         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 469
 470         /* Configure command register as bus master */
 471         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 472
 473         /* 240nS PCI clock */
 474         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 475
 476         /* No error reporting */
 477         pci_write_config_word(0, PCI_ERREN, 0);
 478
 479         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 480
 481 }
 482 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 483
 484 /*************************************************************************
 485  *  pci_master_init
 486  *
 487  ************************************************************************/
 488 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 489 void pci_master_init(struct pci_controller *hose)
 490 {
 491         unsigned short temp_short;
 492
 493         /*--------------------------------------------------------------------------+
 494           | Write the PowerPC440 EP PCI Configuration regs.
 495           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 496           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 497           +--------------------------------------------------------------------------*/
 498         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 499         pci_write_config_word(0, PCI_COMMAND,
 500                               temp_short | PCI_COMMAND_MASTER |
 501                               PCI_COMMAND_MEMORY);
 502 }
 503 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 504
 505 /*************************************************************************
 506  *  is_pci_host
 507  *
 508  *      This routine is called to determine if a pci scan should be
 509  *      performed. With various hardware environments (especially cPCI and
 510  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 511  *      bit in the strap register, or generic host/adapter assumptions.
 512  *
 513  *      Rather than hard-code a bad assumption in the general 440 code, the
 514  *      440 pci code requires the board to decide at runtime.
 515  *
 516  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 517  *
 518  *
 519  ************************************************************************/
 520 #if defined(CONFIG_PCI)
 521 int is_pci_host(struct pci_controller *hose)
 522 {
 523         /* Bamboo is always configured as host. */
 524         return (1);
 525 }
 526 #endif                          /* defined(CONFIG_PCI) */
 527
 528 /*************************************************************************
 529  *  hw_watchdog_reset
 530  *
 531  *      This routine is called to reset (keep alive) the watchdog timer
 532  *
 533  ************************************************************************/
 534 #if defined(CONFIG_HW_WATCHDOG)
 535 void hw_watchdog_reset(void)
 536 {
 537
 538 }
 539 #endif
 540
 541 void board_reset(void)
 542 {
 543         /* give reset to BCSR */
 544         *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
 545 }