board/amcc/yosemite/yosemite.c

   1 /*
   2  * (C) Copyright 2006-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ppc4xx.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <spd_sdram.h>
  29 #include <libfdt.h>
  30 #include <fdt_support.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  35
  36 int board_early_init_f(void)
  37 {
  38         register uint reg;
  39
  40         /*--------------------------------------------------------------------
  41          * Setup the external bus controller/chip selects
  42          *-------------------------------------------------------------------*/
  43         mtdcr(ebccfga, xbcfg);
  44         reg = mfdcr(ebccfgd);
  45         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  46
  47         /*--------------------------------------------------------------------
  48          * Setup the GPIO pins
  49          *-------------------------------------------------------------------*/
  50         /*CPLD cs */
  51         /*setup Address lines for flash size 64Meg. */
  52         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  53         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  54         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  55
  56         /*setup emac */
  57         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  58         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  59         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  60         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  61         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  62
  63         /*UART1 */
  64         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  65         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  66         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  67
  68         /* external interrupts IRQ0...3 */
  69         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  70         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
  71         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  72
  73 #ifdef CONFIG_440EP
  74         /*setup USB 2.0 */
  75         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  76         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  77         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  78         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  79         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  80 #endif
  81
  82         /*--------------------------------------------------------------------
  83          * Setup the interrupt controller polarities, triggers, etc.
  84          *-------------------------------------------------------------------*/
  85         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  86         mtdcr(uic0er, 0x00000000);      /* disable all */
  87         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
  88         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
  89         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
  90         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
  91         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  92
  93         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  94         mtdcr(uic1er, 0x00000000);      /* disable all */
  95         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  96         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
  97         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
  98         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
  99         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 100
 101         /*--------------------------------------------------------------------
 102          * Setup other serial configuration
 103          *-------------------------------------------------------------------*/
 104         mfsdr(sdr_pci0, reg);
 105         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
 106         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 107         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 108
 109         /*clear tmrclk divisor */
 110         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 111
 112         /*enable ethernet */
 113         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 114
 115 #ifdef CONFIG_440EP
 116         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 117         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 118 #endif
 119
 120         /*get rid of flash write protect */
 121         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 122
 123         return 0;
 124 }
 125
 126 int misc_init_r (void)
 127 {
 128         uint pbcr;
 129         int size_val = 0;
 130
 131         /* Re-do sizing to get full correct info */
 132         mtdcr(ebccfga, pb0cr);
 133         pbcr = mfdcr(ebccfgd);
 134         switch (gd->bd->bi_flashsize) {
 135         case 1 << 20:
 136                 size_val = 0;
 137                 break;
 138         case 2 << 20:
 139                 size_val = 1;
 140                 break;
 141         case 4 << 20:
 142                 size_val = 2;
 143                 break;
 144         case 8 << 20:
 145                 size_val = 3;
 146                 break;
 147         case 16 << 20:
 148                 size_val = 4;
 149                 break;
 150         case 32 << 20:
 151                 size_val = 5;
 152                 break;
 153         case 64 << 20:
 154                 size_val = 6;
 155                 break;
 156         case 128 << 20:
 157                 size_val = 7;
 158                 break;
 159         }
 160         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 161         mtdcr(ebccfga, pb0cr);
 162         mtdcr(ebccfgd, pbcr);
 163
 164         /* adjust flash start and offset */
 165         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 166         gd->bd->bi_flashoffset = 0;
 167
 168         /* Monitor protection ON by default */
 169         (void)flash_protect(FLAG_PROTECT_SET,
 170                             -CFG_MONITOR_LEN,
 171                             0xffffffff,
 172                             &flash_info[0]);
 173
 174         return 0;
 175 }
 176
 177 int checkboard(void)
 178 {
 179         char *s = getenv("serial#");
 180         u8 rev;
 181         u8 val;
 182
 183 #ifdef CONFIG_440EP
 184         printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
 185 #else
 186         printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 187 #endif
 188
 189         rev = in_8((void *)(CFG_BCSR_BASE + 0));
 190         val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
 191         printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 192
 193         if (s != NULL) {
 194                 puts(", serial# ");
 195                 puts(s);
 196         }
 197         putc('\n');
 198
 199         return (0);
 200 }
 201
 202 /*************************************************************************
 203  *  sdram_init -- doesn't use serial presence detect.
 204  *
 205  *  Assumes:    256 MB, ECC, non-registered
 206  *              PLB @ 133 MHz
 207  *
 208  ************************************************************************/
 209 #define NUM_TRIES 64
 210 #define NUM_READS 10
 211
 212 void sdram_tr1_set(int ram_address, int* tr1_value)
 213 {
 214         int i;
 215         int j, k;
 216         volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 217         int first_good = -1, last_bad = 0x1ff;
 218
 219         unsigned long test[NUM_TRIES] = {
 220                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 221                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 222                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 223                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 224                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 225                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 226                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 227                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 228                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 229                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 230                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 231                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 232                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 233                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 234                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 235                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 236
 237         /* go through all possible SDRAM0_TR1[RDCT] values */
 238         for (i=0; i<=0x1ff; i++) {
 239                 /* set the current value for TR1 */
 240                 mtsdram(mem_tr1, (0x80800800 | i));
 241
 242                 /* write values */
 243                 for (j=0; j<NUM_TRIES; j++) {
 244                         ram_pointer[j] = test[j];
 245
 246                         /* clear any cache at ram location */
 247                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 248                 }
 249
 250                 /* read values back */
 251                 for (j=0; j<NUM_TRIES; j++) {
 252                         for (k=0; k<NUM_READS; k++) {
 253                                 /* clear any cache at ram location */
 254                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 255
 256                                 if (ram_pointer[j] != test[j])
 257                                         break;
 258                         }
 259
 260                         /* read error */
 261                         if (k != NUM_READS) {
 262                                 break;
 263                         }
 264                 }
 265
 266                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 267                 if (j == NUM_TRIES) {
 268                         if (first_good == -1)
 269                                 first_good = i;         /* found beginning of window */
 270                 } else { /* bad read */
 271                         /* if we have not had a good read then don't care */
 272                         if(first_good != -1) {
 273                                 /* first failure after a good read */
 274                                 last_bad = i-1;
 275                                 break;
 276                         }
 277                 }
 278         }
 279
 280         /* return the current value for TR1 */
 281         *tr1_value = (first_good + last_bad) / 2;
 282 }
 283
 284 void sdram_init(void)
 285 {
 286         register uint reg;
 287         int tr1_bank1, tr1_bank2;
 288
 289         /*--------------------------------------------------------------------
 290          * Setup some default
 291          *------------------------------------------------------------------*/
 292         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 293         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 294         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 295         mtsdram(mem_clktr, 0x40000000); /* ?? */
 296         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 297
 298         /*clear this first, if the DDR is enabled by a debugger
 299           then you can not make changes. */
 300         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 301
 302         /*--------------------------------------------------------------------
 303          * Setup for board-specific specific mem
 304          *------------------------------------------------------------------*/
 305         /*
 306          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 307          */
 308         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 309         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 310
 311         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 312         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 313         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 314         mtsdram(mem_cfg0, 0x30000000);  /* Disable EEC */
 315         udelay(400);            /* Delay 200 usecs (min)            */
 316
 317         /*--------------------------------------------------------------------
 318          * Enable the controller, then wait for DCEN to complete
 319          *------------------------------------------------------------------*/
 320         mtsdram(mem_cfg0, 0x80000000);  /* Enable */
 321
 322         for (;;) {
 323                 mfsdram(mem_mcsts, reg);
 324                 if (reg & 0x80000000)
 325                         break;
 326         }
 327
 328         sdram_tr1_set(0x00000000, &tr1_bank1);
 329         sdram_tr1_set(0x08000000, &tr1_bank2);
 330         mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
 331 }
 332
 333 /*************************************************************************
 334  *  long int initdram
 335  *
 336  ************************************************************************/
 337 long int initdram(int board)
 338 {
 339         sdram_init();
 340         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 341 }
 342
 343 #if defined(CFG_DRAM_TEST)
 344 int testdram(void)
 345 {
 346         unsigned long *mem = (unsigned long *)0;
 347         const unsigned long kend = (1024 / sizeof(unsigned long));
 348         unsigned long k, n;
 349
 350         mtmsr(0);
 351
 352         for (k = 0; k < CFG_KBYTES_SDRAM;
 353              ++k, mem += (1024 / sizeof(unsigned long))) {
 354                 if ((k & 1023) == 0) {
 355                         printf("%3d MB\r", k / 1024);
 356                 }
 357
 358                 memset(mem, 0xaaaaaaaa, 1024);
 359                 for (n = 0; n < kend; ++n) {
 360                         if (mem[n] != 0xaaaaaaaa) {
 361                                 printf("SDRAM test fails at: %08x\n",
 362                                        (uint) & mem[n]);
 363                                 return 1;
 364                         }
 365                 }
 366
 367                 memset(mem, 0x55555555, 1024);
 368                 for (n = 0; n < kend; ++n) {
 369                         if (mem[n] != 0x55555555) {
 370                                 printf("SDRAM test fails at: %08x\n",
 371                                        (uint) & mem[n]);
 372                                 return 1;
 373                         }
 374                 }
 375         }
 376         printf("SDRAM test passes\n");
 377         return 0;
 378 }
 379 #endif
 380
 381 /*************************************************************************
 382  *  pci_pre_init
 383  *
 384  *  This routine is called just prior to registering the hose and gives
 385  *  the board the opportunity to check things. Returning a value of zero
 386  *  indicates that things are bad & PCI initialization should be aborted.
 387  *
 388  *      Different boards may wish to customize the pci controller structure
 389  *      (add regions, override default access routines, etc) or perform
 390  *      certain pre-initialization actions.
 391  *
 392  ************************************************************************/
 393 #if defined(CONFIG_PCI)
 394 int pci_pre_init(struct pci_controller *hose)
 395 {
 396         unsigned long addr;
 397
 398         /*-------------------------------------------------------------------------+
 399           | Set priority for all PLB3 devices to 0.
 400           | Set PLB3 arbiter to fair mode.
 401           +-------------------------------------------------------------------------*/
 402         mfsdr(sdr_amp1, addr);
 403         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 404         addr = mfdcr(plb3_acr);
 405         mtdcr(plb3_acr, addr | 0x80000000);
 406
 407         /*-------------------------------------------------------------------------+
 408           | Set priority for all PLB4 devices to 0.
 409           +-------------------------------------------------------------------------*/
 410         mfsdr(sdr_amp0, addr);
 411         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 412         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 413         mtdcr(plb4_acr, addr);
 414
 415         /*-------------------------------------------------------------------------+
 416           | Set Nebula PLB4 arbiter to fair mode.
 417           +-------------------------------------------------------------------------*/
 418         /* Segment0 */
 419         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 420         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 421         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 422         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 423         mtdcr(plb0_acr, addr);
 424
 425         /* Segment1 */
 426         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 427         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 428         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 429         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 430         mtdcr(plb1_acr, addr);
 431
 432         return 1;
 433 }
 434 #endif  /* defined(CONFIG_PCI) */
 435
 436 /*************************************************************************
 437  *  pci_target_init
 438  *
 439  *      The bootstrap configuration provides default settings for the pci
 440  *      inbound map (PIM). But the bootstrap config choices are limited and
 441  *      may not be sufficient for a given board.
 442  *
 443  ************************************************************************/
 444 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 445 void pci_target_init(struct pci_controller *hose)
 446 {
 447         /*--------------------------------------------------------------------------+
 448          * Set up Direct MMIO registers
 449          *--------------------------------------------------------------------------*/
 450         /*--------------------------------------------------------------------------+
 451           | PowerPC440 EP PCI Master configuration.
 452           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 453           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 454           |   Use byte reversed out routines to handle endianess.
 455           | Make this region non-prefetchable.
 456           +--------------------------------------------------------------------------*/
 457         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 458         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 459         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 460         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 461         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 462
 463         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 464         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 465         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 466         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 467         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 468
 469         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 470         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 471         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 472         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 473
 474         /*--------------------------------------------------------------------------+
 475          * Set up Configuration registers
 476          *--------------------------------------------------------------------------*/
 477
 478         /* Program the board's subsystem id/vendor id */
 479         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 480                               CFG_PCI_SUBSYS_VENDORID);
 481         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 482
 483         /* Configure command register as bus master */
 484         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 485
 486         /* 240nS PCI clock */
 487         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 488
 489         /* No error reporting */
 490         pci_write_config_word(0, PCI_ERREN, 0);
 491
 492         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 493
 494 }
 495 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 496
 497 /*************************************************************************
 498  *  pci_master_init
 499  *
 500  ************************************************************************/
 501 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 502 void pci_master_init(struct pci_controller *hose)
 503 {
 504         unsigned short temp_short;
 505
 506         /*--------------------------------------------------------------------------+
 507           | Write the PowerPC440 EP PCI Configuration regs.
 508           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 509           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 510           +--------------------------------------------------------------------------*/
 511         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 512         pci_write_config_word(0, PCI_COMMAND,
 513                               temp_short | PCI_COMMAND_MASTER |
 514                               PCI_COMMAND_MEMORY);
 515 }
 516 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 517
 518 /*************************************************************************
 519  *  is_pci_host
 520  *
 521  *      This routine is called to determine if a pci scan should be
 522  *      performed. With various hardware environments (especially cPCI and
 523  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 524  *      bit in the strap register, or generic host/adapter assumptions.
 525  *
 526  *      Rather than hard-code a bad assumption in the general 440 code, the
 527  *      440 pci code requires the board to decide at runtime.
 528  *
 529  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 530  *
 531  *
 532  ************************************************************************/
 533 #if defined(CONFIG_PCI)
 534 int is_pci_host(struct pci_controller *hose)
 535 {
 536         /* Bamboo is always configured as host. */
 537         return (1);
 538 }
 539 #endif                          /* defined(CONFIG_PCI) */
 540
 541 /*************************************************************************
 542  *  hw_watchdog_reset
 543  *
 544  *      This routine is called to reset (keep alive) the watchdog timer
 545  *
 546  ************************************************************************/
 547 #if defined(CONFIG_HW_WATCHDOG)
 548 void hw_watchdog_reset(void)
 549 {
 550
 551 }
 552 #endif
 553
 554 void board_reset(void)
 555 {
 556         /* give reset to BCSR */
 557         *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
 558 }
 559
 560 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 561 void ft_board_setup(void *blob, bd_t *bd)
 562 {
 563         u32 val[4];
 564         int rc;
 565
 566         ft_cpu_setup(blob, bd);
 567
 568         /* Fixup NOR mapping */
 569         val[0] = 0;                             /* chip select number */
 570         val[1] = 0;                             /* always 0 */
 571         val[2] = gd->bd->bi_flashstart;
 572         val[3] = gd->bd->bi_flashsize;
 573         rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 574                                   val, sizeof(val), 1);
 575         if (rc)
 576                 printf("Unable to update property NOR mapping, err=%s\n",
 577                        fdt_strerror(rc));
 578 }
 579 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */