board/amcc/yellowstone/yellowstone.c

   1 /*
   2  *
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <ppc4xx.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  30
  31 int board_early_init_f(void)
  32 {
  33         register uint reg;
  34
  35         /*--------------------------------------------------------------------
  36          * Setup the external bus controller/chip selects
  37          *-------------------------------------------------------------------*/
  38         mtdcr(ebccfga, xbcfg);
  39         reg = mfdcr(ebccfgd);
  40         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  41
  42         mtebc(pb0ap, 0x03017300);       /* FLASH/SRAM */
  43         mtebc(pb0cr, 0xfc0da000);       /* BAS=0xfc0 64MB r/w 16-bit */
  44
  45         mtebc(pb1ap, 0x00000000);
  46         mtebc(pb1cr, 0x00000000);
  47
  48         mtebc(pb2ap, 0x04814500);
  49         /*CPLD*/ mtebc(pb2cr, 0x80018000);      /*BAS=0x800 1MB r/w 8-bit */
  50
  51         mtebc(pb3ap, 0x00000000);
  52         mtebc(pb3cr, 0x00000000);
  53
  54         mtebc(pb4ap, 0x00000000);
  55         mtebc(pb4cr, 0x00000000);
  56
  57         mtebc(pb5ap, 0x00000000);
  58         mtebc(pb5cr, 0x00000000);
  59
  60         /*--------------------------------------------------------------------
  61          * Setup the GPIO pins
  62          *-------------------------------------------------------------------*/
  63         /*CPLD cs */
  64         /*setup Address lines for flash size 64Meg. */
  65         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  66         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  67         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  68
  69         /*setup emac */
  70         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  71         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  72         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  73         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  74         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  75
  76         /*UART1 */
  77         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  78         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  79         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  80
  81         /* external interrupts IRQ0...3 */
  82         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  83         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
  84         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  85
  86 #if 0 /* test-only */
  87         /*setup USB 2.0 */
  88         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  89         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  90         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  91         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  92         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  93 #endif
  94
  95         /*--------------------------------------------------------------------
  96          * Setup the interrupt controller polarities, triggers, etc.
  97          *-------------------------------------------------------------------*/
  98         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  99         mtdcr(uic0er, 0x00000000);      /* disable all */
 100         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
 101         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 102         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 103         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 104         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 105
 106         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 107         mtdcr(uic1er, 0x00000000);      /* disable all */
 108         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 109         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 110         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 111         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 112         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 113
 114         /*--------------------------------------------------------------------
 115          * Setup other serial configuration
 116          *-------------------------------------------------------------------*/
 117         mfsdr(sdr_pci0, reg);
 118         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
 119         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 120         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 121
 122         /*clear tmrclk divisor */
 123         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 124
 125         /*enable ethernet */
 126         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 127
 128 #if 0 /* test-only */
 129         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 130         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 131 #endif
 132
 133         /*get rid of flash write protect */
 134         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 135
 136         return 0;
 137 }
 138
 139 int misc_init_r (void)
 140 {
 141         uint pbcr;
 142         int size_val = 0;
 143
 144         /* Re-do sizing to get full correct info */
 145         mtdcr(ebccfga, pb0cr);
 146         pbcr = mfdcr(ebccfgd);
 147         switch (gd->bd->bi_flashsize) {
 148         case 1 << 20:
 149                 size_val = 0;
 150                 break;
 151         case 2 << 20:
 152                 size_val = 1;
 153                 break;
 154         case 4 << 20:
 155                 size_val = 2;
 156                 break;
 157         case 8 << 20:
 158                 size_val = 3;
 159                 break;
 160         case 16 << 20:
 161                 size_val = 4;
 162                 break;
 163         case 32 << 20:
 164                 size_val = 5;
 165                 break;
 166         case 64 << 20:
 167                 size_val = 6;
 168                 break;
 169         case 128 << 20:
 170                 size_val = 7;
 171                 break;
 172         }
 173         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 174         mtdcr(ebccfga, pb0cr);
 175         mtdcr(ebccfgd, pbcr);
 176
 177         /* adjust flash start and offset */
 178         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 179         gd->bd->bi_flashoffset = 0;
 180
 181         /* Monitor protection ON by default */
 182         (void)flash_protect(FLAG_PROTECT_SET,
 183                             -CFG_MONITOR_LEN,
 184                             0xffffffff,
 185                             &flash_info[0]);
 186
 187         return 0;
 188 }
 189
 190 int checkboard(void)
 191 {
 192         char *s = getenv("serial#");
 193
 194         printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 195         if (s != NULL) {
 196                 puts(", serial# ");
 197                 puts(s);
 198         }
 199         putc('\n');
 200
 201         return (0);
 202 }
 203
 204 /*************************************************************************
 205  *  sdram_init -- doesn't use serial presence detect.
 206  *
 207  *  Assumes:    256 MB, ECC, non-registered
 208  *              PLB @ 133 MHz
 209  *
 210  ************************************************************************/
 211 #define NUM_TRIES 64
 212 #define NUM_READS 10
 213
 214 void sdram_tr1_set(int ram_address, int* tr1_value)
 215 {
 216         int i;
 217         int j, k;
 218         volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 219         int first_good = -1, last_bad = 0x1ff;
 220
 221         unsigned long test[NUM_TRIES] = {
 222                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 223                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 224                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 225                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 226                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 227                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 228                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 229                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 230                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 231                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 232                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 233                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 234                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 235                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 236                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 237                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 238
 239         /* go through all possible SDRAM0_TR1[RDCT] values */
 240         for (i=0; i<=0x1ff; i++) {
 241                 /* set the current value for TR1 */
 242                 mtsdram(mem_tr1, (0x80800800 | i));
 243
 244                 /* write values */
 245                 for (j=0; j<NUM_TRIES; j++) {
 246                         ram_pointer[j] = test[j];
 247
 248                         /* clear any cache at ram location */
 249                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 250                 }
 251
 252                 /* read values back */
 253                 for (j=0; j<NUM_TRIES; j++) {
 254                         for (k=0; k<NUM_READS; k++) {
 255                                 /* clear any cache at ram location */
 256                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 257
 258                                 if (ram_pointer[j] != test[j])
 259                                         break;
 260                         }
 261
 262                         /* read error */
 263                         if (k != NUM_READS) {
 264                                 break;
 265                         }
 266                 }
 267
 268                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 269                 if (j == NUM_TRIES) {
 270                         if (first_good == -1)
 271                                 first_good = i;         /* found beginning of window */
 272                 } else { /* bad read */
 273                         /* if we have not had a good read then don't care */
 274                         if(first_good != -1) {
 275                                 /* first failure after a good read */
 276                                 last_bad = i-1;
 277                                 break;
 278                         }
 279                 }
 280         }
 281
 282         /* return the current value for TR1 */
 283         *tr1_value = (first_good + last_bad) / 2;
 284 }
 285
 286 void sdram_init(void)
 287 {
 288         register uint reg;
 289         int tr1_bank1, tr1_bank2;
 290
 291         /*--------------------------------------------------------------------
 292          * Setup some default
 293          *------------------------------------------------------------------*/
 294         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 295         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 296         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 297         mtsdram(mem_clktr, 0x40000000); /* ?? */
 298         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 299
 300         /*clear this first, if the DDR is enabled by a debugger
 301           then you can not make changes. */
 302         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 303
 304         /*--------------------------------------------------------------------
 305          * Setup for board-specific specific mem
 306          *------------------------------------------------------------------*/
 307         /*
 308          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 309          */
 310         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 311         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 312
 313         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 314         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 315         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 316         mtsdram(mem_cfg0, 0x34000000);  /* Disable EEC */
 317         udelay(400);            /* Delay 200 usecs (min)            */
 318
 319         /*--------------------------------------------------------------------
 320          * Enable the controller, then wait for DCEN to complete
 321          *------------------------------------------------------------------*/
 322         mtsdram(mem_cfg0, 0x84000000);  /* Enable */
 323
 324         for (;;) {
 325                 mfsdram(mem_mcsts, reg);
 326                 if (reg & 0x80000000)
 327                         break;
 328         }
 329
 330         sdram_tr1_set(0x00000000, &tr1_bank1);
 331         sdram_tr1_set(0x08000000, &tr1_bank2);
 332         mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
 333 }
 334
 335 /*************************************************************************
 336  *  long int initdram
 337  *
 338  ************************************************************************/
 339 long int initdram(int board)
 340 {
 341         sdram_init();
 342         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 343 }
 344
 345 #if defined(CFG_DRAM_TEST)
 346 int testdram(void)
 347 {
 348         unsigned long *mem = (unsigned long *)0;
 349         const unsigned long kend = (1024 / sizeof(unsigned long));
 350         unsigned long k, n;
 351
 352         mtmsr(0);
 353
 354         for (k = 0; k < CFG_KBYTES_SDRAM;
 355              ++k, mem += (1024 / sizeof(unsigned long))) {
 356                 if ((k & 1023) == 0) {
 357                         printf("%3d MB\r", k / 1024);
 358                 }
 359
 360                 memset(mem, 0xaaaaaaaa, 1024);
 361                 for (n = 0; n < kend; ++n) {
 362                         if (mem[n] != 0xaaaaaaaa) {
 363                                 printf("SDRAM test fails at: %08x\n",
 364                                        (uint) & mem[n]);
 365                                 return 1;
 366                         }
 367                 }
 368
 369                 memset(mem, 0x55555555, 1024);
 370                 for (n = 0; n < kend; ++n) {
 371                         if (mem[n] != 0x55555555) {
 372                                 printf("SDRAM test fails at: %08x\n",
 373                                        (uint) & mem[n]);
 374                                 return 1;
 375                         }
 376                 }
 377         }
 378         printf("SDRAM test passes\n");
 379         return 0;
 380 }
 381 #endif
 382
 383 /*************************************************************************
 384  *  pci_pre_init
 385  *
 386  *  This routine is called just prior to registering the hose and gives
 387  *  the board the opportunity to check things. Returning a value of zero
 388  *  indicates that things are bad & PCI initialization should be aborted.
 389  *
 390  *      Different boards may wish to customize the pci controller structure
 391  *      (add regions, override default access routines, etc) or perform
 392  *      certain pre-initialization actions.
 393  *
 394  ************************************************************************/
 395 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 396 int pci_pre_init(struct pci_controller *hose)
 397 {
 398         unsigned long addr;
 399
 400         /*-------------------------------------------------------------------------+
 401           | Set priority for all PLB3 devices to 0.
 402           | Set PLB3 arbiter to fair mode.
 403           +-------------------------------------------------------------------------*/
 404         mfsdr(sdr_amp1, addr);
 405         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 406         addr = mfdcr(plb3_acr);
 407         mtdcr(plb3_acr, addr | 0x80000000);
 408
 409         /*-------------------------------------------------------------------------+
 410           | Set priority for all PLB4 devices to 0.
 411           +-------------------------------------------------------------------------*/
 412         mfsdr(sdr_amp0, addr);
 413         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 414         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 415         mtdcr(plb4_acr, addr);
 416
 417         /*-------------------------------------------------------------------------+
 418           | Set Nebula PLB4 arbiter to fair mode.
 419           +-------------------------------------------------------------------------*/
 420         /* Segment0 */
 421         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 422         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 423         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 424         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 425         mtdcr(plb0_acr, addr);
 426
 427         /* Segment1 */
 428         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 429         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 430         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 431         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 432         mtdcr(plb1_acr, addr);
 433
 434         return 1;
 435 }
 436 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 437
 438 /*************************************************************************
 439  *  pci_target_init
 440  *
 441  *      The bootstrap configuration provides default settings for the pci
 442  *      inbound map (PIM). But the bootstrap config choices are limited and
 443  *      may not be sufficient for a given board.
 444  *
 445  ************************************************************************/
 446 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 447 void pci_target_init(struct pci_controller *hose)
 448 {
 449         /*--------------------------------------------------------------------------+
 450          * Set up Direct MMIO registers
 451          *--------------------------------------------------------------------------*/
 452         /*--------------------------------------------------------------------------+
 453           | PowerPC440 EP PCI Master configuration.
 454           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 455           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 456           |   Use byte reversed out routines to handle endianess.
 457           | Make this region non-prefetchable.
 458           +--------------------------------------------------------------------------*/
 459         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 460         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 461         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 462         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 463         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 464
 465         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 466         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 467         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 468         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 469         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 470
 471         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 472         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 473         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 474         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 475
 476         /*--------------------------------------------------------------------------+
 477          * Set up Configuration registers
 478          *--------------------------------------------------------------------------*/
 479
 480         /* Program the board's subsystem id/vendor id */
 481         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 482                               CFG_PCI_SUBSYS_VENDORID);
 483         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 484
 485         /* Configure command register as bus master */
 486         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 487
 488         /* 240nS PCI clock */
 489         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 490
 491         /* No error reporting */
 492         pci_write_config_word(0, PCI_ERREN, 0);
 493
 494         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 495
 496 }
 497 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 498
 499 /*************************************************************************
 500  *  pci_master_init
 501  *
 502  ************************************************************************/
 503 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 504 void pci_master_init(struct pci_controller *hose)
 505 {
 506         unsigned short temp_short;
 507
 508         /*--------------------------------------------------------------------------+
 509           | Write the PowerPC440 EP PCI Configuration regs.
 510           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 511           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 512           +--------------------------------------------------------------------------*/
 513         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 514         pci_write_config_word(0, PCI_COMMAND,
 515                               temp_short | PCI_COMMAND_MASTER |
 516                               PCI_COMMAND_MEMORY);
 517 }
 518 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 519
 520 /*************************************************************************
 521  *  is_pci_host
 522  *
 523  *      This routine is called to determine if a pci scan should be
 524  *      performed. With various hardware environments (especially cPCI and
 525  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 526  *      bit in the strap register, or generic host/adapter assumptions.
 527  *
 528  *      Rather than hard-code a bad assumption in the general 440 code, the
 529  *      440 pci code requires the board to decide at runtime.
 530  *
 531  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 532  *
 533  *
 534  ************************************************************************/
 535 #if defined(CONFIG_PCI)
 536 int is_pci_host(struct pci_controller *hose)
 537 {
 538         /* Bamboo is always configured as host. */
 539         return (1);
 540 }
 541 #endif                          /* defined(CONFIG_PCI) */
 542
 543 /*************************************************************************
 544  *  hw_watchdog_reset
 545  *
 546  *      This routine is called to reset (keep alive) the watchdog timer
 547  *
 548  ************************************************************************/
 549 #if defined(CONFIG_HW_WATCHDOG)
 550 void hw_watchdog_reset(void)
 551 {
 552
 553 }
 554 #endif