2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <spd_sdram.h>
28 int board_early_init_f(void)
30 /*-------------------------------------------------------------------------+
31 | Interrupt controller setup for the Walnut/Sycamore board.
32 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
33 | IRQ 16 405GP internally generated; active low; level sensitive
35 | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
36 | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
37 | IRQ 27 (EXT IRQ 2) Not Used
38 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
39 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
40 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
41 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
42 | Note for Walnut board:
43 | An interrupt taken for the FPGA (IRQ 25) indicates that either
44 | the Mouse, Keyboard, IRDA, or External Expansion caused the
45 | interrupt. The FPGA must be read to determine which device
46 | caused the interrupt. The default setting of the FPGA clears
48 +-------------------------------------------------------------------------*/
50 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
51 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
52 mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
53 mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
54 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
55 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
56 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
58 /* set UART1 control to select CTS/RTS */
59 #define FPGA_BRDC 0xF0300004
60 *(volatile char *)(FPGA_BRDC) |= 0x1;
66 * Check Board Identity:
70 char *s = getenv("serial#");
73 if (pvr == PVR_405GPR_RB) {
74 puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
76 puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
89 * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
90 * the necessary info for SDRAM controller configuration
92 phys_size_t initdram(int board_type)