board/amcc/sequoia/sequoia.c

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/processor.h>
  27 #include <ppc440.h>
  28 #include "sequoia.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  33
  34 ulong flash_get_size (ulong base, int banknum);
  35
  36 int board_early_init_f(void)
  37 {
  38         u32 sdr0_cust0;
  39         u32 sdr0_pfc1, sdr0_pfc2;
  40         u32 reg;
  41
  42         mtdcr(ebccfga, xbcfg);
  43         mtdcr(ebccfgd, 0xb8400000);
  44
  45         /*--------------------------------------------------------------------
  46          * Setup the GPIO pins
  47          *-------------------------------------------------------------------*/
  48         /* test-only: take GPIO init from pcs440ep ???? in config file */
  49         out32(GPIO0_OR, 0x00000000);
  50         out32(GPIO0_TCR, 0x0000000f);
  51         out32(GPIO0_OSRL, 0x50015400);
  52         out32(GPIO0_OSRH, 0x550050aa);
  53         out32(GPIO0_TSRL, 0x50015400);
  54         out32(GPIO0_TSRH, 0x55005000);
  55         out32(GPIO0_ISR1L, 0x50000000);
  56         out32(GPIO0_ISR1H, 0x00000000);
  57         out32(GPIO0_ISR2L, 0x00000000);
  58         out32(GPIO0_ISR2H, 0x00000100);
  59         out32(GPIO0_ISR3L, 0x00000000);
  60         out32(GPIO0_ISR3H, 0x00000000);
  61
  62         out32(GPIO1_OR, 0x00000000);
  63         out32(GPIO1_TCR, 0xc2000000);
  64         out32(GPIO1_OSRL, 0x5c280000);
  65         out32(GPIO1_OSRH, 0x00000000);
  66         out32(GPIO1_TSRL, 0x0c000000);
  67         out32(GPIO1_TSRH, 0x00000000);
  68         out32(GPIO1_ISR1L, 0x00005550);
  69         out32(GPIO1_ISR1H, 0x00000000);
  70         out32(GPIO1_ISR2L, 0x00050000);
  71         out32(GPIO1_ISR2H, 0x00000000);
  72         out32(GPIO1_ISR3L, 0x01400000);
  73         out32(GPIO1_ISR3H, 0x00000000);
  74
  75         /*--------------------------------------------------------------------
  76          * Setup the interrupt controller polarities, triggers, etc.
  77          *-------------------------------------------------------------------*/
  78         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  79         mtdcr(uic0er, 0x00000000);      /* disable all */
  80         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
  81         mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
  82         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
  83         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
  84         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  85
  86         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  87         mtdcr(uic1er, 0x00000000);      /* disable all */
  88         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  89         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
  90         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
  91         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
  92         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  93
  94         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  95         mtdcr(uic2er, 0x00000000);      /* disable all */
  96         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
  97         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
  98         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
  99         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
 100         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 101
 102         /* 50MHz tmrclk */
 103         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 104
 105         /* clear write protects */
 106         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 107
 108         /* enable Ethernet */
 109         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
 110
 111         /* enable USB device */
 112         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
 113
 114         /* select Ethernet pins */
 115         mfsdr(SDR0_PFC1, sdr0_pfc1);
 116         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
 117         mfsdr(SDR0_PFC2, sdr0_pfc2);
 118         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
 119         mtsdr(SDR0_PFC2, sdr0_pfc2);
 120         mtsdr(SDR0_PFC1, sdr0_pfc1);
 121
 122         /* PCI arbiter enabled */
 123         mfsdr(sdr_pci0, reg);
 124         mtsdr(sdr_pci0, 0x80000000 | reg);
 125
 126         /* setup NAND FLASH */
 127         mfsdr(SDR0_CUST0, sdr0_cust0);
 128         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 129                 SDR0_CUST0_NDFC_ENABLE          |
 130                 SDR0_CUST0_NDFC_BW_8_BIT        |
 131                 SDR0_CUST0_NDFC_ARE_MASK        |
 132                 (0x80000000 >> (28 + CFG_NAND_CS));
 133         mtsdr(SDR0_CUST0, sdr0_cust0);
 134
 135         return 0;
 136 }
 137
 138 /*---------------------------------------------------------------------------+
 139   | misc_init_r.
 140   +---------------------------------------------------------------------------*/
 141 int misc_init_r(void)
 142 {
 143         uint pbcr;
 144         int size_val = 0;
 145         u32 reg;
 146 #ifdef CONFIG_440EPX
 147         unsigned long usb2d0cr = 0;
 148         unsigned long usb2phy0cr, usb2h0cr = 0;
 149         unsigned long sdr0_pfc1;
 150         char *act = getenv("usbact");
 151 #endif
 152
 153         /*
 154          * FLASH stuff...
 155          */
 156
 157         /* Re-do sizing to get full correct info */
 158
 159         /* adjust flash start and offset */
 160         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 161         gd->bd->bi_flashoffset = 0;
 162
 163 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 164         mtdcr(ebccfga, pb3cr);
 165 #else
 166         mtdcr(ebccfga, pb0cr);
 167 #endif
 168         pbcr = mfdcr(ebccfgd);
 169         switch (gd->bd->bi_flashsize) {
 170         case 1 << 20:
 171                 size_val = 0;
 172                 break;
 173         case 2 << 20:
 174                 size_val = 1;
 175                 break;
 176         case 4 << 20:
 177                 size_val = 2;
 178                 break;
 179         case 8 << 20:
 180                 size_val = 3;
 181                 break;
 182         case 16 << 20:
 183                 size_val = 4;
 184                 break;
 185         case 32 << 20:
 186                 size_val = 5;
 187                 break;
 188         case 64 << 20:
 189                 size_val = 6;
 190                 break;
 191         case 128 << 20:
 192                 size_val = 7;
 193                 break;
 194         }
 195         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 196 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 197         mtdcr(ebccfga, pb3cr);
 198 #else
 199         mtdcr(ebccfga, pb0cr);
 200 #endif
 201         mtdcr(ebccfgd, pbcr);
 202
 203         /*
 204          * Re-check to get correct base address
 205          */
 206         flash_get_size(gd->bd->bi_flashstart, 0);
 207
 208 #ifdef CFG_ENV_IS_IN_FLASH
 209         /* Monitor protection ON by default */
 210         (void)flash_protect(FLAG_PROTECT_SET,
 211                             -CFG_MONITOR_LEN,
 212                             0xffffffff,
 213                             &flash_info[0]);
 214
 215         /* Env protection ON by default */
 216         (void)flash_protect(FLAG_PROTECT_SET,
 217                             CFG_ENV_ADDR_REDUND,
 218                             CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
 219                             &flash_info[0]);
 220 #endif
 221
 222         /*
 223          * USB suff...
 224          */
 225 #ifdef CONFIG_440EPX
 226         if (act == NULL || strcmp(act, "hostdev") == 0) {
 227                 /* SDR Setting */
 228                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 229                 mfsdr(SDR0_USB0, usb2d0cr);
 230                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 231                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 232
 233                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 234                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 235                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 236                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1*/
 237                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 238                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 239                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 240                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 241                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 242                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 243
 244                 /* An 8-bit/60MHz interface is the only possible alternative
 245                    when connecting the Device to the PHY */
 246                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 247                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;        /*1*/
 248
 249                 /* To enable the USB 2.0 Device function through the UTMI interface */
 250                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 251                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;          /*1*/
 252
 253                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 254                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;                /*0*/
 255
 256                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 257                 mtsdr(SDR0_USB0, usb2d0cr);
 258                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 259                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 260
 261                 /*clear resets*/
 262                 udelay (1000);
 263                 mtsdr(SDR0_SRST1, 0x00000000);
 264                 udelay (1000);
 265                 mtsdr(SDR0_SRST0, 0x00000000);
 266
 267                 printf("USB:   Host(int phy) Device(ext phy)\n");
 268
 269         } else if (strcmp(act, "dev") == 0) {
 270                 /*-------------------PATCH-------------------------------*/
 271                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 272
 273                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 274                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 275                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 276                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 277                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 278                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 279                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 280                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 281                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 282
 283                 udelay (1000);
 284                 mtsdr(SDR0_SRST1, 0x672c6000);
 285
 286                 udelay (1000);
 287                 mtsdr(SDR0_SRST0, 0x00000080);
 288
 289                 udelay (1000);
 290                 mtsdr(SDR0_SRST1, 0x60206000);
 291
 292                 *(unsigned int *)(0xe0000350) = 0x00000001;
 293
 294                 udelay (1000);
 295                 mtsdr(SDR0_SRST1, 0x60306000);
 296                 /*-------------------PATCH-------------------------------*/
 297
 298                 /* SDR Setting */
 299                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 300                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 301                 mfsdr(SDR0_USB0, usb2d0cr);
 302                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 303
 304                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 305                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 306                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 307                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;     /*0*/
 308                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 309                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;          /*1*/
 310                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 311                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;           /*0*/
 312                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 313                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;           /*0*/
 314
 315                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 316                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;         /*0*/
 317
 318                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 319                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;              /*0*/
 320
 321                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 322                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;                /*1*/
 323
 324                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 325                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 326                 mtsdr(SDR0_USB0, usb2d0cr);
 327                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 328
 329                 /*clear resets*/
 330                 udelay (1000);
 331                 mtsdr(SDR0_SRST1, 0x00000000);
 332                 udelay (1000);
 333                 mtsdr(SDR0_SRST0, 0x00000000);
 334
 335                 printf("USB:   Device(int phy)\n");
 336         }
 337 #endif /* CONFIG_440EPX */
 338
 339         mfsdr(SDR0_SRST1, reg);         /* enable security/kasumi engines */
 340         reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
 341         mtsdr(SDR0_SRST1, reg);
 342
 343         /*
 344          * Clear PLB4A0_ACR[WRP]
 345          * This fix will make the MAL burst disabling patch for the Linux
 346          * EMAC driver obsolete.
 347          */
 348         reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
 349         mtdcr(plb4_acr, reg);
 350
 351         return 0;
 352 }
 353
 354 int checkboard(void)
 355 {
 356         char *s = getenv("serial#");
 357         u8 rev;
 358         u8 val;
 359
 360 #ifdef CONFIG_440EPX
 361         printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
 362 #else
 363         printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 364 #endif
 365
 366         rev = *(u8 *)(CFG_BCSR_BASE + 0);
 367         val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
 368         printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 369
 370         if (s != NULL) {
 371                 puts(", serial# ");
 372                 puts(s);
 373         }
 374         putc('\n');
 375
 376         return (0);
 377 }
 378
 379 #if defined(CFG_DRAM_TEST)
 380 int testdram(void)
 381 {
 382         unsigned long *mem = (unsigned long *)0;
 383         const unsigned long kend = (1024 / sizeof(unsigned long));
 384         unsigned long k, n;
 385
 386         mtmsr(0);
 387
 388         for (k = 0; k < CFG_MBYTES_SDRAM;
 389              ++k, mem += (1024 / sizeof(unsigned long))) {
 390                 if ((k & 1023) == 0) {
 391                         printf("%3d MB\r", k / 1024);
 392                 }
 393
 394                 memset(mem, 0xaaaaaaaa, 1024);
 395                 for (n = 0; n < kend; ++n) {
 396                         if (mem[n] != 0xaaaaaaaa) {
 397                                 printf("SDRAM test fails at: %08x\n",
 398                                        (uint) & mem[n]);
 399                                 return 1;
 400                         }
 401                 }
 402
 403                 memset(mem, 0x55555555, 1024);
 404                 for (n = 0; n < kend; ++n) {
 405                         if (mem[n] != 0x55555555) {
 406                                 printf("SDRAM test fails at: %08x\n",
 407                                        (uint) & mem[n]);
 408                                 return 1;
 409                         }
 410                 }
 411         }
 412         printf("SDRAM test passes\n");
 413         return 0;
 414 }
 415 #endif
 416
 417 /*************************************************************************
 418  *  pci_pre_init
 419  *
 420  *  This routine is called just prior to registering the hose and gives
 421  *  the board the opportunity to check things. Returning a value of zero
 422  *  indicates that things are bad & PCI initialization should be aborted.
 423  *
 424  *      Different boards may wish to customize the pci controller structure
 425  *      (add regions, override default access routines, etc) or perform
 426  *      certain pre-initialization actions.
 427  *
 428  ************************************************************************/
 429 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 430 int pci_pre_init(struct pci_controller *hose)
 431 {
 432         unsigned long addr;
 433 #if 0
 434         /*--------------------------------------------------------------------------+
 435          *      Cactus is always configured as the host & requires the
 436          *      PCI arbiter to be enabled ???
 437          *--------------------------------------------------------------------------*/
 438         unsigned long strap;
 439         mfsdr(sdr_sdstp1, strap);
 440         if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 441                 printf("PCI: SDR0_STRP1[PAE] not set.\n");
 442                 printf("PCI: Configuration aborted.\n");
 443                 return 0;
 444         }
 445 #endif
 446
 447         /*-------------------------------------------------------------------------+
 448           | Set priority for all PLB3 devices to 0.
 449           | Set PLB3 arbiter to fair mode.
 450           +-------------------------------------------------------------------------*/
 451         mfsdr(sdr_amp1, addr);
 452         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 453         addr = mfdcr(plb3_acr);
 454         mtdcr(plb3_acr, addr | 0x80000000);
 455
 456         /*-------------------------------------------------------------------------+
 457           | Set priority for all PLB4 devices to 0.
 458           +-------------------------------------------------------------------------*/
 459         mfsdr(sdr_amp0, addr);
 460         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 461         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 462         mtdcr(plb4_acr, addr);
 463
 464         /*-------------------------------------------------------------------------+
 465           | Set Nebula PLB4 arbiter to fair mode.
 466           +-------------------------------------------------------------------------*/
 467         /* Segment0 */
 468         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 469         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 470         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 471         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 472         mtdcr(plb0_acr, addr);
 473
 474         /* Segment1 */
 475         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 476         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 477         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 478         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 479         mtdcr(plb1_acr, addr);
 480
 481         return 1;
 482 }
 483 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 484
 485 /*************************************************************************
 486  *  pci_target_init
 487  *
 488  *      The bootstrap configuration provides default settings for the pci
 489  *      inbound map (PIM). But the bootstrap config choices are limited and
 490  *      may not be sufficient for a given board.
 491  *
 492  ************************************************************************/
 493 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 494 void pci_target_init(struct pci_controller *hose)
 495 {
 496         /*--------------------------------------------------------------------------+
 497          * Set up Direct MMIO registers
 498          *--------------------------------------------------------------------------*/
 499         /*--------------------------------------------------------------------------+
 500           | PowerPC440EPX PCI Master configuration.
 501           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 502           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 503           |   Use byte reversed out routines to handle endianess.
 504           | Make this region non-prefetchable.
 505           +--------------------------------------------------------------------------*/
 506         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 507         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 508         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 509         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 510         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 511
 512         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 513         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 514         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 515         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 516         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 517
 518         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 519         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 520         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 521         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 522
 523         /*--------------------------------------------------------------------------+
 524          * Set up Configuration registers
 525          *--------------------------------------------------------------------------*/
 526
 527         /* Program the board's subsystem id/vendor id */
 528         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 529                               CFG_PCI_SUBSYS_VENDORID);
 530         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 531
 532         /* Configure command register as bus master */
 533         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 534
 535         /* 240nS PCI clock */
 536         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 537
 538         /* No error reporting */
 539         pci_write_config_word(0, PCI_ERREN, 0);
 540
 541         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 542
 543 }
 544 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 545
 546 /*************************************************************************
 547  *  pci_master_init
 548  *
 549  ************************************************************************/
 550 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 551 void pci_master_init(struct pci_controller *hose)
 552 {
 553         unsigned short temp_short;
 554
 555         /*--------------------------------------------------------------------------+
 556           | Write the PowerPC440 EP PCI Configuration regs.
 557           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 558           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 559           +--------------------------------------------------------------------------*/
 560         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 561         pci_write_config_word(0, PCI_COMMAND,
 562                               temp_short | PCI_COMMAND_MASTER |
 563                               PCI_COMMAND_MEMORY);
 564 }
 565 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 566
 567 /*************************************************************************
 568  *  is_pci_host
 569  *
 570  *      This routine is called to determine if a pci scan should be
 571  *      performed. With various hardware environments (especially cPCI and
 572  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 573  *      bit in the strap register, or generic host/adapter assumptions.
 574  *
 575  *      Rather than hard-code a bad assumption in the general 440 code, the
 576  *      440 pci code requires the board to decide at runtime.
 577  *
 578  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 579  *
 580  *
 581  ************************************************************************/
 582 #if defined(CONFIG_PCI)
 583 int is_pci_host(struct pci_controller *hose)
 584 {
 585         /* Cactus is always configured as host. */
 586         return (1);
 587 }
 588 #endif                          /* defined(CONFIG_PCI) */