3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * There are 2 versions of production Sequoia & Rainier platforms.
32 * The primary difference is the reference clock. Those with
33 * 33333333 reference clocks will also have 667MHz rated
34 * processors. Not enough differences to have unique clock
37 * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
38 * values are independent of the rest of the clock settings.
40 * All Sequoias & Rainiers select from two possible EEPROMs in Boot
41 * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
42 * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
43 * the only value affected for a 66MHz PCI and simply needs a +0x10.
46 #define NAND_COMPATIBLE 0x01
47 #define NOR_COMPATIBLE 0x02
49 /* check with Stefan on CFG_I2C_EEPROM_ADDR */
50 #define I2C_EEPROM_ADDR 0x52
52 static char *config_labels[] = {
53 "CPU: 333 PLB: 133 OPB: 66 EBC: 66",
54 "CPU: 333 PLB: 166 OPB: 83 EBC: 55",
55 "CPU: 400 PLB: 133 OPB: 66 EBC: 66",
56 "CPU: 400 PLB: 160 OPB: 80 EBC: 53",
57 "CPU: 416 PLB: 166 OPB: 83 EBC: 55",
58 "CPU: 500 PLB: 166 OPB: 83 EBC: 55",
59 "CPU: 533 PLB: 133 OPB: 66 EBC: 66",
60 "CPU: 667 PLB: 166 OPB: 83 EBC: 55",
64 static u8 boot_configs[][17] = {
67 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
68 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
71 (NAND_COMPATIBLE | NOR_COMPATIBLE),
72 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
73 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
77 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
78 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
82 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
83 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
86 (NAND_COMPATIBLE | NOR_COMPATIBLE),
87 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
88 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
91 (NAND_COMPATIBLE | NOR_COMPATIBLE),
92 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
93 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
97 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
98 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
101 (NAND_COMPATIBLE | NOR_COMPATIBLE),
102 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
103 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
107 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
112 * Bytes 6,8,9,11 change for NAND boot
114 static u8 nand_boot[] = {
115 0xd0, 0xa0, 0x68, 0x58
118 static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
121 int x, y, nbytes, selcfg;
122 extern char console_buffer[];
125 printf("Usage:\n%s\n", cmdtp->usage);
129 if ((strcmp(argv[1], "nor") != 0) &&
130 (strcmp(argv[1], "nand") != 0)) {
131 printf("Unsupported boot-device - only nor|nand support\n");
135 /* set the nand flag based on provided input */
136 if ((strcmp(argv[1], "nand") == 0))
141 printf("Available configurations: \n\n");
144 for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
145 /* filter on nand compatible */
146 if (boot_configs[x][0] & NAND_COMPATIBLE) {
147 printf(" %d - %s\n", (y+1), config_labels[x]);
152 for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
153 /* filter on nor compatible */
154 if (boot_configs[x][0] & NOR_COMPATIBLE) {
155 printf(" %d - %s\n", (y+1), config_labels[x]);
162 nbytes = readline(" Selection [1-x / quit]: ");
165 if (strcmp(console_buffer, "quit") == 0)
167 selcfg = simple_strtol(console_buffer, NULL, 10);
168 if ((selcfg < 1) || (selcfg > y))
171 } while (nbytes == 0);
176 for (x = 0; boot_configs[x][0] != 0; x++) {
178 if (boot_configs[x][0] & NAND_COMPATIBLE) {
185 if (boot_configs[x][0] & NOR_COMPATIBLE) {
194 buf = &boot_configs[x][1];
197 buf[6] = nand_boot[0];
198 buf[8] = nand_boot[1];
199 buf[9] = nand_boot[2];
200 buf[11] = nand_boot[3];
203 /* check CPLD register +5 for PCI 66MHz flag */
204 if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
206 * PLB-to-PCI divisor = 3 for 33MHz sync PCI
207 * instead of 2 for 66MHz systems
211 if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
212 printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
213 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
216 printf("Please power-cycle the board for the changes to take effect\n");
222 bootstrap, 2, 0, do_bootstrap,
223 "bootstrap - program the I2C bootstrap EEPROM\n",
224 "<nand|nor> - strap to boot from NAND or NOR flash\n"