3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * There are 2 versions of production Sequoia & Rainier platforms.
31 * The primary difference is the reference clock. Those with
32 * 33333333 reference clocks will also have 667MHz rated
33 * processors. Not enough differences to have unique clock
36 * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
37 * values are independent of the rest of the clock settings.
39 * All Sequoias & Rainiers select from two possible EEPROMs in Boot
40 * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
41 * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
42 * the only value affected for a 66MHz PCI and simply needs a +0x10.
45 #define NAND_COMPATIBLE 0x01
46 #define NOR_COMPATIBLE 0x02
48 /* check with Stefan on CFG_I2C_EEPROM_ADDR */
49 #define I2C_EEPROM_ADDR 0x52
51 static char *config_labels[] = {
52 "CPU: 333 PLB: 133 OPB: 66 EBC: 66",
53 "CPU: 333 PLB: 166 OPB: 83 EBC: 55",
54 "CPU: 400 PLB: 133 OPB: 66 EBC: 66",
55 "CPU: 400 PLB: 160 OPB: 80 EBC: 53",
56 "CPU: 416 PLB: 166 OPB: 83 EBC: 55",
57 "CPU: 500 PLB: 166 OPB: 83 EBC: 55",
58 "CPU: 533 PLB: 133 OPB: 66 EBC: 66",
59 "CPU: 667 PLB: 166 OPB: 83 EBC: 55",
63 static u8 boot_configs[][17] = {
66 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
67 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
70 (NAND_COMPATIBLE | NOR_COMPATIBLE),
71 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
72 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
76 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
77 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
81 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
82 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
85 (NAND_COMPATIBLE | NOR_COMPATIBLE),
86 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
87 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
90 (NAND_COMPATIBLE | NOR_COMPATIBLE),
91 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
92 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
96 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
97 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
100 (NAND_COMPATIBLE | NOR_COMPATIBLE),
101 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
102 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
106 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
111 * Bytes 6,8,9,11 change for NAND boot
113 static u8 nand_boot[] = {
114 0xd0, 0xa0, 0x68, 0x58
117 static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
120 int x, y, nbytes, selcfg;
121 extern char console_buffer[];
124 printf("Usage:\n%s\n", cmdtp->usage);
128 if ((strcmp(argv[1], "nor") != 0) &&
129 (strcmp(argv[1], "nand") != 0)) {
130 printf("Unsupported boot-device - only nor|nand support\n");
134 /* set the nand flag based on provided input */
135 if ((strcmp(argv[1], "nand") == 0))
140 printf("Available configurations: \n\n");
143 for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
144 /* filter on nand compatible */
145 if (boot_configs[x][0] & NAND_COMPATIBLE) {
146 printf(" %d - %s\n", (y+1), config_labels[x]);
151 for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
152 /* filter on nor compatible */
153 if (boot_configs[x][0] & NOR_COMPATIBLE) {
154 printf(" %d - %s\n", (y+1), config_labels[x]);
161 nbytes = readline(" Selection [1-x / quit]: ");
164 if (strcmp(console_buffer, "quit") == 0)
166 selcfg = simple_strtol(console_buffer, NULL, 10);
167 if ((selcfg < 1) || (selcfg > y))
170 } while (nbytes == 0);
175 for (x = 0; boot_configs[x][0] != 0; x++) {
177 if (boot_configs[x][0] & NAND_COMPATIBLE) {
184 if (boot_configs[x][0] & NOR_COMPATIBLE) {
193 buf = &boot_configs[x][1];
196 buf[6] = nand_boot[0];
197 buf[8] = nand_boot[1];
198 buf[9] = nand_boot[2];
199 buf[11] = nand_boot[3];
202 /* check CPLD register +5 for PCI 66MHz flag */
203 if (in8(CFG_BCSR_BASE + 5) & 0x01)
206 if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
207 printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
208 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
211 printf("Please power-cycle the board for the changes to take effect\n");
217 bootstrap, 2, 0, do_bootstrap,
218 "bootstrap - program the I2C bootstrap EEPROM\n",
219 "<nand|nor> - strap to boot from NAND or NOR flash\n"