Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
[platform/kernel/u-boot.git] / board / amcc / ocotea / ocotea.c
1 /*
2  *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
3  *
4  * (C) Copyright 2005
5  * Stefan Roese, DENX Software Engineering, sr@denx.de.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26
27 #include <common.h>
28 #include "ocotea.h"
29 #include <asm/processor.h>
30 #include <spd_sdram.h>
31 #include <ppc4xx_enet.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define BOOT_SMALL_FLASH        32      /* 00100000 */
36 #define FLASH_ONBD_N            2       /* 00000010 */
37 #define FLASH_SRAM_SEL          1       /* 00000001 */
38
39 long int fixed_sdram (void);
40 void fpga_init (void);
41
42 int board_early_init_f (void)
43 {
44         unsigned long mfr;
45         unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
46         unsigned char switch_status;
47         unsigned long cs0_base;
48         unsigned long cs0_size;
49         unsigned long cs0_twt;
50         unsigned long cs2_base;
51         unsigned long cs2_size;
52         unsigned long cs2_twt;
53
54         /*-------------------------------------------------------------------------+
55           | Initialize EBC CONFIG
56           +-------------------------------------------------------------------------*/
57         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
58               EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
59               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
60               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
61               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
62
63         /*-------------------------------------------------------------------------+
64           | FPGA. Initialize bank 7 with default values.
65           +-------------------------------------------------------------------------*/
66         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
67               EBC_BXAP_BCE_DISABLE|
68               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
69               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
70               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
71               EBC_BXAP_BEM_WRITEONLY|
72               EBC_BXAP_PEN_DISABLED);
73         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
74               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
75
76         /* read FPGA base register FPGA_REG0 */
77         switch_status = *fpga_base;
78
79         if (switch_status & 0x40) {
80                 cs0_base = 0xFFE00000;
81                 cs0_size = EBC_BXCR_BS_2MB;
82                 cs0_twt = 8;
83                 cs2_base = 0xFF800000;
84                 cs2_size = EBC_BXCR_BS_4MB;
85                 cs2_twt = 10;
86         } else {
87                 cs0_base = 0xFFC00000;
88                 cs0_size = EBC_BXCR_BS_4MB;
89                 cs0_twt = 10;
90                 cs2_base = 0xFF800000;
91                 cs2_size = EBC_BXCR_BS_2MB;
92                 cs2_twt = 8;
93         }
94
95         /*-------------------------------------------------------------------------+
96           | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
97           +-------------------------------------------------------------------------*/
98         mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
99               EBC_BXAP_BCE_DISABLE|
100               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
101               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
102               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
103               EBC_BXAP_BEM_WRITEONLY|
104               EBC_BXAP_PEN_DISABLED);
105         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
106               cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
107
108         /*-------------------------------------------------------------------------+
109           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
110           +-------------------------------------------------------------------------*/
111         mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
112               EBC_BXAP_BCE_DISABLE|
113               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
114               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
115               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
116               EBC_BXAP_BEM_WRITEONLY|
117               EBC_BXAP_PEN_DISABLED);
118         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
119               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
120
121         /*-------------------------------------------------------------------------+
122           | 4 MB FLASH. Initialize bank 2 with default values.
123           +-------------------------------------------------------------------------*/
124         mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
125               EBC_BXAP_BCE_DISABLE|
126               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
127               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
128               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
129               EBC_BXAP_BEM_WRITEONLY|
130               EBC_BXAP_PEN_DISABLED);
131         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
132               cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
133
134         /*-------------------------------------------------------------------------+
135           | FPGA. Initialize bank 7 with default values.
136           +-------------------------------------------------------------------------*/
137         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
138               EBC_BXAP_BCE_DISABLE|
139               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
140               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
141               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
142               EBC_BXAP_BEM_WRITEONLY|
143               EBC_BXAP_PEN_DISABLED);
144         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
145               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
146
147         /*--------------------------------------------------------------------
148          * Setup the interrupt controller polarities, triggers, etc.
149          *-------------------------------------------------------------------*/
150         mtdcr (uic0sr, 0xffffffff);     /* clear all */
151         mtdcr (uic0er, 0x00000000);     /* disable all */
152         mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
153         mtdcr (uic0pr, 0xfffffe13);     /* per ref-board manual */
154         mtdcr (uic0tr, 0x01c00008);     /* per ref-board manual */
155         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
156         mtdcr (uic0sr, 0xffffffff);     /* clear all */
157
158         mtdcr (uic1sr, 0xffffffff);     /* clear all */
159         mtdcr (uic1er, 0x00000000);     /* disable all */
160         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
161         mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
162         mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
163         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
164         mtdcr (uic1sr, 0xffffffff);     /* clear all */
165
166         mtdcr (uic2sr, 0xffffffff);     /* clear all */
167         mtdcr (uic2er, 0x00000000);     /* disable all */
168         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
169         mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
170         mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
171         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
172         mtdcr (uic2sr, 0xffffffff);     /* clear all */
173
174         mtdcr (uicb0sr, 0xfc000000); /* clear all */
175         mtdcr (uicb0er, 0x00000000); /* disable all */
176         mtdcr (uicb0cr, 0x00000000); /* all non-critical */
177         mtdcr (uicb0pr, 0xfc000000); /* */
178         mtdcr (uicb0tr, 0x00000000); /* */
179         mtdcr (uicb0vr, 0x00000001); /* */
180         mfsdr (sdr_mfr, mfr);
181         mfr &= ~SDR0_MFR_ECS_MASK;
182 /*      mtsdr(sdr_mfr, mfr); */
183         fpga_init();
184
185         return 0;
186 }
187
188
189 int checkboard (void)
190 {
191         char *s = getenv ("serial#");
192
193         printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
194         if (s != NULL) {
195                 puts (", serial# ");
196                 puts (s);
197         }
198         putc ('\n');
199
200         return (0);
201 }
202
203
204 long int initdram (int board_type)
205 {
206         long dram_size = 0;
207
208 #if defined(CONFIG_SPD_EEPROM)
209         dram_size = spd_sdram ();
210 #else
211         dram_size = fixed_sdram ();
212 #endif
213         return dram_size;
214 }
215
216
217 #if !defined(CONFIG_SPD_EEPROM)
218 /*************************************************************************
219  *  fixed sdram init -- doesn't use serial presence detect.
220  *
221  *  Assumes:    128 MB, non-ECC, non-registered
222  *              PLB @ 133 MHz
223  *
224  ************************************************************************/
225 long int fixed_sdram (void)
226 {
227         uint reg;
228
229         /*--------------------------------------------------------------------
230          * Setup some default
231          *------------------------------------------------------------------*/
232         mtsdram (mem_uabba, 0x00000000);        /* ubba=0 (default)             */
233         mtsdram (mem_slio, 0x00000000);         /* rdre=0 wrre=0 rarw=0         */
234         mtsdram (mem_devopt, 0x00000000);       /* dll=0 ds=0 (normal)          */
235         mtsdram (mem_wddctr, 0x00000000);       /* wrcp=0 dcd=0                 */
236         mtsdram (mem_clktr, 0x40000000);        /* clkp=1 (90 deg wr) dcdt=0    */
237
238         /*--------------------------------------------------------------------
239          * Setup for board-specific specific mem
240          *------------------------------------------------------------------*/
241         /*
242          * Following for CAS Latency = 2.5 @ 133 MHz PLB
243          */
244         mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
245         mtsdram (mem_tr0, 0x410a4012);  /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
246         /* RA=10 RD=3                       */
247         mtsdram (mem_tr1, 0x8080082f);  /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
248         mtsdram (mem_rtr, 0x08200000);  /* Rate 15.625 ns @ 133 MHz PLB     */
249         mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
250         udelay (400);                   /* Delay 200 usecs (min)            */
251
252         /*--------------------------------------------------------------------
253          * Enable the controller, then wait for DCEN to complete
254          *------------------------------------------------------------------*/
255         mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit           */
256         for (;;) {
257                 mfsdram (mem_mcsts, reg);
258                 if (reg & 0x80000000)
259                         break;
260         }
261
262         return (128 * 1024 * 1024);     /* 128 MB                           */
263 }
264 #endif  /* !defined(CONFIG_SPD_EEPROM) */
265
266
267 /*************************************************************************
268  *  pci_pre_init
269  *
270  *  This routine is called just prior to registering the hose and gives
271  *  the board the opportunity to check things. Returning a value of zero
272  *  indicates that things are bad & PCI initialization should be aborted.
273  *
274  *      Different boards may wish to customize the pci controller structure
275  *      (add regions, override default access routines, etc) or perform
276  *      certain pre-initialization actions.
277  *
278  ************************************************************************/
279 #if defined(CONFIG_PCI)
280 int pci_pre_init(struct pci_controller * hose )
281 {
282         unsigned long strap;
283
284         /*--------------------------------------------------------------------------+
285          *      The ocotea board is always configured as the host & requires the
286          *      PCI arbiter to be enabled.
287          *--------------------------------------------------------------------------*/
288         mfsdr(sdr_sdstp1, strap);
289         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
290                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
291                 return 0;
292         }
293
294         return 1;
295 }
296 #endif /* defined(CONFIG_PCI) */
297
298 /*************************************************************************
299  *  pci_target_init
300  *
301  *      The bootstrap configuration provides default settings for the pci
302  *      inbound map (PIM). But the bootstrap config choices are limited and
303  *      may not be sufficient for a given board.
304  *
305  ************************************************************************/
306 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
307 void pci_target_init(struct pci_controller * hose )
308 {
309         /*--------------------------------------------------------------------------+
310          * Disable everything
311          *--------------------------------------------------------------------------*/
312         out32r( PCIX0_PIM0SA, 0 ); /* disable */
313         out32r( PCIX0_PIM1SA, 0 ); /* disable */
314         out32r( PCIX0_PIM2SA, 0 ); /* disable */
315         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
316
317         /*--------------------------------------------------------------------------+
318          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
319          * options to not support sizes such as 128/256 MB.
320          *--------------------------------------------------------------------------*/
321         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
322         out32r( PCIX0_PIM0LAH, 0 );
323         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
324
325         out32r( PCIX0_BAR0, 0 );
326
327         /*--------------------------------------------------------------------------+
328          * Program the board's subsystem id/vendor id
329          *--------------------------------------------------------------------------*/
330         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
331         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
332
333         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
334 }
335 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
336
337
338 /*************************************************************************
339  *  is_pci_host
340  *
341  *      This routine is called to determine if a pci scan should be
342  *      performed. With various hardware environments (especially cPCI and
343  *      PPMC) it's insufficient to depend on the state of the arbiter enable
344  *      bit in the strap register, or generic host/adapter assumptions.
345  *
346  *      Rather than hard-code a bad assumption in the general 440 code, the
347  *      440 pci code requires the board to decide at runtime.
348  *
349  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
350  *
351  *
352  ************************************************************************/
353 #if defined(CONFIG_PCI)
354 int is_pci_host(struct pci_controller *hose)
355 {
356     /* The ocotea board is always configured as host. */
357     return(1);
358 }
359 #endif /* defined(CONFIG_PCI) */
360
361
362 void fpga_init(void)
363 {
364         unsigned long group;
365         unsigned long sdr0_pfc0;
366         unsigned long sdr0_pfc1;
367         unsigned long sdr0_cust0;
368         unsigned long pvr;
369
370         mfsdr (sdr_pfc0, sdr0_pfc0);
371         mfsdr (sdr_pfc1, sdr0_pfc1);
372         group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
373         pvr = get_pvr ();
374
375         sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
376         if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
377                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
378                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
379                 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
380                      FPGA_REG2_EXT_INTFACE_ENABLE);
381                 mtsdr (sdr_pfc0, sdr0_pfc0);
382                 mtsdr (sdr_pfc1, sdr0_pfc1);
383         } else {
384                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
385                 switch (group)
386                 {
387                 case 0:
388                 case 1:
389                 case 2:
390                         /* CPU trace A */
391                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
392                              FPGA_REG2_EXT_INTFACE_ENABLE);
393                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
394                         mtsdr (sdr_pfc0, sdr0_pfc0);
395                         mtsdr (sdr_pfc1, sdr0_pfc1);
396                         break;
397                 case 3:
398                 case 4:
399                 case 5:
400                 case 6:
401                         /* CPU trace B - Over EBMI */
402                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
403                         mtsdr (sdr_pfc0, sdr0_pfc0);
404                         mtsdr (sdr_pfc1, sdr0_pfc1);
405                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
406                              FPGA_REG2_EXT_INTFACE_DISABLE);
407                         break;
408                 }
409         }
410
411         /* Initialize the ethernet specific functions in the fpga */
412         mfsdr(sdr_pfc1, sdr0_pfc1);
413         mfsdr(sdr_cust0, sdr0_cust0);
414         if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
415             ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
416              (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
417         {
418                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
419                 {
420                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
421                              FPGA_REG3_ENET_GROUP7);
422                 }
423                 else
424                 {
425                         if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
426                         {
427                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
428                                      FPGA_REG3_ENET_GROUP7);
429                         }
430                         else
431                         {
432                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
433                                      FPGA_REG3_ENET_GROUP8);
434                         }
435                 }
436         }
437         else
438         {
439                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
440                 {
441                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
442                              FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
443                 }
444                 else
445                 {
446                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
447                              FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
448                 }
449         }
450         out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
451              FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
452              FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
453
454         /* reset the gigabyte phy if necessary */
455         if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
456         {
457                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
458                 {
459                         out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
460                         udelay(10000);
461                         out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
462                 }
463                 else
464                 {
465                         out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
466                         udelay(10000);
467                         out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
468                 }
469         }
470
471         /*
472          * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
473          */
474         if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
475                 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
476                 udelay(10000);
477                 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
478         }
479
480         /* Turn off the LED's */
481         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
482              FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
483              FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
484
485         return;
486 }
487
488 #ifdef CONFIG_POST
489 /*
490  * Returns 1 if keys pressed to start the power-on long-running tests
491  * Called from board_init_f().
492  */
493 int post_hotkeys_pressed(void)
494 {
495
496         return (ctrlc());
497 }
498 #endif