3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <fdt_support.h>
25 #include <asm/processor.h>
28 #include <asm/4xx_pcie.h>
30 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
32 DECLARE_GLOBAL_DATA_PTR;
34 int board_early_init_f(void)
38 /*------------------------------------------------------------------+
39 * Setup the interrupt controller polarities, triggers, etc.
40 *------------------------------------------------------------------*/
41 mtdcr(uic0sr, 0xffffffff); /* clear all */
42 mtdcr(uic0er, 0x00000000); /* disable all */
43 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
44 mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
45 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
46 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
47 mtdcr(uic0sr, 0xffffffff); /* clear all */
49 mtdcr(uic1sr, 0xffffffff); /* clear all */
50 mtdcr(uic1er, 0x00000000); /* disable all */
51 mtdcr(uic1cr, 0x00000000); /* all non-critical */
52 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
53 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
54 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
55 mtdcr(uic1sr, 0xffffffff); /* clear all */
57 mtdcr(uic2sr, 0xffffffff); /* clear all */
58 mtdcr(uic2er, 0x00000000); /* disable all */
59 mtdcr(uic2cr, 0x00000000); /* all non-critical */
60 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
61 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
62 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
63 mtdcr(uic2sr, 0xffffffff); /* clear all */
65 mtdcr(uic3sr, 0xffffffff); /* clear all */
66 mtdcr(uic3er, 0x00000000); /* disable all */
67 mtdcr(uic3cr, 0x00000000); /* all non-critical */
68 mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
69 mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
70 mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
71 mtdcr(uic3sr, 0xffffffff); /* clear all */
73 /* SDR Setting - enable NDFC */
74 mfsdr(SDR0_CUST0, sdr0_cust0);
75 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
76 SDR0_CUST0_NDFC_ENABLE |
77 SDR0_CUST0_NDFC_BW_8_BIT |
78 SDR0_CUST0_NDFC_ARE_MASK |
79 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
80 (0x80000000 >> (28 + CFG_NAND_CS));
81 mtsdr(SDR0_CUST0, sdr0_cust0);
84 * Configure PFC (Pin Function Control) registers
87 mtsdr(SDR0_PFC1, 0x00040000);
89 /* Enable PCI host functionality in SDR0_PCI0 */
90 mtsdr(SDR0_PCI0, 0xe0000000);
92 /* Enable ethernet and take out of reset */
93 out_8((void *)CFG_BCSR_BASE + 6, 0);
95 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
96 out_8((void *)CFG_BCSR_BASE + 5, 0);
98 /* Enable USB host & USB-OTG */
99 out_8((void *)CFG_BCSR_BASE + 7, 0);
101 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
106 int checkboard (void)
108 char *s = getenv("serial#");
111 if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
112 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
114 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
126 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
127 * board specific values.
129 u32 ddr_wrdtr(u32 default_val) {
130 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
133 u32 ddr_clktr(u32 default_val) {
134 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
137 #if defined(CONFIG_NAND_U_BOOT)
139 * NAND booting U-Boot version uses a fixed initialization, since the whole
140 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
143 long int initdram(int board_type)
145 return CFG_MBYTES_SDRAM << 20;
149 #if defined(CFG_DRAM_TEST)
152 unsigned long *mem = (unsigned long *)0;
153 const unsigned long kend = (1024 / sizeof(unsigned long));
158 for (k = 0; k < CFG_KBYTES_SDRAM;
159 ++k, mem += (1024 / sizeof(unsigned long))) {
160 if ((k & 1023) == 0) {
161 printf("%3d MB\r", k / 1024);
164 memset(mem, 0xaaaaaaaa, 1024);
165 for (n = 0; n < kend; ++n) {
166 if (mem[n] != 0xaaaaaaaa) {
167 printf("SDRAM test fails at: %08x\n",
173 memset(mem, 0x55555555, 1024);
174 for (n = 0; n < kend; ++n) {
175 if (mem[n] != 0x55555555) {
176 printf("SDRAM test fails at: %08x\n",
182 printf("SDRAM test passes\n");
187 /*************************************************************************
190 * The bootstrap configuration provides default settings for the pci
191 * inbound map (PIM). But the bootstrap config choices are limited and
192 * may not be sufficient for a given board.
194 ************************************************************************/
195 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
196 void pci_target_init(struct pci_controller * hose )
198 /*-------------------------------------------------------------------+
200 *-------------------------------------------------------------------*/
201 out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
202 out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
203 out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
204 out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
206 /*-------------------------------------------------------------------+
207 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
208 * strapping options to not support sizes such as 128/256 MB.
209 *-------------------------------------------------------------------*/
210 out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
211 out_le32((void *)PCIX0_PIM0LAH, 0);
212 out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
213 out_le32((void *)PCIX0_BAR0, 0);
215 /*-------------------------------------------------------------------+
216 * Program the board's subsystem id/vendor id
217 *-------------------------------------------------------------------*/
218 out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
219 out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
221 out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
223 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
225 #if defined(CONFIG_PCI)
229 * This routine is called to determine if a pci scan should be
230 * performed. With various hardware environments (especially cPCI and
231 * PPMC) it's insufficient to depend on the state of the arbiter enable
232 * bit in the strap register, or generic host/adapter assumptions.
234 * Rather than hard-code a bad assumption in the general 440 code, the
235 * 440 pci code requires the board to decide at runtime.
237 * Return 0 for adapter mode, non-zero for host (monarch) mode.
239 int is_pci_host(struct pci_controller *hose)
241 /* Board is always configured as host. */
245 static struct pci_controller pcie_hose[2] = {{0},{0}};
247 void pcie_setup_hoses(int busno)
249 struct pci_controller *hose;
256 * assume we're called after the PCIX hose is initialized, which takes
257 * bus ID 0 and therefore start numbering PCIe's from 1.
260 for (i = 0; i <= 1; i++) {
263 ret = ppc4xx_init_pcie_endport(i);
265 ret = ppc4xx_init_pcie_rootport(i);
267 printf("PCIE%d: initialization as %s failed\n", i,
268 is_end_point(i) ? "endpoint" : "root-complex");
272 hose = &pcie_hose[i];
273 hose->first_busno = bus;
274 hose->last_busno = bus;
275 hose->current_busno = bus;
277 /* setup mem resource */
278 pci_set_region(hose->regions + 0,
279 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
280 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
283 hose->region_count = 1;
284 pci_register_hose(hose);
286 if (is_end_point(i)) {
287 ppc4xx_setup_pcie_endpoint(hose, i);
289 * Reson for no scanning is endpoint can not generate
290 * upstream configuration accesses.
293 ppc4xx_setup_pcie_rootpoint(hose, i);
294 env = getenv ("pciscandelay");
296 delay = simple_strtoul(env, NULL, 10);
298 printf("Warning, expect noticable delay before "
299 "PCIe scan due to 'pciscandelay' value!\n");
300 mdelay(delay * 1000);
304 * Config access can only go down stream
306 hose->last_busno = pci_hose_scan(hose);
307 bus = hose->last_busno + 1;
311 #endif /* CONFIG_PCI */
313 int board_early_init_r (void)
316 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
317 * boot EBC mapping only supports a maximum of 16MBytes
318 * (4.ff00.0000 - 4.ffff.ffff).
319 * To solve this problem, the FLASH has to get remapped to another
320 * EBC address which accepts bigger regions:
322 * 0xfc00.0000 -> 4.cc00.0000
325 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
326 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
327 mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
329 mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
332 /* Remove TLB entry of boot EBC mapping */
333 remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
335 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
336 program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
340 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
341 * 0xfc00.0000 is possible
345 * Clear potential errors resulting from auto-calibration.
346 * If not done, then we could get an interrupt later on when
347 * exceptions are enabled.
349 set_mcsr(get_mcsr());
354 int misc_init_r(void)
360 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
361 * This is board specific, so let's do it here.
363 mfsdr(SDR0_ETH_CFG, eth_cfg);
364 /* disable SGMII mode */
365 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
366 SDR0_ETH_CFG_SGMII1_ENABLE |
367 SDR0_ETH_CFG_SGMII0_ENABLE);
368 /* Set the for 2 RGMII mode */
369 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
370 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
371 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
372 mtsdr(SDR0_ETH_CFG, eth_cfg);
375 * The AHB Bridge core is held in reset after power-on or reset
378 mfsdr(SDR0_SRST1, sdr0_srst1);
379 sdr0_srst1 &= ~SDR0_SRST1_AHB;
380 mtsdr(SDR0_SRST1, sdr0_srst1);
385 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
386 void ft_board_setup(void *blob, bd_t *bd)
391 ft_cpu_setup(blob, bd);
393 /* Fixup NOR mapping */
394 val[0] = 0; /* chip select number */
395 val[1] = 0; /* always 0 */
396 val[2] = gd->bd->bi_flashstart;
397 val[3] = gd->bd->bi_flashsize;
398 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
399 val, sizeof(val), 1);
401 printf("Unable to update property NOR mapping, err=%s\n",
404 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */