board/amcc/bamboo/bamboo.c

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <spd_sdram.h>
  27 #include <ppc440.h>
  28 #include "bamboo.h"
  29
  30 void ext_bus_cntlr_init(void);
  31 void configure_ppc440ep_pins(void);
  32 int is_nand_selected(void);
  33
  34 unsigned char cfg_simulate_spd_eeprom[128];
  35
  36 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  37 #if 0
  38 {          /* GPIO   Alternate1       Alternate2        Alternate3 */
  39     {
  40         /* GPIO Core 0 */
  41         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0  -> EBC_ADDR(7)      DMA_REQ(2) */
  42         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1  -> EBC_ADDR(6)      DMA_ACK(2) */
  43         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2  -> EBC_ADDR(5)      DMA_EOT/TC(2) */
  44         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3  -> EBC_ADDR(4)      DMA_REQ(3) */
  45         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4  -> EBC_ADDR(3)      DMA_ACK(3) */
  46         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  47         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6  -> EBC_CS_N(1) */
  48         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7  -> EBC_CS_N(2) */
  49         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8  -> EBC_CS_N(3) */
  50         { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9  -> EBC_CS_N(4) */
  51         { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  52         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  53         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  54         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  55         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  56         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  57         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  58         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  59         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  60         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  61         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  62         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  63         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  64         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  65         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  66         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  67         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->                  USB2D_RXVALID */
  68         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ      USB2D_RXERROR */
  69         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->                  USB2D_TXVALID */
  70         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA     USB2D_PAD_SUSPNDM */
  71         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK      USB2D_XCVRSELECT */
  72         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
  73     },
  74     {
  75         /* GPIO Core 1 */
  76         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0  -> USB2D_OPMODE0 */
  77         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1  -> USB2D_OPMODE1 */
  78         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2  -> UART0_DCD_N      UART1_DSR_CTS_N   UART2_SOUT */
  79         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3  -> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
  80         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4  -> UART0_8PIN_CTS_N                   UART3_SIN */
  81         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5  -> UART0_RTS_N */
  82         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6  -> UART0_DTR_N      UART1_SOUT */
  83         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7  -> UART0_RI_N       UART1_SIN */
  84         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8  -> UIC_IRQ(0) */
  85         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9  -> UIC_IRQ(1) */
  86         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  87         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  88         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)       DMA_ACK(1) */
  89         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)       DMA_EOT/TC(1) */
  90         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)       DMA_REQ(0) */
  91         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)       DMA_ACK(0) */
  92         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)       DMA_EOT/TC(0) */
  93         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  94         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
  95         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
  96         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
  97         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
  98         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
  99         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \     Can be unselected thru TraceSelect Bit */
 100         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /        in PowerPC440EP Chip */
 101         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
 102         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
 103         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
 104         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
 105         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
 106         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
 107         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
 108     }
 109 };
 110 #endif
 111
 112 /*----------------------------------------------------------------------------+
 113   | EBC Devices Characteristics
 114   |   Peripheral Bank Access Parameters       -   EBC0_BnAP
 115   |   Peripheral Bank Configuration Register  -   EBC0_BnCR
 116   +----------------------------------------------------------------------------*/
 117 /* Small Flash */
 118 #define EBC0_BNAP_SMALL_FLASH                           \
 119         EBC0_BNAP_BME_DISABLED                  |       \
 120         EBC0_BNAP_TWT_ENCODE(6)                 |       \
 121         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 122         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 123         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 124         EBC0_BNAP_WBF_ENCODE(3)                 |       \
 125         EBC0_BNAP_TH_ENCODE(1)                  |       \
 126         EBC0_BNAP_RE_ENABLED                    |       \
 127         EBC0_BNAP_SOR_DELAYED                   |       \
 128         EBC0_BNAP_BEM_WRITEONLY                 |       \
 129         EBC0_BNAP_PEN_DISABLED
 130
 131 #define EBC0_BNCR_SMALL_FLASH_CS0                       \
 132         EBC0_BNCR_BAS_ENCODE(0xFFF00000)        |       \
 133         EBC0_BNCR_BS_1MB                        |       \
 134         EBC0_BNCR_BU_RW                         |       \
 135         EBC0_BNCR_BW_8BIT
 136
 137 #define EBC0_BNCR_SMALL_FLASH_CS4                       \
 138         EBC0_BNCR_BAS_ENCODE(0x87F00000)        |       \
 139         EBC0_BNCR_BS_1MB                        |       \
 140         EBC0_BNCR_BU_RW                         |       \
 141         EBC0_BNCR_BW_8BIT
 142
 143 /* Large Flash or SRAM */
 144 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM                   \
 145         EBC0_BNAP_BME_DISABLED                  |       \
 146         EBC0_BNAP_TWT_ENCODE(8)                 |       \
 147         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 148         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 149         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 150         EBC0_BNAP_WBF_ENCODE(1)                 |       \
 151         EBC0_BNAP_TH_ENCODE(2)                  |       \
 152         EBC0_BNAP_SOR_DELAYED                   |       \
 153         EBC0_BNAP_BEM_RW                        |       \
 154         EBC0_BNAP_PEN_DISABLED
 155
 156 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0               \
 157         EBC0_BNCR_BAS_ENCODE(0xFF800000)        |       \
 158         EBC0_BNCR_BS_8MB                        |       \
 159         EBC0_BNCR_BU_RW                         |       \
 160         EBC0_BNCR_BW_16BIT
 161
 162
 163 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4               \
 164         EBC0_BNCR_BAS_ENCODE(0x87800000)        |       \
 165         EBC0_BNCR_BS_8MB                        |       \
 166         EBC0_BNCR_BU_RW                         |       \
 167         EBC0_BNCR_BW_16BIT
 168
 169 /* NVRAM - FPGA */
 170 #define EBC0_BNAP_NVRAM_FPGA                            \
 171         EBC0_BNAP_BME_DISABLED                  |       \
 172         EBC0_BNAP_TWT_ENCODE(9)                 |       \
 173         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 174         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 175         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 176         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 177         EBC0_BNAP_TH_ENCODE(2)                  |       \
 178         EBC0_BNAP_RE_ENABLED                    |       \
 179         EBC0_BNAP_SOR_DELAYED                   |       \
 180         EBC0_BNAP_BEM_WRITEONLY                 |       \
 181         EBC0_BNAP_PEN_DISABLED
 182
 183 #define EBC0_BNCR_NVRAM_FPGA_CS5                        \
 184         EBC0_BNCR_BAS_ENCODE(0x80000000)        |       \
 185         EBC0_BNCR_BS_1MB                        |       \
 186         EBC0_BNCR_BU_RW                         |       \
 187         EBC0_BNCR_BW_8BIT
 188
 189 /* Nand Flash */
 190 #define EBC0_BNAP_NAND_FLASH                            \
 191         EBC0_BNAP_BME_DISABLED                  |       \
 192         EBC0_BNAP_TWT_ENCODE(3)                 |       \
 193         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 194         EBC0_BNAP_OEN_ENCODE(0)                 |       \
 195         EBC0_BNAP_WBN_ENCODE(0)                 |       \
 196         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 197         EBC0_BNAP_TH_ENCODE(1)                  |       \
 198         EBC0_BNAP_RE_ENABLED                    |       \
 199         EBC0_BNAP_SOR_NOT_DELAYED               |       \
 200         EBC0_BNAP_BEM_RW                        |       \
 201         EBC0_BNAP_PEN_DISABLED
 202
 203
 204 #define EBC0_BNCR_NAND_FLASH_CS0        0xB8400000
 205
 206 /* NAND0 */
 207 #define EBC0_BNCR_NAND_FLASH_CS1                        \
 208         EBC0_BNCR_BAS_ENCODE(0x90000000)        |       \
 209         EBC0_BNCR_BS_1MB                        |       \
 210         EBC0_BNCR_BU_RW                         |       \
 211         EBC0_BNCR_BW_32BIT
 212 /* NAND1 - Bank2 */
 213 #define EBC0_BNCR_NAND_FLASH_CS2                        \
 214         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 215         EBC0_BNCR_BS_1MB                        |       \
 216         EBC0_BNCR_BU_RW                         |       \
 217         EBC0_BNCR_BW_32BIT
 218
 219 /* NAND1 - Bank3 */
 220 #define EBC0_BNCR_NAND_FLASH_CS3                        \
 221         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 222         EBC0_BNCR_BS_1MB                        |       \
 223         EBC0_BNCR_BU_RW                         |       \
 224         EBC0_BNCR_BW_32BIT
 225
 226 int board_early_init_f(void)
 227 {
 228         ext_bus_cntlr_init();
 229
 230         /*--------------------------------------------------------------------
 231          * Setup the interrupt controller polarities, triggers, etc.
 232          *-------------------------------------------------------------------*/
 233         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 234         mtdcr(uic0er, 0x00000000);      /* disable all */
 235         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
 236         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 237         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 238         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 239         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 240
 241         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 242         mtdcr(uic1er, 0x00000000);      /* disable all */
 243         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 244         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 245         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 246         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 247         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 248
 249         /*--------------------------------------------------------------------
 250          * Setup the GPIO pins
 251          *-------------------------------------------------------------------*/
 252         out32(GPIO0_OSRL,  0x00000400);
 253         out32(GPIO0_OSRH,  0x00000000);
 254         out32(GPIO0_TSRL,  0x00000400);
 255         out32(GPIO0_TSRH,  0x00000000);
 256         out32(GPIO0_ISR1L, 0x00000000);
 257         out32(GPIO0_ISR1H, 0x00000000);
 258         out32(GPIO0_ISR2L, 0x00000000);
 259         out32(GPIO0_ISR2H, 0x00000000);
 260         out32(GPIO0_ISR3L, 0x00000000);
 261         out32(GPIO0_ISR3H, 0x00000000);
 262
 263         out32(GPIO1_OSRL,  0x0C380000);
 264         out32(GPIO1_OSRH,  0x00000000);
 265         out32(GPIO1_TSRL,  0x0C380000);
 266         out32(GPIO1_TSRH,  0x00000000);
 267         out32(GPIO1_ISR1L, 0x0FC30000);
 268         out32(GPIO1_ISR1H, 0x00000000);
 269         out32(GPIO1_ISR2L, 0x0C010000);
 270         out32(GPIO1_ISR2H, 0x00000000);
 271         out32(GPIO1_ISR3L, 0x01400000);
 272         out32(GPIO1_ISR3H, 0x00000000);
 273
 274         configure_ppc440ep_pins();
 275
 276         return 0;
 277 }
 278
 279 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 280 #include <linux/mtd/nand.h>
 281 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 282
 283 /*----------------------------------------------------------------------------+
 284   | nand_reset.
 285   |   Reset Nand flash
 286   |   This routine will abort previous cmd
 287   +----------------------------------------------------------------------------*/
 288 int nand_reset(ulong addr)
 289 {
 290         int wait=0, stat=0;
 291
 292         out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
 293         out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
 294
 295         while ((stat != 0xc0) && (wait != 0xffff)) {
 296                 stat = in8(addr + NAND_DATA_REG);
 297                 wait++;
 298         }
 299
 300         if (stat == 0xc0) {
 301                 return 0;
 302         } else {
 303                 printf("NAND Reset timeout.\n");
 304                 return -1;
 305         }
 306 }
 307
 308 void board_nand_set_device(int cs, ulong addr)
 309 {
 310         /* Set NandFlash Core Configuration Register */
 311         out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
 312
 313         switch (cs) {
 314         case 1:
 315                 /* -------
 316                  *  NAND0
 317                  * -------
 318                  * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
 319                  * Set NDF1CR - Enable External CS1 in NAND FLASH controller
 320                  */
 321                 out32(addr + NAND_CR1_REG, 0x80002222);
 322                 break;
 323
 324         case 2:
 325                 /* -------
 326                  *  NAND1
 327                  * -------
 328                  * K9K2G0B : 5 addr cyc, 2 col + 3 Row
 329                  * Set NDF2CR : Enable External CS2 in NAND FLASH controller
 330                  */
 331                 out32(addr + NAND_CR2_REG, 0xC0007777);
 332                 break;
 333         }
 334
 335         /* Perform Reset Command */
 336         if (nand_reset(addr) != 0)
 337                 return;
 338 }
 339
 340 void nand_init(void)
 341 {
 342         board_nand_set_device(1, CFG_NAND_ADDR);
 343
 344         nand_probe(CFG_NAND_ADDR);
 345         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 346                 print_size(nand_dev_desc[0].totlen, "\n");
 347         }
 348
 349 #if 0 /* NAND1 not supported yet */
 350         board_nand_set_device(2, CFG_NAND2_ADDR);
 351
 352         nand_probe(CFG_NAND2_ADDR);
 353         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 354                 print_size(nand_dev_desc[0].totlen, "\n");
 355         }
 356 #endif
 357 }
 358 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
 359
 360 int checkboard(void)
 361 {
 362         sys_info_t sysinfo;
 363         unsigned char *s = getenv("serial#");
 364
 365         get_sys_info(&sysinfo);
 366
 367         printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
 368         if (s != NULL) {
 369                 puts(", serial# ");
 370                 puts(s);
 371         }
 372         putc('\n');
 373
 374         printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 375         printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 376         printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 377         printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 378         printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 379
 380         return (0);
 381 }
 382
 383 /*************************************************************************
 384  *
 385  * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
 386  *
 387  * Fixed memory is composed of :
 388  *      MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
 389  *      13 row add bits, 10 column add bits (but 12 row used only).
 390  *      ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
 391  *      12 row add bits, 10 column add bits.
 392  *      Prepare a subset (only the used ones) of SPD data
 393  *
 394  *      Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
 395  *      the corresponding bank is divided by 2 due to number of Row addresses
 396  *      12 in the ECC module
 397  *
 398  *  Assumes:    64 MB, ECC, non-registered
 399  *              PLB @ 133 MHz
 400  *
 401  ************************************************************************/
 402 static void init_spd_array(void)
 403 {
 404         cfg_simulate_spd_eeprom[8]     = 0x04;    /* 2.5 Volt */
 405         cfg_simulate_spd_eeprom[2]     = 0x07;    /* DDR ram */
 406
 407 #ifdef CONFIG_DDR_ECC
 408         cfg_simulate_spd_eeprom[11]    = 0x02;    /* ECC ON : 02 OFF : 00 */
 409         cfg_simulate_spd_eeprom[31]    = 0x08;    /* bankSizeID: 32MB */
 410         cfg_simulate_spd_eeprom[3]     = 0x0C;    /* num Row Addr: 12 */
 411 #else
 412         cfg_simulate_spd_eeprom[11]    = 0x00;    /* ECC ON : 02 OFF : 00 */
 413         cfg_simulate_spd_eeprom[31]    = 0x10;    /* bankSizeID: 64MB */
 414         cfg_simulate_spd_eeprom[3]     = 0x0D;    /* num Row Addr: 13 */
 415 #endif
 416
 417         cfg_simulate_spd_eeprom[4]     = 0x09;    /* numColAddr: 9  */
 418         cfg_simulate_spd_eeprom[5]     = 0x01;    /* numBanks: 1 */
 419         cfg_simulate_spd_eeprom[0]     = 0x80;    /* number of SPD bytes used: 128 */
 420         cfg_simulate_spd_eeprom[1]     = 0x08;    /*  total number bytes in SPD device = 256 */
 421         cfg_simulate_spd_eeprom[21]    = 0x00;    /* not registered: 0  registered : 0x02*/
 422         cfg_simulate_spd_eeprom[6]     = 0x20;    /* Module data width: 32 bits */
 423         cfg_simulate_spd_eeprom[7]     = 0x00;    /* Module data width continued: +0 */
 424         cfg_simulate_spd_eeprom[15]    = 0x01;    /* wcsbc = 1 */
 425         cfg_simulate_spd_eeprom[27]    = 0x50;    /* tRpNs = 20 ns  */
 426         cfg_simulate_spd_eeprom[29]    = 0x50;    /* tRcdNs = 20 ns */
 427
 428         cfg_simulate_spd_eeprom[30]    = 45;      /* tRasNs */
 429
 430         cfg_simulate_spd_eeprom[18]    = 0x0C;    /* casBit (2,2.5) */
 431
 432         cfg_simulate_spd_eeprom[9]     = 0x75;    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
 433         cfg_simulate_spd_eeprom[23]    = 0xA0;    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
 434         cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
 435         cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */
 436 }
 437
 438 long int initdram (int board_type)
 439 {
 440         long dram_size = 0;
 441
 442         /*
 443          * First write simulated values in eeprom array for onboard bank 0
 444          */
 445         init_spd_array();
 446
 447         dram_size = spd_sdram (0);
 448
 449         return dram_size;
 450 }
 451
 452 #if defined(CFG_DRAM_TEST)
 453 int testdram(void)
 454 {
 455         unsigned long *mem = (unsigned long *)0;
 456         const unsigned long kend = (1024 / sizeof(unsigned long));
 457         unsigned long k, n;
 458
 459         mtmsr(0);
 460
 461         for (k = 0; k < CFG_KBYTES_SDRAM;
 462              ++k, mem += (1024 / sizeof(unsigned long))) {
 463                 if ((k & 1023) == 0) {
 464                         printf("%3d MB\r", k / 1024);
 465                 }
 466
 467                 memset(mem, 0xaaaaaaaa, 1024);
 468                 for (n = 0; n < kend; ++n) {
 469                         if (mem[n] != 0xaaaaaaaa) {
 470                                 printf("SDRAM test fails at: %08x\n",
 471                                        (uint) & mem[n]);
 472                                 return 1;
 473                         }
 474                 }
 475
 476                 memset(mem, 0x55555555, 1024);
 477                 for (n = 0; n < kend; ++n) {
 478                         if (mem[n] != 0x55555555) {
 479                                 printf("SDRAM test fails at: %08x\n",
 480                                        (uint) & mem[n]);
 481                                 return 1;
 482                         }
 483                 }
 484         }
 485         printf("SDRAM test passes\n");
 486         return 0;
 487 }
 488 #endif
 489
 490 /*************************************************************************
 491  *  pci_pre_init
 492  *
 493  *  This routine is called just prior to registering the hose and gives
 494  *  the board the opportunity to check things. Returning a value of zero
 495  *  indicates that things are bad & PCI initialization should be aborted.
 496  *
 497  *      Different boards may wish to customize the pci controller structure
 498  *      (add regions, override default access routines, etc) or perform
 499  *      certain pre-initialization actions.
 500  *
 501  ************************************************************************/
 502 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 503 int pci_pre_init(struct pci_controller *hose)
 504 {
 505         unsigned long strap;
 506         unsigned long addr;
 507
 508         /*--------------------------------------------------------------------------+
 509          *      Bamboo is always configured as the host & requires the
 510          *      PCI arbiter to be enabled.
 511          *--------------------------------------------------------------------------*/
 512         mfsdr(sdr_sdstp1, strap);
 513         if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 514                 printf("PCI: SDR0_STRP1[PAE] not set.\n");
 515                 printf("PCI: Configuration aborted.\n");
 516                 return 0;
 517         }
 518
 519         /*-------------------------------------------------------------------------+
 520           | Set priority for all PLB3 devices to 0.
 521           | Set PLB3 arbiter to fair mode.
 522           +-------------------------------------------------------------------------*/
 523         mfsdr(sdr_amp1, addr);
 524         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 525         addr = mfdcr(plb3_acr);
 526         mtdcr(plb3_acr, addr | 0x80000000);
 527
 528         /*-------------------------------------------------------------------------+
 529           | Set priority for all PLB4 devices to 0.
 530           +-------------------------------------------------------------------------*/
 531         mfsdr(sdr_amp0, addr);
 532         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 533         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 534         mtdcr(plb4_acr, addr);
 535
 536         /*-------------------------------------------------------------------------+
 537           | Set Nebula PLB4 arbiter to fair mode.
 538           +-------------------------------------------------------------------------*/
 539         /* Segment0 */
 540         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 541         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 542         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 543         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 544         mtdcr(plb0_acr, addr);
 545
 546         /* Segment1 */
 547         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 548         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 549         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 550         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 551         mtdcr(plb1_acr, addr);
 552
 553         return 1;
 554 }
 555 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 556
 557 /*************************************************************************
 558  *  pci_target_init
 559  *
 560  *      The bootstrap configuration provides default settings for the pci
 561  *      inbound map (PIM). But the bootstrap config choices are limited and
 562  *      may not be sufficient for a given board.
 563  *
 564  ************************************************************************/
 565 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 566 void pci_target_init(struct pci_controller *hose)
 567 {
 568         /*--------------------------------------------------------------------------+
 569          * Set up Direct MMIO registers
 570          *--------------------------------------------------------------------------*/
 571         /*--------------------------------------------------------------------------+
 572           | PowerPC440 EP PCI Master configuration.
 573           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 574           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 575           |   Use byte reversed out routines to handle endianess.
 576           | Make this region non-prefetchable.
 577           +--------------------------------------------------------------------------*/
 578         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 579         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 580         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 581         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 582         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 583
 584         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 585         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 586         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 587         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 588         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 589
 590         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 591         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 592         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 593         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 594
 595         /*--------------------------------------------------------------------------+
 596          * Set up Configuration registers
 597          *--------------------------------------------------------------------------*/
 598
 599         /* Program the board's subsystem id/vendor id */
 600         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 601                               CFG_PCI_SUBSYS_VENDORID);
 602         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 603
 604         /* Configure command register as bus master */
 605         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 606
 607         /* 240nS PCI clock */
 608         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 609
 610         /* No error reporting */
 611         pci_write_config_word(0, PCI_ERREN, 0);
 612
 613         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 614
 615 }
 616 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 617
 618 /*************************************************************************
 619  *  pci_master_init
 620  *
 621  ************************************************************************/
 622 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 623 void pci_master_init(struct pci_controller *hose)
 624 {
 625         unsigned short temp_short;
 626
 627         /*--------------------------------------------------------------------------+
 628           | Write the PowerPC440 EP PCI Configuration regs.
 629           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 630           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 631           +--------------------------------------------------------------------------*/
 632         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 633         pci_write_config_word(0, PCI_COMMAND,
 634                               temp_short | PCI_COMMAND_MASTER |
 635                               PCI_COMMAND_MEMORY);
 636 }
 637 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 638
 639 /*************************************************************************
 640  *  is_pci_host
 641  *
 642  *      This routine is called to determine if a pci scan should be
 643  *      performed. With various hardware environments (especially cPCI and
 644  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 645  *      bit in the strap register, or generic host/adapter assumptions.
 646  *
 647  *      Rather than hard-code a bad assumption in the general 440 code, the
 648  *      440 pci code requires the board to decide at runtime.
 649  *
 650  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 651  *
 652  *
 653  ************************************************************************/
 654 #if defined(CONFIG_PCI)
 655 int is_pci_host(struct pci_controller *hose)
 656 {
 657         /* Bamboo is always configured as host. */
 658         return (1);
 659 }
 660 #endif                          /* defined(CONFIG_PCI) */
 661
 662 /*----------------------------------------------------------------------------+
 663   | is_powerpc440ep_pass1.
 664   +----------------------------------------------------------------------------*/
 665 int is_powerpc440ep_pass1(void)
 666 {
 667         unsigned long pvr;
 668
 669         pvr = get_pvr();
 670
 671         if (pvr == PVR_POWERPC_440EP_PASS1)
 672                 return TRUE;
 673         else if (pvr == PVR_POWERPC_440EP_PASS2)
 674                 return FALSE;
 675         else {
 676                 printf("brdutil error 3\n");
 677                 for (;;)
 678                         ;
 679         }
 680
 681         return(FALSE);
 682 }
 683
 684 /*----------------------------------------------------------------------------+
 685   | is_nand_selected.
 686   +----------------------------------------------------------------------------*/
 687 int is_nand_selected(void)
 688 {
 689 #ifdef CONFIG_BAMBOO_NAND
 690         return TRUE;
 691 #else
 692         return FALSE;
 693 #endif
 694 }
 695
 696 /*----------------------------------------------------------------------------+
 697   | config_on_ebc_cs4_is_small_flash => from EPLD
 698   +----------------------------------------------------------------------------*/
 699 unsigned char config_on_ebc_cs4_is_small_flash(void)
 700 {
 701         /* Not implemented yet => returns constant value */
 702         return TRUE;
 703 }
 704
 705 /*----------------------------------------------------------------------------+
 706   | Ext_bus_cntlr_init.
 707   | Initialize the external bus controller
 708   +----------------------------------------------------------------------------*/
 709 void ext_bus_cntlr_init(void)
 710 {
 711         unsigned long sdr0_pstrp0, sdr0_sdstp1;
 712         unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
 713         int           computed_boot_device = BOOT_DEVICE_UNKNOWN;
 714         unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
 715         unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
 716         unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
 717         unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
 718         unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
 719
 720
 721         /*-------------------------------------------------------------------------+
 722           |
 723           |  PART 1 : Initialize EBC Bank 5
 724           |  ==============================
 725           | Bank5 is always associated to the NVRAM/EPLD.
 726           | It has to be initialized prior to other banks settings computation since
 727           | some board registers values may be needed
 728           |
 729           +-------------------------------------------------------------------------*/
 730         /* NVRAM - FPGA */
 731         mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
 732         mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
 733
 734         /*-------------------------------------------------------------------------+
 735           |
 736           |  PART 2 : Determine which boot device was selected
 737           |  =========================================
 738           |
 739           |  Read Pin Strap Register in PPC440EP
 740           |  In case of boot from IIC, read Serial Device Strap Register1
 741           |
 742           |  Result can either be :
 743           |   - Boot from EBC 8bits    => SMALL FLASH
 744           |   - Boot from EBC 16bits   => Large Flash or SRAM
 745           |   - Boot from NAND Flash
 746           |   - Boot from PCI
 747           |
 748           +-------------------------------------------------------------------------*/
 749         /* Read Pin Strap Register in PPC440EP */
 750         mfsdr(sdr_pstrp0, sdr0_pstrp0);
 751         bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
 752
 753         /*-------------------------------------------------------------------------+
 754           |  PPC440EP Pass1
 755           +-------------------------------------------------------------------------*/
 756         if (is_powerpc440ep_pass1() == TRUE) {
 757                 switch(bootstrap_settings) {
 758                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 759                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 760                         /* Boot from Small Flash */
 761                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 762                         break;
 763                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 764                         /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
 765                         /* Boot from PCI */
 766                         computed_boot_device = BOOT_FROM_PCI;
 767                         break;
 768
 769                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 770                         /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
 771                         /* Boot from Nand Flash */
 772                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 773                         break;
 774
 775                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 776                         /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
 777                         /* Boot from Small Flash */
 778                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 779                         break;
 780
 781                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 782                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 783                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 784                         /* Read Serial Device Strap Register1 in PPC440EP */
 785                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 786                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 787                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 788
 789                         switch(boot_selection) {
 790                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 791                                 switch(ebc_boot_size) {
 792                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 793                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 794                                         break;
 795                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 796                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 797                                         break;
 798                                 }
 799                                 break;
 800
 801                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 802                                 computed_boot_device = BOOT_FROM_PCI;
 803                                 break;
 804
 805                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 806                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 807                                 break;
 808                         }
 809                         break;
 810                 }
 811         }
 812
 813         /*-------------------------------------------------------------------------+
 814           |  PPC440EP Pass2
 815           +-------------------------------------------------------------------------*/
 816         else {
 817                 switch(bootstrap_settings) {
 818                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 819                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 820                         /* Boot from Small Flash */
 821                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 822                         break;
 823                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 824                         /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
 825                         /* Boot from PCI */
 826                         computed_boot_device = BOOT_FROM_PCI;
 827                         break;
 828
 829                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 830                         /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
 831                         /* Boot from Nand Flash */
 832                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 833                         break;
 834
 835                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 836                         /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
 837                         /* Boot from Large Flash or SRAM */
 838                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 839                         break;
 840
 841                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
 842                         /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
 843                         /* Boot from Large Flash or SRAM */
 844                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 845                         break;
 846
 847                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
 848                         /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
 849                         /* Boot from PCI */
 850                         computed_boot_device = BOOT_FROM_PCI;
 851                         break;
 852
 853                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 854                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 855                         /* Default Strap Settings 5-7 */
 856                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 857                         /* Read Serial Device Strap Register1 in PPC440EP */
 858                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 859                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 860                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 861
 862                         switch(boot_selection) {
 863                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 864                                 switch(ebc_boot_size) {
 865                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 866                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 867                                         break;
 868                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 869                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 870                                         break;
 871                                 }
 872                                 break;
 873
 874                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 875                                 computed_boot_device = BOOT_FROM_PCI;
 876                                 break;
 877
 878                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 879                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 880                                 break;
 881                         }
 882                         break;
 883                 }
 884         }
 885
 886         /*-------------------------------------------------------------------------+
 887           |
 888           |  PART 3 : Compute EBC settings depending on selected boot device
 889           |  ======   ======================================================
 890           |
 891           | Resulting EBC init will be among following configurations :
 892           |
 893           |  - Boot from EBC 8bits => boot from SMALL FLASH selected
 894           |            EBC-CS0     = Small Flash
 895           |            EBC-CS1,2,3 = NAND Flash or
 896           |                         Exp.Slot depending on Soft Config
 897           |            EBC-CS4     = SRAM/Large Flash or
 898           |                         Large Flash/SRAM depending on jumpers
 899           |            EBC-CS5     = NVRAM / EPLD
 900           |
 901           |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
 902           |            EBC-CS0     = SRAM/Large Flash or
 903           |                          Large Flash/SRAM depending on jumpers
 904           |            EBC-CS1,2,3 = NAND Flash or
 905           |                          Exp.Slot depending on Software Configuration
 906           |            EBC-CS4     = Small Flash
 907           |            EBC-CS5     = NVRAM / EPLD
 908           |
 909           |  - Boot from NAND Flash
 910           |            EBC-CS0     = NAND Flash0
 911           |            EBC-CS1,2,3 = NAND Flash1
 912           |            EBC-CS4     = SRAM/Large Flash or
 913           |                          Large Flash/SRAM depending on jumpers
 914           |            EBC-CS5     = NVRAM / EPLD
 915           |
 916           |    - Boot from PCI
 917           |            EBC-CS0     = ...
 918           |            EBC-CS1,2,3 = NAND Flash or
 919           |                          Exp.Slot depending on Software Configuration
 920           |            EBC-CS4     = SRAM/Large Flash or
 921           |                          Large Flash/SRAM or
 922           |                          Small Flash depending on jumpers
 923           |            EBC-CS5     = NVRAM / EPLD
 924           |
 925           +-------------------------------------------------------------------------*/
 926
 927         switch(computed_boot_device) {
 928                 /*------------------------------------------------------------------------- */
 929         case BOOT_FROM_SMALL_FLASH:
 930                 /*------------------------------------------------------------------------- */
 931                 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
 932                 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
 933                 if ((is_nand_selected()) == TRUE) {
 934                         /* NAND Flash */
 935                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 936                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 937                         ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
 938                         ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
 939                         ebc0_cs3_bnap_value = 0;
 940                         ebc0_cs3_bncr_value = 0;
 941                 } else {
 942                         /* Expansion Slot */
 943                         ebc0_cs1_bnap_value = 0;
 944                         ebc0_cs1_bncr_value = 0;
 945                         ebc0_cs2_bnap_value = 0;
 946                         ebc0_cs2_bncr_value = 0;
 947                         ebc0_cs3_bnap_value = 0;
 948                         ebc0_cs3_bncr_value = 0;
 949                 }
 950                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 951                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 952
 953                 break;
 954
 955                 /*------------------------------------------------------------------------- */
 956         case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 957                 /*------------------------------------------------------------------------- */
 958                 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 959                 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
 960                 if ((is_nand_selected()) == TRUE) {
 961                         /* NAND Flash */
 962                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 963                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 964                         ebc0_cs2_bnap_value = 0;
 965                         ebc0_cs2_bncr_value = 0;
 966                         ebc0_cs3_bnap_value = 0;
 967                         ebc0_cs3_bncr_value = 0;
 968                 } else {
 969                         /* Expansion Slot */
 970                         ebc0_cs1_bnap_value = 0;
 971                         ebc0_cs1_bncr_value = 0;
 972                         ebc0_cs2_bnap_value = 0;
 973                         ebc0_cs2_bncr_value = 0;
 974                         ebc0_cs3_bnap_value = 0;
 975                         ebc0_cs3_bncr_value = 0;
 976                 }
 977                 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 978                 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 979
 980                 break;
 981
 982                 /*------------------------------------------------------------------------- */
 983         case BOOT_FROM_NAND_FLASH0:
 984                 /*------------------------------------------------------------------------- */
 985                 ebc0_cs0_bnap_value = 0;
 986                 ebc0_cs0_bncr_value = 0;
 987
 988                 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 989                 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 990                 ebc0_cs2_bnap_value = 0;
 991                 ebc0_cs2_bncr_value = 0;
 992                 ebc0_cs3_bnap_value = 0;
 993                 ebc0_cs3_bncr_value = 0;
 994
 995                 /* Large Flash or SRAM */
 996                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 997                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 998
 999                 break;
1000
1001                 /*------------------------------------------------------------------------- */
1002         case BOOT_FROM_PCI:
1003                 /*------------------------------------------------------------------------- */
1004                 ebc0_cs0_bnap_value = 0;
1005                 ebc0_cs0_bncr_value = 0;
1006
1007                 if ((is_nand_selected()) == TRUE) {
1008                         /* NAND Flash */
1009                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
1010                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
1011                         ebc0_cs2_bnap_value = 0;
1012                         ebc0_cs2_bncr_value = 0;
1013                         ebc0_cs3_bnap_value = 0;
1014                         ebc0_cs3_bncr_value = 0;
1015                 } else {
1016                         /* Expansion Slot */
1017                         ebc0_cs1_bnap_value = 0;
1018                         ebc0_cs1_bncr_value = 0;
1019                         ebc0_cs2_bnap_value = 0;
1020                         ebc0_cs2_bncr_value = 0;
1021                         ebc0_cs3_bnap_value = 0;
1022                         ebc0_cs3_bncr_value = 0;
1023                 }
1024
1025                 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
1026                         /* Small Flash */
1027                         ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
1028                         ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
1029                 } else {
1030                         /* Large Flash or SRAM */
1031                         ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
1032                         ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1033                 }
1034
1035                 break;
1036
1037                 /*------------------------------------------------------------------------- */
1038         case BOOT_DEVICE_UNKNOWN:
1039                 /*------------------------------------------------------------------------- */
1040                 /* Error */
1041                 break;
1042
1043         }
1044
1045
1046         /*-------------------------------------------------------------------------+
1047           | Initialize EBC CONFIG
1048           +-------------------------------------------------------------------------*/
1049         mtdcr(ebccfga, xbcfg);
1050         mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN        |
1051               EBC0_CFG_PTD_ENABLED        |
1052               EBC0_CFG_RTC_2048PERCLK     |
1053               EBC0_CFG_EMPL_LOW           |
1054               EBC0_CFG_EMPH_LOW           |
1055               EBC0_CFG_CSTC_DRIVEN        |
1056               EBC0_CFG_BPF_ONEDW          |
1057               EBC0_CFG_EMS_8BIT           |
1058               EBC0_CFG_PME_DISABLED       |
1059               EBC0_CFG_PMT_ENCODE(0)      );
1060
1061         /*-------------------------------------------------------------------------+
1062           | Initialize EBC Bank 0-4
1063           +-------------------------------------------------------------------------*/
1064         /* EBC Bank0 */
1065         mtebc(pb0ap, ebc0_cs0_bnap_value);
1066         mtebc(pb0cr, ebc0_cs0_bncr_value);
1067         /* EBC Bank1 */
1068         mtebc(pb1ap, ebc0_cs1_bnap_value);
1069         mtebc(pb1cr, ebc0_cs1_bncr_value);
1070         /* EBC Bank2 */
1071         mtebc(pb2ap, ebc0_cs2_bnap_value);
1072         mtebc(pb2cr, ebc0_cs2_bncr_value);
1073         /* EBC Bank3 */
1074         mtebc(pb3ap, ebc0_cs3_bnap_value);
1075         mtebc(pb3cr, ebc0_cs3_bncr_value);
1076         /* EBC Bank4 */
1077         mtebc(pb4ap, ebc0_cs4_bnap_value);
1078         mtebc(pb4cr, ebc0_cs4_bncr_value);
1079
1080         return;
1081 }
1082
1083
1084 /*----------------------------------------------------------------------------+
1085   | get_uart_configuration.
1086   +----------------------------------------------------------------------------*/
1087 uart_config_nb_t get_uart_configuration(void)
1088 {
1089         return (L4);
1090 }
1091
1092 /*----------------------------------------------------------------------------+
1093   | set_phy_configuration_through_fpga => to EPLD
1094   +----------------------------------------------------------------------------*/
1095 void set_phy_configuration_through_fpga(zmii_config_t config)
1096 {
1097
1098         unsigned long fpga_selection_reg;
1099
1100         fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1101
1102         switch(config)
1103         {
1104         case ZMII_CONFIGURATION_IS_MII:
1105                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1106                 break;
1107         case ZMII_CONFIGURATION_IS_RMII:
1108                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1109                 break;
1110         case ZMII_CONFIGURATION_IS_SMII:
1111                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1112                 break;
1113         case ZMII_CONFIGURATION_UNKNOWN:
1114         default:
1115                 break;
1116         }
1117         out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1118
1119 }
1120
1121 /*----------------------------------------------------------------------------+
1122   | scp_selection_in_fpga.
1123   +----------------------------------------------------------------------------*/
1124 void scp_selection_in_fpga(void)
1125 {
1126         unsigned long fpga_selection_2_reg;
1127
1128         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1129         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1130         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1131 }
1132
1133 /*----------------------------------------------------------------------------+
1134   | iic1_selection_in_fpga.
1135   +----------------------------------------------------------------------------*/
1136 void iic1_selection_in_fpga(void)
1137 {
1138         unsigned long fpga_selection_2_reg;
1139
1140         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1141         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1142         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1143 }
1144
1145 /*----------------------------------------------------------------------------+
1146   | dma_a_b_selection_in_fpga.
1147   +----------------------------------------------------------------------------*/
1148 void dma_a_b_selection_in_fpga(void)
1149 {
1150         unsigned long fpga_selection_2_reg;
1151
1152         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1153         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1154 }
1155
1156 /*----------------------------------------------------------------------------+
1157   | dma_a_b_unselect_in_fpga.
1158   +----------------------------------------------------------------------------*/
1159 void dma_a_b_unselect_in_fpga(void)
1160 {
1161         unsigned long fpga_selection_2_reg;
1162
1163         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1164         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1165 }
1166
1167 /*----------------------------------------------------------------------------+
1168   | dma_c_d_selection_in_fpga.
1169   +----------------------------------------------------------------------------*/
1170 void dma_c_d_selection_in_fpga(void)
1171 {
1172         unsigned long fpga_selection_2_reg;
1173
1174         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1175         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1176 }
1177
1178 /*----------------------------------------------------------------------------+
1179   | dma_c_d_unselect_in_fpga.
1180   +----------------------------------------------------------------------------*/
1181 void dma_c_d_unselect_in_fpga(void)
1182 {
1183         unsigned long fpga_selection_2_reg;
1184
1185         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1186         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1187 }
1188
1189 /*----------------------------------------------------------------------------+
1190   | usb2_device_selection_in_fpga.
1191   +----------------------------------------------------------------------------*/
1192 void usb2_device_selection_in_fpga(void)
1193 {
1194         unsigned long fpga_selection_1_reg;
1195
1196         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1197         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1198 }
1199
1200 /*----------------------------------------------------------------------------+
1201   | usb2_device_reset_through_fpga.
1202   +----------------------------------------------------------------------------*/
1203 void usb2_device_reset_through_fpga(void)
1204 {
1205         /* Perform soft Reset pulse */
1206         unsigned long fpga_reset_reg;
1207         int i;
1208
1209         fpga_reset_reg = in8(FPGA_RESET_REG);
1210         out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1211         for (i=0; i<500; i++)
1212                 udelay(1000);
1213         out8(FPGA_RESET_REG,fpga_reset_reg);
1214 }
1215
1216 /*----------------------------------------------------------------------------+
1217   | usb2_host_selection_in_fpga.
1218   +----------------------------------------------------------------------------*/
1219 void usb2_host_selection_in_fpga(void)
1220 {
1221         unsigned long fpga_selection_1_reg;
1222
1223         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1224         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1225 }
1226
1227 /*----------------------------------------------------------------------------+
1228   | ndfc_selection_in_fpga.
1229   +----------------------------------------------------------------------------*/
1230 void ndfc_selection_in_fpga(void)
1231 {
1232         unsigned long fpga_selection_1_reg;
1233
1234         fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1235         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1236         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1237         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1238 }
1239
1240 /*----------------------------------------------------------------------------+
1241   | uart_selection_in_fpga.
1242   +----------------------------------------------------------------------------*/
1243 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1244 {
1245         /* FPGA register */
1246         unsigned char   fpga_selection_3_reg;
1247
1248         /* Read FPGA Reagister */
1249         fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1250
1251         switch (uart_config)
1252         {
1253         case L1:
1254                 /* ----------------------------------------------------------------------- */
1255                 /* L1 configuration:    UART0 = 8 pins */
1256                 /* ----------------------------------------------------------------------- */
1257                 /* Configure FPGA */
1258                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1259                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1260                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1261
1262                 break;
1263
1264         case L2:
1265                 /* ----------------------------------------------------------------------- */
1266                 /* L2 configuration:    UART0 = 4 pins */
1267                 /*                      UART1 = 4 pins */
1268                 /* ----------------------------------------------------------------------- */
1269                 /* Configure FPGA */
1270                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1271                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1272                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1273
1274                 break;
1275
1276         case L3:
1277                 /* ----------------------------------------------------------------------- */
1278                 /* L3 configuration:    UART0 = 4 pins */
1279                 /*                      UART1 = 2 pins */
1280                 /*                      UART2 = 2 pins */
1281                 /* ----------------------------------------------------------------------- */
1282                 /* Configure FPGA */
1283                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1284                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1285                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1286                 break;
1287
1288         case L4:
1289                 /* Configure FPGA */
1290                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1291                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1292                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1293
1294                 break;
1295
1296         default:
1297                 /* Unsupported UART configuration number */
1298                 for (;;)
1299                         ;
1300                 break;
1301
1302         }
1303 }
1304
1305
1306 /*----------------------------------------------------------------------------+
1307   | init_default_gpio
1308   +----------------------------------------------------------------------------*/
1309 void init_default_gpio(void)
1310 {
1311         int i;
1312
1313         /* Init GPIO0 */
1314         for(i=0; i<GPIO_MAX; i++)
1315         {
1316                 gpio_tab[GPIO0][i].add    = GPIO0_BASE;
1317                 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1318                 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1319         }
1320
1321         /* Init GPIO1 */
1322         for(i=0; i<GPIO_MAX; i++)
1323         {
1324                 gpio_tab[GPIO1][i].add    = GPIO1_BASE;
1325                 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1326                 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1327         }
1328
1329         /* EBC_CS_N(5) - GPIO0_10 */
1330         gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
1331         gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
1332
1333         /* EBC_CS_N(4) - GPIO0_9 */
1334         gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
1335         gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
1336 }
1337
1338 /*----------------------------------------------------------------------------+
1339   | update_uart_ios
1340   +------------------------------------------------------------------------------
1341   |
1342   | Set UART Configuration in PowerPC440EP
1343   |
1344   | +---------------------------------------------------------------------+
1345   | | Configuartion   |   Connector   | Nb of pins | Pins   | Associated  |
1346   | |    Number       |   Port Name   |  available | naming |   CORE      |
1347   | +-----------------+---------------+------------+--------+-------------+
1348   | |     L1          |   Port_A      |     8      | UART   | UART core 0 |
1349   | +-----------------+---------------+------------+--------+-------------+
1350   | |     L2          |   Port_A      |     4      | UART1  | UART core 0 |
1351   | |    (L2D)        |   Port_B      |     4      | UART2  | UART core 1 |
1352   | +-----------------+---------------+------------+--------+-------------+
1353   | |     L3          |   Port_A      |     4      | UART1  | UART core 0 |
1354   | |    (L3D)        |   Port_B      |     2      | UART2  | UART core 1 |
1355   | |                 |   Port_C      |     2      | UART3  | UART core 2 |
1356   | +-----------------+---------------+------------+--------+-------------+
1357   | |                 |   Port_A      |     2      | UART1  | UART core 0 |
1358   | |     L4          |   Port_B      |     2      | UART2  | UART core 1 |
1359   | |    (L4D)        |   Port_C      |     2      | UART3  | UART core 2 |
1360   | |                 |   Port_D      |     2      | UART4  | UART core 3 |
1361   | +-----------------+---------------+------------+--------+-------------+
1362   |
1363   |  Involved GPIOs
1364   |
1365   | +------------------------------------------------------------------------------+
1366   | |  GPIO   |   Aternate 1     | I/O |  Alternate 2    | I/O | Alternate 3 | I/O |
1367   | +---------+------------------+-----+-----------------+-----+-------------+-----+
1368   | | GPIO1_2 | UART0_DCD_N      |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |  O  |
1369   | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |  I  |
1370   | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA              |  NA | UART3_SIN   |  I  |
1371   | | GPIO1_5 | UART0_RTS_N      |  O  | NA              |  NA | UART3_SOUT  |  O  |
1372   | | GPIO1_6 | UART0_DTR_N      |  O  | UART1_SOUT      |  O  | NA          |  NA |
1373   | | GPIO1_7 | UART0_RI_N       |  I  | UART1_SIN       |  I  | NA          |  NA |
1374   | +------------------------------------------------------------------------------+
1375   |
1376   |
1377   +----------------------------------------------------------------------------*/
1378
1379 void update_uart_ios(uart_config_nb_t uart_config)
1380 {
1381         switch (uart_config)
1382         {
1383         case L1:
1384                 /* ----------------------------------------------------------------------- */
1385                 /* L1 configuration:    UART0 = 8 pins */
1386                 /* ----------------------------------------------------------------------- */
1387                 /* Update GPIO Configuration Table */
1388                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1389                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1390
1391                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1392                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1393
1394                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1395                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1396
1397                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1398                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1399
1400                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1401                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1402
1403                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1404                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1405
1406                 break;
1407
1408         case L2:
1409                 /* ----------------------------------------------------------------------- */
1410                 /* L2 configuration:    UART0 = 4 pins */
1411                 /*                      UART1 = 4 pins */
1412                 /* ----------------------------------------------------------------------- */
1413                 /* Update GPIO Configuration Table */
1414                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1415                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1416
1417                 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1418                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1419
1420                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1421                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1422
1423                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1424                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1425
1426                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1427                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1428
1429                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1430                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1431
1432                 break;
1433
1434         case L3:
1435                 /* ----------------------------------------------------------------------- */
1436                 /* L3 configuration:    UART0 = 4 pins */
1437                 /*                      UART1 = 2 pins */
1438                 /*                      UART2 = 2 pins */
1439                 /* ----------------------------------------------------------------------- */
1440                 /* Update GPIO Configuration Table */
1441                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1442                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1443
1444                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1445                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1446
1447                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1448                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1449
1450                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1451                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1452
1453                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1454                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1455
1456                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1457                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1458
1459                 break;
1460
1461         case L4:
1462                 /* ----------------------------------------------------------------------- */
1463                 /* L4 configuration:    UART0 = 2 pins */
1464                 /*                      UART1 = 2 pins */
1465                 /*                      UART2 = 2 pins */
1466                 /*                      UART3 = 2 pins */
1467                 /* ----------------------------------------------------------------------- */
1468                 /* Update GPIO Configuration Table */
1469                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1470                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1471
1472                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1473                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1474
1475                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1476                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1477
1478                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1479                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1480
1481                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1482                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1483
1484                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1485                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1486
1487                 break;
1488
1489         default:
1490                 /* Unsupported UART configuration number */
1491                 printf("ERROR - Unsupported UART configuration number.\n\n");
1492                 for (;;)
1493                         ;
1494                 break;
1495
1496         }
1497
1498         /* Set input Selection Register on Alt_Receive for UART Input Core */
1499         out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1500         out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1501         out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1502 }
1503
1504 /*----------------------------------------------------------------------------+
1505   | update_ndfc_ios(void).
1506   +----------------------------------------------------------------------------*/
1507 void update_ndfc_ios(void)
1508 {
1509         /* Update GPIO Configuration Table */
1510         gpio_tab[GPIO0][6].in_out = GPIO_OUT;       /* EBC_CS_N(1) */
1511         gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1512
1513 #if 0
1514         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(2) */
1515         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1516
1517         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(3) */
1518         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1519 #endif
1520 }
1521
1522 /*----------------------------------------------------------------------------+
1523   | update_zii_ios(void).
1524   +----------------------------------------------------------------------------*/
1525 void update_zii_ios(void)
1526 {
1527         /* Update GPIO Configuration Table */
1528         gpio_tab[GPIO0][12].in_out = GPIO_IN;       /* ZII_p0Rxd(0) */
1529         gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1530
1531         gpio_tab[GPIO0][13].in_out = GPIO_IN;       /* ZII_p0Rxd(1) */
1532         gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1533
1534         gpio_tab[GPIO0][14].in_out = GPIO_IN;       /* ZII_p0Rxd(2) */
1535         gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1536
1537         gpio_tab[GPIO0][15].in_out = GPIO_IN;       /* ZII_p0Rxd(3) */
1538         gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1539
1540         gpio_tab[GPIO0][16].in_out = GPIO_OUT;      /* ZII_p0Txd(0) */
1541         gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1542
1543         gpio_tab[GPIO0][17].in_out = GPIO_OUT;      /* ZII_p0Txd(1) */
1544         gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1545
1546         gpio_tab[GPIO0][18].in_out = GPIO_OUT;      /* ZII_p0Txd(2) */
1547         gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1548
1549         gpio_tab[GPIO0][19].in_out = GPIO_OUT;      /* ZII_p0Txd(3) */
1550         gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1551
1552         gpio_tab[GPIO0][20].in_out = GPIO_IN;       /* ZII_p0Rx_er */
1553         gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1554
1555         gpio_tab[GPIO0][21].in_out = GPIO_IN;       /* ZII_p0Rx_dv */
1556         gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1557
1558         gpio_tab[GPIO0][22].in_out = GPIO_IN;       /* ZII_p0Crs */
1559         gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1560
1561         gpio_tab[GPIO0][23].in_out = GPIO_OUT;      /* ZII_p0Tx_er */
1562         gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1563
1564         gpio_tab[GPIO0][24].in_out = GPIO_OUT;      /* ZII_p0Tx_en */
1565         gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1566
1567         gpio_tab[GPIO0][25].in_out = GPIO_IN;       /* ZII_p0Col */
1568         gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1569
1570 }
1571
1572 /*----------------------------------------------------------------------------+
1573   | update_uic_0_3_irq_ios().
1574   +----------------------------------------------------------------------------*/
1575 void update_uic_0_3_irq_ios(void)
1576 {
1577         gpio_tab[GPIO1][8].in_out = GPIO_IN;        /* UIC_IRQ(0) */
1578         gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1579
1580         gpio_tab[GPIO1][9].in_out = GPIO_IN;        /* UIC_IRQ(1) */
1581         gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1582
1583         gpio_tab[GPIO1][10].in_out = GPIO_IN;       /* UIC_IRQ(2) */
1584         gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1585
1586         gpio_tab[GPIO1][11].in_out = GPIO_IN;       /* UIC_IRQ(3) */
1587         gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1588 }
1589
1590 /*----------------------------------------------------------------------------+
1591   | update_uic_4_9_irq_ios().
1592   +----------------------------------------------------------------------------*/
1593 void update_uic_4_9_irq_ios(void)
1594 {
1595         gpio_tab[GPIO1][12].in_out = GPIO_IN;       /* UIC_IRQ(4) */
1596         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1597
1598         gpio_tab[GPIO1][13].in_out = GPIO_IN;       /* UIC_IRQ(6) */
1599         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1600
1601         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* UIC_IRQ(7) */
1602         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1603
1604         gpio_tab[GPIO1][15].in_out = GPIO_IN;       /* UIC_IRQ(8) */
1605         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1606
1607         gpio_tab[GPIO1][16].in_out = GPIO_IN;       /* UIC_IRQ(9) */
1608         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1609 }
1610
1611 /*----------------------------------------------------------------------------+
1612   | update_dma_a_b_ios().
1613   +----------------------------------------------------------------------------*/
1614 void update_dma_a_b_ios(void)
1615 {
1616         gpio_tab[GPIO1][12].in_out = GPIO_OUT;      /* DMA_ACK(1) */
1617         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1618
1619         gpio_tab[GPIO1][13].in_out = GPIO_BI;       /* DMA_EOT/TC(1) */
1620         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1621
1622         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* DMA_REQ(0) */
1623         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1624
1625         gpio_tab[GPIO1][15].in_out = GPIO_OUT;      /* DMA_ACK(0) */
1626         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1627
1628         gpio_tab[GPIO1][16].in_out = GPIO_BI;       /* DMA_EOT/TC(0) */
1629         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1630 }
1631
1632 /*----------------------------------------------------------------------------+
1633   | update_dma_c_d_ios().
1634   +----------------------------------------------------------------------------*/
1635 void update_dma_c_d_ios(void)
1636 {
1637         gpio_tab[GPIO0][0].in_out = GPIO_IN;        /* DMA_REQ(2) */
1638         gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1639
1640         gpio_tab[GPIO0][1].in_out = GPIO_OUT;       /* DMA_ACK(2) */
1641         gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1642
1643         gpio_tab[GPIO0][2].in_out = GPIO_BI;        /* DMA_EOT/TC(2) */
1644         gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1645
1646         gpio_tab[GPIO0][3].in_out = GPIO_IN;        /* DMA_REQ(3) */
1647         gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1648
1649         gpio_tab[GPIO0][4].in_out = GPIO_OUT;       /* DMA_ACK(3) */
1650         gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1651
1652         gpio_tab[GPIO0][5].in_out = GPIO_BI;        /* DMA_EOT/TC(3) */
1653         gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1654
1655 }
1656
1657 /*----------------------------------------------------------------------------+
1658   | update_ebc_master_ios().
1659   +----------------------------------------------------------------------------*/
1660 void update_ebc_master_ios(void)
1661 {
1662         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* EXT_EBC_REQ */
1663         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1664
1665         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1666         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1667
1668         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* EBC_EXT_ACK */
1669         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1670
1671         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* EBC_EXR_BUSREQ */
1672         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1673 }
1674
1675 /*----------------------------------------------------------------------------+
1676   | update_usb2_device_ios().
1677   +----------------------------------------------------------------------------*/
1678 void update_usb2_device_ios(void)
1679 {
1680         gpio_tab[GPIO0][26].in_out = GPIO_IN;       /* USB2D_RXVALID */
1681         gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1682
1683         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* USB2D_RXERROR */
1684         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1685
1686         gpio_tab[GPIO0][28].in_out = GPIO_OUT;      /* USB2D_TXVALID */
1687         gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1688
1689         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* USB2D_PAD_SUSPNDM */
1690         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1691
1692         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* USB2D_XCVRSELECT */
1693         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1694
1695         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* USB2D_TERMSELECT */
1696         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1697
1698         gpio_tab[GPIO1][0].in_out = GPIO_OUT;       /* USB2D_OPMODE0 */
1699         gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1700
1701         gpio_tab[GPIO1][1].in_out = GPIO_OUT;       /* USB2D_OPMODE1 */
1702         gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1703
1704 }
1705
1706 /*----------------------------------------------------------------------------+
1707   | update_pci_patch_ios().
1708   +----------------------------------------------------------------------------*/
1709 void update_pci_patch_ios(void)
1710 {
1711         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1712         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1713 }
1714
1715 /*----------------------------------------------------------------------------+
1716   |   set_chip_gpio_configuration(unsigned char gpio_core)
1717   |   Put the core impacted by clock modification and sharing in reset.
1718   |   Config the select registers to resolve the sharing depending of the config.
1719   |   Configure the GPIO registers.
1720   |
1721   +----------------------------------------------------------------------------*/
1722 void set_chip_gpio_configuration(unsigned char gpio_core)
1723 {
1724         unsigned char i=0, j=0, reg_offset = 0;
1725         unsigned long gpio_reg, gpio_core_add;
1726
1727         /* GPIO config of the GPIOs 0 to 31 */
1728         for (i=0; i<GPIO_MAX; i++, j++)
1729         {
1730                 if (i == GPIO_MAX/2)
1731                 {
1732                         reg_offset = 4;
1733                         j = i-16;
1734                 }
1735
1736                 gpio_core_add = gpio_tab[gpio_core][i].add;
1737
1738                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1739                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1740                 {
1741                         switch (gpio_tab[gpio_core][i].alt_nb)
1742                         {
1743                         case GPIO_SEL:
1744                                 break;
1745
1746                         case GPIO_ALT1:
1747                                 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1748                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1749                                 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1750                                 break;
1751
1752                         case GPIO_ALT2:
1753                                 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1754                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1755                                 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1756                                 break;
1757
1758                         case GPIO_ALT3:
1759                                 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1760                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1761                                 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1762                                 break;
1763                         }
1764                 }
1765                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1766                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1767                 {
1768
1769                         switch (gpio_tab[gpio_core][i].alt_nb)
1770                         {
1771                         case GPIO_SEL:
1772                                 break;
1773                         case GPIO_ALT1:
1774                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1775                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1776                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1777                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1778                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1779                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1780                                 break;
1781                         case GPIO_ALT2:
1782                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1783                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1784                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1785                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1786                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1787                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1788                                 break;
1789                         case GPIO_ALT3:
1790                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1791                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1792                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1793                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1794                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1795                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1796                                 break;
1797                         }
1798                 }
1799         }
1800 }
1801
1802 /*----------------------------------------------------------------------------+
1803   | force_bup_core_selection.
1804   +----------------------------------------------------------------------------*/
1805 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1806 {
1807         /* Pointer invalid */
1808         if (core_select_P == NULL)
1809         {
1810                 printf("Configuration invalid pointer 1\n");
1811                 for (;;)
1812                         ;
1813         }
1814
1815         /* L4 Selection */
1816         *(core_select_P+UART_CORE0)            = CORE_SELECTED;
1817         *(core_select_P+UART_CORE1)            = CORE_SELECTED;
1818         *(core_select_P+UART_CORE2)            = CORE_SELECTED;
1819         *(core_select_P+UART_CORE3)            = CORE_SELECTED;
1820
1821         /* RMII Selection */
1822         *(core_select_P+RMII_SEL)               = CORE_SELECTED;
1823
1824         /* External Interrupt 0-9 selection */
1825         *(core_select_P+UIC_0_3)                = CORE_SELECTED;
1826         *(core_select_P+UIC_4_9)                = CORE_SELECTED;
1827
1828         *(core_select_P+SCP_CORE)               = CORE_SELECTED;
1829         *(core_select_P+DMA_CHANNEL_CD)         = CORE_SELECTED;
1830         *(core_select_P+PACKET_REJ_FUNC_AVAIL)  = CORE_SELECTED;
1831         *(core_select_P+USB1_DEVICE)            = CORE_SELECTED;
1832
1833         if (is_nand_selected()) {
1834                 *(core_select_P+NAND_FLASH)     = CORE_SELECTED;
1835         }
1836
1837         *config_val_P = CONFIG_IS_VALID;
1838
1839 }
1840
1841 /*----------------------------------------------------------------------------+
1842   | configure_ppc440ep_pins.
1843   +----------------------------------------------------------------------------*/
1844 void configure_ppc440ep_pins(void)
1845 {
1846         uart_config_nb_t uart_configuration;
1847         config_validity_t config_val = CONFIG_IS_INVALID;
1848
1849         /* Create Core Selection Table */
1850         core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1851                 {
1852                         CORE_NOT_SELECTED,      /* IIC_CORE, */
1853                         CORE_NOT_SELECTED,      /* SPC_CORE, */
1854                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_AB, */
1855                         CORE_NOT_SELECTED,      /* UIC_4_9, */
1856                         CORE_NOT_SELECTED,      /* USB2_HOST, */
1857                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_CD, */
1858                         CORE_NOT_SELECTED,      /* USB2_DEVICE, */
1859                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_AVAIL, */
1860                         CORE_NOT_SELECTED,      /* USB1_DEVICE, */
1861                         CORE_NOT_SELECTED,      /* EBC_MASTER, */
1862                         CORE_NOT_SELECTED,      /* NAND_FLASH, */
1863                         CORE_NOT_SELECTED,      /* UART_CORE0, */
1864                         CORE_NOT_SELECTED,      /* UART_CORE1, */
1865                         CORE_NOT_SELECTED,      /* UART_CORE2, */
1866                         CORE_NOT_SELECTED,      /* UART_CORE3, */
1867                         CORE_NOT_SELECTED,      /* MII_SEL, */
1868                         CORE_NOT_SELECTED,      /* RMII_SEL, */
1869                         CORE_NOT_SELECTED,      /* SMII_SEL, */
1870                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_EN */
1871                         CORE_NOT_SELECTED,      /* UIC_0_3 */
1872                         CORE_NOT_SELECTED,      /* USB1_HOST */
1873                         CORE_NOT_SELECTED       /* PCI_PATCH */
1874                 };
1875
1876
1877         /* Table Default Initialisation + FPGA Access */
1878         init_default_gpio();
1879         set_chip_gpio_configuration(GPIO0);
1880         set_chip_gpio_configuration(GPIO1);
1881
1882         /* Update Table */
1883         force_bup_core_selection(ppc440ep_core_selection, &config_val);
1884 #if 0 /* test-only */
1885         /* If we are running PIBS 1, force known configuration */
1886         update_core_selection_table(ppc440ep_core_selection, &config_val);
1887 #endif
1888
1889         /*----------------------------------------------------------------------------+
1890           | SDR + ios table update + fpga initialization
1891           +----------------------------------------------------------------------------*/
1892         unsigned long sdr0_pfc1     = 0;
1893         unsigned long sdr0_usb0     = 0;
1894         unsigned long sdr0_mfr      = 0;
1895
1896         /* PCI Always selected */
1897
1898         /* I2C Selection */
1899         if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1900         {
1901                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1902                 iic1_selection_in_fpga();
1903         }
1904
1905         /* SCP Selection */
1906         if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1907         {
1908                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1909                 scp_selection_in_fpga();
1910         }
1911
1912         /* UIC 0:3 Selection */
1913         if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1914         {
1915                 update_uic_0_3_irq_ios();
1916                 dma_a_b_unselect_in_fpga();
1917         }
1918
1919         /* UIC 4:9 Selection */
1920         if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1921         {
1922                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1923                 update_uic_4_9_irq_ios();
1924         }
1925
1926         /* DMA AB Selection */
1927         if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1928         {
1929                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1930                 update_dma_a_b_ios();
1931                 dma_a_b_selection_in_fpga();
1932         }
1933
1934         /* DMA CD Selection */
1935         if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1936         {
1937                 update_dma_c_d_ios();
1938                 dma_c_d_selection_in_fpga();
1939         }
1940
1941         /* EBC Master Selection */
1942         if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1943         {
1944                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1945                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1946                 update_ebc_master_ios();
1947         }
1948
1949         /* PCI Patch Enable */
1950         if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1951         {
1952                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1953                 update_pci_patch_ios();
1954         }
1955
1956         /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1957         if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1958         {
1959                 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1960                 printf("Invalid configuration => USB2 Host selected\n");
1961                 for (;;)
1962                         ;
1963                 /*usb2_host_selection_in_fpga(); */
1964         }
1965
1966         /* USB2.0 Device Selection */
1967         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1968         {
1969                 update_usb2_device_ios();
1970                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1971                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1972
1973                 mfsdr(sdr_usb0, sdr0_usb0);
1974                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1975                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1976                 mtsdr(sdr_usb0, sdr0_usb0);
1977
1978                 usb2_device_selection_in_fpga();
1979         }
1980
1981         /* USB1.1 Device Selection */
1982         if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1983         {
1984                 mfsdr(sdr_usb0, sdr0_usb0);
1985                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1986                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1987                 mtsdr(sdr_usb0, sdr0_usb0);
1988         }
1989
1990         /* USB1.1 Host Selection */
1991         if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1992         {
1993                 mfsdr(sdr_usb0, sdr0_usb0);
1994                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1995                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1996                 mtsdr(sdr_usb0, sdr0_usb0);
1997         }
1998
1999         /* NAND Flash Selection */
2000         if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
2001         {
2002                 update_ndfc_ios();
2003
2004                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
2005                       SDR0_CUST0_NDFC_ENABLE    |
2006                       SDR0_CUST0_NDFC_BW_8_BIT  |
2007                       SDR0_CUST0_NDFC_ARE_MASK  |
2008                       SDR0_CUST0_CHIPSELGAT_EN1 |
2009                       SDR0_CUST0_CHIPSELGAT_EN2);
2010
2011                 ndfc_selection_in_fpga();
2012         }
2013         else
2014         {
2015                 /* Set Mux on EMAC */
2016                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
2017         }
2018
2019         /* MII Selection */
2020         if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
2021         {
2022                 update_zii_ios();
2023                 mfsdr(sdr_mfr, sdr0_mfr);
2024                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
2025                 mtsdr(sdr_mfr, sdr0_mfr);
2026
2027                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
2028         }
2029
2030         /* RMII Selection */
2031         if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
2032         {
2033                 update_zii_ios();
2034                 mfsdr(sdr_mfr, sdr0_mfr);
2035                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
2036                 mtsdr(sdr_mfr, sdr0_mfr);
2037
2038                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
2039         }
2040
2041         /* SMII Selection */
2042         if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
2043         {
2044                 update_zii_ios();
2045                 mfsdr(sdr_mfr, sdr0_mfr);
2046                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2047                 mtsdr(sdr_mfr, sdr0_mfr);
2048
2049                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2050         }
2051
2052         /* UART Selection */
2053         uart_configuration = get_uart_configuration();
2054         switch (uart_configuration)
2055         {
2056         case L1:         /* L1 Selection */
2057                 /* UART0 8 pins Only */
2058                 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
2059                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;   /* Chip Pb */
2060                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2061                 break;
2062         case L2:         /* L2 Selection */
2063                 /* UART0 and UART1 4 pins */
2064                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2065                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2066                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2067                 break;
2068         case L3:         /* L3 Selection */
2069                 /* UART0 4 pins, UART1 and UART2 2 pins */
2070                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2071                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2072                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2073                 break;
2074         case L4:         /* L4 Selection */
2075                 /* UART0, UART1, UART2 and UART3 2 pins */
2076                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2077                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2078                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2079                 break;
2080         }
2081         update_uart_ios(uart_configuration);
2082
2083         /* UART Selection in all cases */
2084         uart_selection_in_fpga(uart_configuration);
2085
2086         /* Packet Reject Function Available */
2087         if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2088         {
2089                 /* Set UPR Bit in SDR0_PFC1 Register */
2090                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2091         }
2092
2093         /* Packet Reject Function Enable */
2094         if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2095         {
2096                 mfsdr(sdr_mfr, sdr0_mfr);
2097                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2098                 mtsdr(sdr_mfr, sdr0_mfr);
2099         }
2100
2101         /* Perform effective access to hardware */
2102         mtsdr(sdr_pfc1, sdr0_pfc1);
2103         set_chip_gpio_configuration(GPIO0);
2104         set_chip_gpio_configuration(GPIO1);
2105
2106         /* USB2.0 Device Reset must be done after GPIO setting */
2107         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2108                 usb2_device_reset_through_fpga();
2109
2110 }