board/amcc/bamboo/bamboo.c

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/gpio.h>
  27 #include <spd_sdram.h>
  28 #include <ppc440.h>
  29 #include "bamboo.h"
  30
  31 void ext_bus_cntlr_init(void);
  32 void configure_ppc440ep_pins(void);
  33 int is_nand_selected(void);
  34
  35 unsigned char cfg_simulate_spd_eeprom[128];
  36
  37 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  38 #if 0
  39 {          /* GPIO   Alternate1       Alternate2        Alternate3 */
  40     {
  41         /* GPIO Core 0 */
  42         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0  -> EBC_ADDR(7)      DMA_REQ(2) */
  43         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1  -> EBC_ADDR(6)      DMA_ACK(2) */
  44         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2  -> EBC_ADDR(5)      DMA_EOT/TC(2) */
  45         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3  -> EBC_ADDR(4)      DMA_REQ(3) */
  46         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4  -> EBC_ADDR(3)      DMA_ACK(3) */
  47         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  48         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6  -> EBC_CS_N(1) */
  49         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7  -> EBC_CS_N(2) */
  50         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8  -> EBC_CS_N(3) */
  51         { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9  -> EBC_CS_N(4) */
  52         { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  53         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  54         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  55         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  56         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  57         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  58         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  59         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  60         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  61         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  62         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  63         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  64         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  65         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  66         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  67         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  68         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->                  USB2D_RXVALID */
  69         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ      USB2D_RXERROR */
  70         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->                  USB2D_TXVALID */
  71         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA     USB2D_PAD_SUSPNDM */
  72         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK      USB2D_XCVRSELECT */
  73         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
  74     },
  75     {
  76         /* GPIO Core 1 */
  77         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0  -> USB2D_OPMODE0 */
  78         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1  -> USB2D_OPMODE1 */
  79         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2  -> UART0_DCD_N      UART1_DSR_CTS_N   UART2_SOUT */
  80         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3  -> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
  81         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4  -> UART0_8PIN_CTS_N                   UART3_SIN */
  82         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5  -> UART0_RTS_N */
  83         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6  -> UART0_DTR_N      UART1_SOUT */
  84         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7  -> UART0_RI_N       UART1_SIN */
  85         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8  -> UIC_IRQ(0) */
  86         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9  -> UIC_IRQ(1) */
  87         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  88         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  89         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)       DMA_ACK(1) */
  90         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)       DMA_EOT/TC(1) */
  91         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)       DMA_REQ(0) */
  92         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)       DMA_ACK(0) */
  93         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)       DMA_EOT/TC(0) */
  94         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  95         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
  96         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
  97         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
  98         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
  99         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
 100         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \     Can be unselected thru TraceSelect Bit */
 101         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /        in PowerPC440EP Chip */
 102         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
 103         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
 104         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
 105         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
 106         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
 107         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
 108         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
 109     }
 110 };
 111 #endif
 112
 113 /*----------------------------------------------------------------------------+
 114   | EBC Devices Characteristics
 115   |   Peripheral Bank Access Parameters       -   EBC0_BnAP
 116   |   Peripheral Bank Configuration Register  -   EBC0_BnCR
 117   +----------------------------------------------------------------------------*/
 118 /* Small Flash */
 119 #define EBC0_BNAP_SMALL_FLASH                           \
 120         EBC0_BNAP_BME_DISABLED                  |       \
 121         EBC0_BNAP_TWT_ENCODE(6)                 |       \
 122         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 123         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 124         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 125         EBC0_BNAP_WBF_ENCODE(3)                 |       \
 126         EBC0_BNAP_TH_ENCODE(1)                  |       \
 127         EBC0_BNAP_RE_ENABLED                    |       \
 128         EBC0_BNAP_SOR_DELAYED                   |       \
 129         EBC0_BNAP_BEM_WRITEONLY                 |       \
 130         EBC0_BNAP_PEN_DISABLED
 131
 132 #define EBC0_BNCR_SMALL_FLASH_CS0                       \
 133         EBC0_BNCR_BAS_ENCODE(0xFFF00000)        |       \
 134         EBC0_BNCR_BS_1MB                        |       \
 135         EBC0_BNCR_BU_RW                         |       \
 136         EBC0_BNCR_BW_8BIT
 137
 138 #define EBC0_BNCR_SMALL_FLASH_CS4                       \
 139         EBC0_BNCR_BAS_ENCODE(0x87F00000)        |       \
 140         EBC0_BNCR_BS_1MB                        |       \
 141         EBC0_BNCR_BU_RW                         |       \
 142         EBC0_BNCR_BW_8BIT
 143
 144 /* Large Flash or SRAM */
 145 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM                   \
 146         EBC0_BNAP_BME_DISABLED                  |       \
 147         EBC0_BNAP_TWT_ENCODE(8)                 |       \
 148         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 149         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 150         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 151         EBC0_BNAP_WBF_ENCODE(1)                 |       \
 152         EBC0_BNAP_TH_ENCODE(2)                  |       \
 153         EBC0_BNAP_SOR_DELAYED                   |       \
 154         EBC0_BNAP_BEM_RW                        |       \
 155         EBC0_BNAP_PEN_DISABLED
 156
 157 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0               \
 158         EBC0_BNCR_BAS_ENCODE(0xFF800000)        |       \
 159         EBC0_BNCR_BS_8MB                        |       \
 160         EBC0_BNCR_BU_RW                         |       \
 161         EBC0_BNCR_BW_16BIT
 162
 163
 164 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4               \
 165         EBC0_BNCR_BAS_ENCODE(0x87800000)        |       \
 166         EBC0_BNCR_BS_8MB                        |       \
 167         EBC0_BNCR_BU_RW                         |       \
 168         EBC0_BNCR_BW_16BIT
 169
 170 /* NVRAM - FPGA */
 171 #define EBC0_BNAP_NVRAM_FPGA                            \
 172         EBC0_BNAP_BME_DISABLED                  |       \
 173         EBC0_BNAP_TWT_ENCODE(9)                 |       \
 174         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 175         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 176         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 177         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 178         EBC0_BNAP_TH_ENCODE(2)                  |       \
 179         EBC0_BNAP_RE_ENABLED                    |       \
 180         EBC0_BNAP_SOR_DELAYED                   |       \
 181         EBC0_BNAP_BEM_WRITEONLY                 |       \
 182         EBC0_BNAP_PEN_DISABLED
 183
 184 #define EBC0_BNCR_NVRAM_FPGA_CS5                        \
 185         EBC0_BNCR_BAS_ENCODE(0x80000000)        |       \
 186         EBC0_BNCR_BS_1MB                        |       \
 187         EBC0_BNCR_BU_RW                         |       \
 188         EBC0_BNCR_BW_8BIT
 189
 190 /* Nand Flash */
 191 #define EBC0_BNAP_NAND_FLASH                            \
 192         EBC0_BNAP_BME_DISABLED                  |       \
 193         EBC0_BNAP_TWT_ENCODE(3)                 |       \
 194         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 195         EBC0_BNAP_OEN_ENCODE(0)                 |       \
 196         EBC0_BNAP_WBN_ENCODE(0)                 |       \
 197         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 198         EBC0_BNAP_TH_ENCODE(1)                  |       \
 199         EBC0_BNAP_RE_ENABLED                    |       \
 200         EBC0_BNAP_SOR_NOT_DELAYED               |       \
 201         EBC0_BNAP_BEM_RW                        |       \
 202         EBC0_BNAP_PEN_DISABLED
 203
 204
 205 #define EBC0_BNCR_NAND_FLASH_CS0        0xB8400000
 206
 207 /* NAND0 */
 208 #define EBC0_BNCR_NAND_FLASH_CS1                        \
 209         EBC0_BNCR_BAS_ENCODE(0x90000000)        |       \
 210         EBC0_BNCR_BS_1MB                        |       \
 211         EBC0_BNCR_BU_RW                         |       \
 212         EBC0_BNCR_BW_32BIT
 213 /* NAND1 - Bank2 */
 214 #define EBC0_BNCR_NAND_FLASH_CS2                        \
 215         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 216         EBC0_BNCR_BS_1MB                        |       \
 217         EBC0_BNCR_BU_RW                         |       \
 218         EBC0_BNCR_BW_32BIT
 219
 220 /* NAND1 - Bank3 */
 221 #define EBC0_BNCR_NAND_FLASH_CS3                        \
 222         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 223         EBC0_BNCR_BS_1MB                        |       \
 224         EBC0_BNCR_BU_RW                         |       \
 225         EBC0_BNCR_BW_32BIT
 226
 227 int board_early_init_f(void)
 228 {
 229         ext_bus_cntlr_init();
 230
 231         /*--------------------------------------------------------------------
 232          * Setup the interrupt controller polarities, triggers, etc.
 233          *-------------------------------------------------------------------*/
 234         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 235         mtdcr(uic0er, 0x00000000);      /* disable all */
 236         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
 237         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 238         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 239         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 240         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 241
 242         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 243         mtdcr(uic1er, 0x00000000);      /* disable all */
 244         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 245         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 246         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 247         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 248         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 249
 250         /*--------------------------------------------------------------------
 251          * Setup the GPIO pins
 252          *-------------------------------------------------------------------*/
 253         out32(GPIO0_OSRL,  0x00000400);
 254         out32(GPIO0_OSRH,  0x00000000);
 255         out32(GPIO0_TSRL,  0x00000400);
 256         out32(GPIO0_TSRH,  0x00000000);
 257         out32(GPIO0_ISR1L, 0x00000000);
 258         out32(GPIO0_ISR1H, 0x00000000);
 259         out32(GPIO0_ISR2L, 0x00000000);
 260         out32(GPIO0_ISR2H, 0x00000000);
 261         out32(GPIO0_ISR3L, 0x00000000);
 262         out32(GPIO0_ISR3H, 0x00000000);
 263
 264         out32(GPIO1_OSRL,  0x0C380000);
 265         out32(GPIO1_OSRH,  0x00000000);
 266         out32(GPIO1_TSRL,  0x0C380000);
 267         out32(GPIO1_TSRH,  0x00000000);
 268         out32(GPIO1_ISR1L, 0x0FC30000);
 269         out32(GPIO1_ISR1H, 0x00000000);
 270         out32(GPIO1_ISR2L, 0x0C010000);
 271         out32(GPIO1_ISR2H, 0x00000000);
 272         out32(GPIO1_ISR3L, 0x01400000);
 273         out32(GPIO1_ISR3H, 0x00000000);
 274
 275         configure_ppc440ep_pins();
 276
 277         return 0;
 278 }
 279
 280 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 281 #include <linux/mtd/nand_legacy.h>
 282 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 283
 284 /*----------------------------------------------------------------------------+
 285   | nand_reset.
 286   |   Reset Nand flash
 287   |   This routine will abort previous cmd
 288   +----------------------------------------------------------------------------*/
 289 int nand_reset(ulong addr)
 290 {
 291         int wait=0, stat=0;
 292
 293         out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
 294         out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
 295
 296         while ((stat != 0xc0) && (wait != 0xffff)) {
 297                 stat = in8(addr + NAND_DATA_REG);
 298                 wait++;
 299         }
 300
 301         if (stat == 0xc0) {
 302                 return 0;
 303         } else {
 304                 printf("NAND Reset timeout.\n");
 305                 return -1;
 306         }
 307 }
 308
 309 void board_nand_set_device(int cs, ulong addr)
 310 {
 311         /* Set NandFlash Core Configuration Register */
 312         out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
 313
 314         switch (cs) {
 315         case 1:
 316                 /* -------
 317                  *  NAND0
 318                  * -------
 319                  * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
 320                  * Set NDF1CR - Enable External CS1 in NAND FLASH controller
 321                  */
 322                 out32(addr + NAND_CR1_REG, 0x80002222);
 323                 break;
 324
 325         case 2:
 326                 /* -------
 327                  *  NAND1
 328                  * -------
 329                  * K9K2G0B : 5 addr cyc, 2 col + 3 Row
 330                  * Set NDF2CR : Enable External CS2 in NAND FLASH controller
 331                  */
 332                 out32(addr + NAND_CR2_REG, 0xC0007777);
 333                 break;
 334         }
 335
 336         /* Perform Reset Command */
 337         if (nand_reset(addr) != 0)
 338                 return;
 339 }
 340
 341 void nand_init(void)
 342 {
 343         board_nand_set_device(1, CFG_NAND_ADDR);
 344
 345         nand_probe(CFG_NAND_ADDR);
 346         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 347                 print_size(nand_dev_desc[0].totlen, "\n");
 348         }
 349
 350 #if 0 /* NAND1 not supported yet */
 351         board_nand_set_device(2, CFG_NAND2_ADDR);
 352
 353         nand_probe(CFG_NAND2_ADDR);
 354         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 355                 print_size(nand_dev_desc[0].totlen, "\n");
 356         }
 357 #endif
 358 }
 359 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
 360
 361 int checkboard(void)
 362 {
 363         char *s = getenv("serial#");
 364
 365         printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
 366         if (s != NULL) {
 367                 puts(", serial# ");
 368                 puts(s);
 369         }
 370         putc('\n');
 371
 372         return (0);
 373 }
 374
 375 /*************************************************************************
 376  *
 377  * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
 378  *
 379  * Fixed memory is composed of :
 380  *      MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
 381  *      13 row add bits, 10 column add bits (but 12 row used only).
 382  *      ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
 383  *      12 row add bits, 10 column add bits.
 384  *      Prepare a subset (only the used ones) of SPD data
 385  *
 386  *      Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
 387  *      the corresponding bank is divided by 2 due to number of Row addresses
 388  *      12 in the ECC module
 389  *
 390  *  Assumes:    64 MB, ECC, non-registered
 391  *              PLB @ 133 MHz
 392  *
 393  ************************************************************************/
 394 static void init_spd_array(void)
 395 {
 396         cfg_simulate_spd_eeprom[8]     = 0x04;    /* 2.5 Volt */
 397         cfg_simulate_spd_eeprom[2]     = 0x07;    /* DDR ram */
 398
 399 #ifdef CONFIG_DDR_ECC
 400         cfg_simulate_spd_eeprom[11]    = 0x02;    /* ECC ON : 02 OFF : 00 */
 401         cfg_simulate_spd_eeprom[31]    = 0x08;    /* bankSizeID: 32MB */
 402         cfg_simulate_spd_eeprom[3]     = 0x0C;    /* num Row Addr: 12 */
 403 #else
 404         cfg_simulate_spd_eeprom[11]    = 0x00;    /* ECC ON : 02 OFF : 00 */
 405         cfg_simulate_spd_eeprom[31]    = 0x10;    /* bankSizeID: 64MB */
 406         cfg_simulate_spd_eeprom[3]     = 0x0D;    /* num Row Addr: 13 */
 407 #endif
 408
 409         cfg_simulate_spd_eeprom[4]     = 0x09;    /* numColAddr: 9  */
 410         cfg_simulate_spd_eeprom[5]     = 0x01;    /* numBanks: 1 */
 411         cfg_simulate_spd_eeprom[0]     = 0x80;    /* number of SPD bytes used: 128 */
 412         cfg_simulate_spd_eeprom[1]     = 0x08;    /*  total number bytes in SPD device = 256 */
 413         cfg_simulate_spd_eeprom[21]    = 0x00;    /* not registered: 0  registered : 0x02*/
 414         cfg_simulate_spd_eeprom[6]     = 0x20;    /* Module data width: 32 bits */
 415         cfg_simulate_spd_eeprom[7]     = 0x00;    /* Module data width continued: +0 */
 416         cfg_simulate_spd_eeprom[15]    = 0x01;    /* wcsbc = 1 */
 417         cfg_simulate_spd_eeprom[27]    = 0x50;    /* tRpNs = 20 ns  */
 418         cfg_simulate_spd_eeprom[29]    = 0x50;    /* tRcdNs = 20 ns */
 419
 420         cfg_simulate_spd_eeprom[30]    = 45;      /* tRasNs */
 421
 422         cfg_simulate_spd_eeprom[18]    = 0x0C;    /* casBit (2,2.5) */
 423
 424         cfg_simulate_spd_eeprom[9]     = 0x75;    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
 425         cfg_simulate_spd_eeprom[23]    = 0xA0;    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
 426         cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
 427         cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */
 428 }
 429
 430 long int initdram (int board_type)
 431 {
 432         long dram_size = 0;
 433
 434         /*
 435          * First write simulated values in eeprom array for onboard bank 0
 436          */
 437         init_spd_array();
 438
 439         dram_size = spd_sdram();
 440
 441         return dram_size;
 442 }
 443
 444 #if defined(CFG_DRAM_TEST)
 445 int testdram(void)
 446 {
 447         unsigned long *mem = (unsigned long *)0;
 448         const unsigned long kend = (1024 / sizeof(unsigned long));
 449         unsigned long k, n;
 450
 451         mtmsr(0);
 452
 453         for (k = 0; k < CFG_KBYTES_SDRAM;
 454              ++k, mem += (1024 / sizeof(unsigned long))) {
 455                 if ((k & 1023) == 0) {
 456                         printf("%3d MB\r", k / 1024);
 457                 }
 458
 459                 memset(mem, 0xaaaaaaaa, 1024);
 460                 for (n = 0; n < kend; ++n) {
 461                         if (mem[n] != 0xaaaaaaaa) {
 462                                 printf("SDRAM test fails at: %08x\n",
 463                                        (uint) & mem[n]);
 464                                 return 1;
 465                         }
 466                 }
 467
 468                 memset(mem, 0x55555555, 1024);
 469                 for (n = 0; n < kend; ++n) {
 470                         if (mem[n] != 0x55555555) {
 471                                 printf("SDRAM test fails at: %08x\n",
 472                                        (uint) & mem[n]);
 473                                 return 1;
 474                         }
 475                 }
 476         }
 477         printf("SDRAM test passes\n");
 478         return 0;
 479 }
 480 #endif
 481
 482 /*************************************************************************
 483  *  pci_pre_init
 484  *
 485  *  This routine is called just prior to registering the hose and gives
 486  *  the board the opportunity to check things. Returning a value of zero
 487  *  indicates that things are bad & PCI initialization should be aborted.
 488  *
 489  *      Different boards may wish to customize the pci controller structure
 490  *      (add regions, override default access routines, etc) or perform
 491  *      certain pre-initialization actions.
 492  *
 493  ************************************************************************/
 494 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 495 int pci_pre_init(struct pci_controller *hose)
 496 {
 497         unsigned long addr;
 498
 499         /*-------------------------------------------------------------------------+
 500           | Set priority for all PLB3 devices to 0.
 501           | Set PLB3 arbiter to fair mode.
 502           +-------------------------------------------------------------------------*/
 503         mfsdr(sdr_amp1, addr);
 504         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 505         addr = mfdcr(plb3_acr);
 506         mtdcr(plb3_acr, addr | 0x80000000);
 507
 508         /*-------------------------------------------------------------------------+
 509           | Set priority for all PLB4 devices to 0.
 510           +-------------------------------------------------------------------------*/
 511         mfsdr(sdr_amp0, addr);
 512         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 513         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 514         mtdcr(plb4_acr, addr);
 515
 516         /*-------------------------------------------------------------------------+
 517           | Set Nebula PLB4 arbiter to fair mode.
 518           +-------------------------------------------------------------------------*/
 519         /* Segment0 */
 520         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 521         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 522         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 523         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 524         mtdcr(plb0_acr, addr);
 525
 526         /* Segment1 */
 527         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 528         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 529         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 530         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 531         mtdcr(plb1_acr, addr);
 532
 533         return 1;
 534 }
 535 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 536
 537 /*************************************************************************
 538  *  pci_target_init
 539  *
 540  *      The bootstrap configuration provides default settings for the pci
 541  *      inbound map (PIM). But the bootstrap config choices are limited and
 542  *      may not be sufficient for a given board.
 543  *
 544  ************************************************************************/
 545 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 546 void pci_target_init(struct pci_controller *hose)
 547 {
 548         /*--------------------------------------------------------------------------+
 549          * Set up Direct MMIO registers
 550          *--------------------------------------------------------------------------*/
 551         /*--------------------------------------------------------------------------+
 552           | PowerPC440 EP PCI Master configuration.
 553           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 554           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 555           |   Use byte reversed out routines to handle endianess.
 556           | Make this region non-prefetchable.
 557           +--------------------------------------------------------------------------*/
 558         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 559         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 560         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 561         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 562         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 563
 564         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 565         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 566         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 567         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 568         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 569
 570         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 571         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 572         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 573         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 574
 575         /*--------------------------------------------------------------------------+
 576          * Set up Configuration registers
 577          *--------------------------------------------------------------------------*/
 578
 579         /* Program the board's subsystem id/vendor id */
 580         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 581                               CFG_PCI_SUBSYS_VENDORID);
 582         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 583
 584         /* Configure command register as bus master */
 585         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 586
 587         /* 240nS PCI clock */
 588         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 589
 590         /* No error reporting */
 591         pci_write_config_word(0, PCI_ERREN, 0);
 592
 593         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 594
 595 }
 596 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 597
 598 /*************************************************************************
 599  *  pci_master_init
 600  *
 601  ************************************************************************/
 602 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 603 void pci_master_init(struct pci_controller *hose)
 604 {
 605         unsigned short temp_short;
 606
 607         /*--------------------------------------------------------------------------+
 608           | Write the PowerPC440 EP PCI Configuration regs.
 609           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 610           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 611           +--------------------------------------------------------------------------*/
 612         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 613         pci_write_config_word(0, PCI_COMMAND,
 614                               temp_short | PCI_COMMAND_MASTER |
 615                               PCI_COMMAND_MEMORY);
 616 }
 617 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 618
 619 /*************************************************************************
 620  *  is_pci_host
 621  *
 622  *      This routine is called to determine if a pci scan should be
 623  *      performed. With various hardware environments (especially cPCI and
 624  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 625  *      bit in the strap register, or generic host/adapter assumptions.
 626  *
 627  *      Rather than hard-code a bad assumption in the general 440 code, the
 628  *      440 pci code requires the board to decide at runtime.
 629  *
 630  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 631  *
 632  *
 633  ************************************************************************/
 634 #if defined(CONFIG_PCI)
 635 int is_pci_host(struct pci_controller *hose)
 636 {
 637         /* Bamboo is always configured as host. */
 638         return (1);
 639 }
 640 #endif                          /* defined(CONFIG_PCI) */
 641
 642 /*----------------------------------------------------------------------------+
 643   | is_powerpc440ep_pass1.
 644   +----------------------------------------------------------------------------*/
 645 int is_powerpc440ep_pass1(void)
 646 {
 647         unsigned long pvr;
 648
 649         pvr = get_pvr();
 650
 651         if (pvr == PVR_POWERPC_440EP_PASS1)
 652                 return TRUE;
 653         else if (pvr == PVR_POWERPC_440EP_PASS2)
 654                 return FALSE;
 655         else {
 656                 printf("brdutil error 3\n");
 657                 for (;;)
 658                         ;
 659         }
 660
 661         return(FALSE);
 662 }
 663
 664 /*----------------------------------------------------------------------------+
 665   | is_nand_selected.
 666   +----------------------------------------------------------------------------*/
 667 int is_nand_selected(void)
 668 {
 669 #ifdef CONFIG_BAMBOO_NAND
 670         return TRUE;
 671 #else
 672         return FALSE;
 673 #endif
 674 }
 675
 676 /*----------------------------------------------------------------------------+
 677   | config_on_ebc_cs4_is_small_flash => from EPLD
 678   +----------------------------------------------------------------------------*/
 679 unsigned char config_on_ebc_cs4_is_small_flash(void)
 680 {
 681         /* Not implemented yet => returns constant value */
 682         return TRUE;
 683 }
 684
 685 /*----------------------------------------------------------------------------+
 686   | Ext_bus_cntlr_init.
 687   | Initialize the external bus controller
 688   +----------------------------------------------------------------------------*/
 689 void ext_bus_cntlr_init(void)
 690 {
 691         unsigned long sdr0_pstrp0, sdr0_sdstp1;
 692         unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
 693         int           computed_boot_device = BOOT_DEVICE_UNKNOWN;
 694         unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
 695         unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
 696         unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
 697         unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
 698         unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
 699
 700
 701         /*-------------------------------------------------------------------------+
 702           |
 703           |  PART 1 : Initialize EBC Bank 5
 704           |  ==============================
 705           | Bank5 is always associated to the NVRAM/EPLD.
 706           | It has to be initialized prior to other banks settings computation since
 707           | some board registers values may be needed
 708           |
 709           +-------------------------------------------------------------------------*/
 710         /* NVRAM - FPGA */
 711         mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
 712         mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
 713
 714         /*-------------------------------------------------------------------------+
 715           |
 716           |  PART 2 : Determine which boot device was selected
 717           |  =========================================
 718           |
 719           |  Read Pin Strap Register in PPC440EP
 720           |  In case of boot from IIC, read Serial Device Strap Register1
 721           |
 722           |  Result can either be :
 723           |   - Boot from EBC 8bits    => SMALL FLASH
 724           |   - Boot from EBC 16bits   => Large Flash or SRAM
 725           |   - Boot from NAND Flash
 726           |   - Boot from PCI
 727           |
 728           +-------------------------------------------------------------------------*/
 729         /* Read Pin Strap Register in PPC440EP */
 730         mfsdr(sdr_pstrp0, sdr0_pstrp0);
 731         bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
 732
 733         /*-------------------------------------------------------------------------+
 734           |  PPC440EP Pass1
 735           +-------------------------------------------------------------------------*/
 736         if (is_powerpc440ep_pass1() == TRUE) {
 737                 switch(bootstrap_settings) {
 738                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 739                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 740                         /* Boot from Small Flash */
 741                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 742                         break;
 743                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 744                         /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
 745                         /* Boot from PCI */
 746                         computed_boot_device = BOOT_FROM_PCI;
 747                         break;
 748
 749                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 750                         /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
 751                         /* Boot from Nand Flash */
 752                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 753                         break;
 754
 755                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 756                         /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
 757                         /* Boot from Small Flash */
 758                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 759                         break;
 760
 761                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 762                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 763                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 764                         /* Read Serial Device Strap Register1 in PPC440EP */
 765                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 766                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 767                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 768
 769                         switch(boot_selection) {
 770                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 771                                 switch(ebc_boot_size) {
 772                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 773                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 774                                         break;
 775                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 776                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 777                                         break;
 778                                 }
 779                                 break;
 780
 781                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 782                                 computed_boot_device = BOOT_FROM_PCI;
 783                                 break;
 784
 785                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 786                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 787                                 break;
 788                         }
 789                         break;
 790                 }
 791         }
 792
 793         /*-------------------------------------------------------------------------+
 794           |  PPC440EP Pass2
 795           +-------------------------------------------------------------------------*/
 796         else {
 797                 switch(bootstrap_settings) {
 798                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 799                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 800                         /* Boot from Small Flash */
 801                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 802                         break;
 803                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 804                         /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
 805                         /* Boot from PCI */
 806                         computed_boot_device = BOOT_FROM_PCI;
 807                         break;
 808
 809                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 810                         /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
 811                         /* Boot from Nand Flash */
 812                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 813                         break;
 814
 815                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 816                         /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
 817                         /* Boot from Large Flash or SRAM */
 818                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 819                         break;
 820
 821                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
 822                         /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
 823                         /* Boot from Large Flash or SRAM */
 824                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 825                         break;
 826
 827                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
 828                         /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
 829                         /* Boot from PCI */
 830                         computed_boot_device = BOOT_FROM_PCI;
 831                         break;
 832
 833                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 834                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 835                         /* Default Strap Settings 5-7 */
 836                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 837                         /* Read Serial Device Strap Register1 in PPC440EP */
 838                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 839                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 840                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 841
 842                         switch(boot_selection) {
 843                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 844                                 switch(ebc_boot_size) {
 845                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 846                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 847                                         break;
 848                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 849                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 850                                         break;
 851                                 }
 852                                 break;
 853
 854                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 855                                 computed_boot_device = BOOT_FROM_PCI;
 856                                 break;
 857
 858                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 859                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 860                                 break;
 861                         }
 862                         break;
 863                 }
 864         }
 865
 866         /*-------------------------------------------------------------------------+
 867           |
 868           |  PART 3 : Compute EBC settings depending on selected boot device
 869           |  ======   ======================================================
 870           |
 871           | Resulting EBC init will be among following configurations :
 872           |
 873           |  - Boot from EBC 8bits => boot from SMALL FLASH selected
 874           |            EBC-CS0     = Small Flash
 875           |            EBC-CS1,2,3 = NAND Flash or
 876           |                         Exp.Slot depending on Soft Config
 877           |            EBC-CS4     = SRAM/Large Flash or
 878           |                         Large Flash/SRAM depending on jumpers
 879           |            EBC-CS5     = NVRAM / EPLD
 880           |
 881           |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
 882           |            EBC-CS0     = SRAM/Large Flash or
 883           |                          Large Flash/SRAM depending on jumpers
 884           |            EBC-CS1,2,3 = NAND Flash or
 885           |                          Exp.Slot depending on Software Configuration
 886           |            EBC-CS4     = Small Flash
 887           |            EBC-CS5     = NVRAM / EPLD
 888           |
 889           |  - Boot from NAND Flash
 890           |            EBC-CS0     = NAND Flash0
 891           |            EBC-CS1,2,3 = NAND Flash1
 892           |            EBC-CS4     = SRAM/Large Flash or
 893           |                          Large Flash/SRAM depending on jumpers
 894           |            EBC-CS5     = NVRAM / EPLD
 895           |
 896           |    - Boot from PCI
 897           |            EBC-CS0     = ...
 898           |            EBC-CS1,2,3 = NAND Flash or
 899           |                          Exp.Slot depending on Software Configuration
 900           |            EBC-CS4     = SRAM/Large Flash or
 901           |                          Large Flash/SRAM or
 902           |                          Small Flash depending on jumpers
 903           |            EBC-CS5     = NVRAM / EPLD
 904           |
 905           +-------------------------------------------------------------------------*/
 906
 907         switch(computed_boot_device) {
 908                 /*------------------------------------------------------------------------- */
 909         case BOOT_FROM_SMALL_FLASH:
 910                 /*------------------------------------------------------------------------- */
 911                 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
 912                 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
 913                 if ((is_nand_selected()) == TRUE) {
 914                         /* NAND Flash */
 915                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 916                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 917                         ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
 918                         ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
 919                         ebc0_cs3_bnap_value = 0;
 920                         ebc0_cs3_bncr_value = 0;
 921                 } else {
 922                         /* Expansion Slot */
 923                         ebc0_cs1_bnap_value = 0;
 924                         ebc0_cs1_bncr_value = 0;
 925                         ebc0_cs2_bnap_value = 0;
 926                         ebc0_cs2_bncr_value = 0;
 927                         ebc0_cs3_bnap_value = 0;
 928                         ebc0_cs3_bncr_value = 0;
 929                 }
 930                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 931                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 932
 933                 break;
 934
 935                 /*------------------------------------------------------------------------- */
 936         case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 937                 /*------------------------------------------------------------------------- */
 938                 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 939                 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
 940                 if ((is_nand_selected()) == TRUE) {
 941                         /* NAND Flash */
 942                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 943                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 944                         ebc0_cs2_bnap_value = 0;
 945                         ebc0_cs2_bncr_value = 0;
 946                         ebc0_cs3_bnap_value = 0;
 947                         ebc0_cs3_bncr_value = 0;
 948                 } else {
 949                         /* Expansion Slot */
 950                         ebc0_cs1_bnap_value = 0;
 951                         ebc0_cs1_bncr_value = 0;
 952                         ebc0_cs2_bnap_value = 0;
 953                         ebc0_cs2_bncr_value = 0;
 954                         ebc0_cs3_bnap_value = 0;
 955                         ebc0_cs3_bncr_value = 0;
 956                 }
 957                 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 958                 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 959
 960                 break;
 961
 962                 /*------------------------------------------------------------------------- */
 963         case BOOT_FROM_NAND_FLASH0:
 964                 /*------------------------------------------------------------------------- */
 965                 ebc0_cs0_bnap_value = 0;
 966                 ebc0_cs0_bncr_value = 0;
 967
 968                 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 969                 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 970                 ebc0_cs2_bnap_value = 0;
 971                 ebc0_cs2_bncr_value = 0;
 972                 ebc0_cs3_bnap_value = 0;
 973                 ebc0_cs3_bncr_value = 0;
 974
 975                 /* Large Flash or SRAM */
 976                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 977                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 978
 979                 break;
 980
 981                 /*------------------------------------------------------------------------- */
 982         case BOOT_FROM_PCI:
 983                 /*------------------------------------------------------------------------- */
 984                 ebc0_cs0_bnap_value = 0;
 985                 ebc0_cs0_bncr_value = 0;
 986
 987                 if ((is_nand_selected()) == TRUE) {
 988                         /* NAND Flash */
 989                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 990                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 991                         ebc0_cs2_bnap_value = 0;
 992                         ebc0_cs2_bncr_value = 0;
 993                         ebc0_cs3_bnap_value = 0;
 994                         ebc0_cs3_bncr_value = 0;
 995                 } else {
 996                         /* Expansion Slot */
 997                         ebc0_cs1_bnap_value = 0;
 998                         ebc0_cs1_bncr_value = 0;
 999                         ebc0_cs2_bnap_value = 0;
1000                         ebc0_cs2_bncr_value = 0;
1001                         ebc0_cs3_bnap_value = 0;
1002                         ebc0_cs3_bncr_value = 0;
1003                 }
1004
1005                 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
1006                         /* Small Flash */
1007                         ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
1008                         ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
1009                 } else {
1010                         /* Large Flash or SRAM */
1011                         ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
1012                         ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1013                 }
1014
1015                 break;
1016
1017                 /*------------------------------------------------------------------------- */
1018         case BOOT_DEVICE_UNKNOWN:
1019                 /*------------------------------------------------------------------------- */
1020                 /* Error */
1021                 break;
1022
1023         }
1024
1025
1026         /*-------------------------------------------------------------------------+
1027           | Initialize EBC CONFIG
1028           +-------------------------------------------------------------------------*/
1029         mtdcr(ebccfga, xbcfg);
1030         mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN        |
1031               EBC0_CFG_PTD_ENABLED        |
1032               EBC0_CFG_RTC_2048PERCLK     |
1033               EBC0_CFG_EMPL_LOW           |
1034               EBC0_CFG_EMPH_LOW           |
1035               EBC0_CFG_CSTC_DRIVEN        |
1036               EBC0_CFG_BPF_ONEDW          |
1037               EBC0_CFG_EMS_8BIT           |
1038               EBC0_CFG_PME_DISABLED       |
1039               EBC0_CFG_PMT_ENCODE(0)      );
1040
1041         /*-------------------------------------------------------------------------+
1042           | Initialize EBC Bank 0-4
1043           +-------------------------------------------------------------------------*/
1044         /* EBC Bank0 */
1045         mtebc(pb0ap, ebc0_cs0_bnap_value);
1046         mtebc(pb0cr, ebc0_cs0_bncr_value);
1047         /* EBC Bank1 */
1048         mtebc(pb1ap, ebc0_cs1_bnap_value);
1049         mtebc(pb1cr, ebc0_cs1_bncr_value);
1050         /* EBC Bank2 */
1051         mtebc(pb2ap, ebc0_cs2_bnap_value);
1052         mtebc(pb2cr, ebc0_cs2_bncr_value);
1053         /* EBC Bank3 */
1054         mtebc(pb3ap, ebc0_cs3_bnap_value);
1055         mtebc(pb3cr, ebc0_cs3_bncr_value);
1056         /* EBC Bank4 */
1057         mtebc(pb4ap, ebc0_cs4_bnap_value);
1058         mtebc(pb4cr, ebc0_cs4_bncr_value);
1059
1060         return;
1061 }
1062
1063
1064 /*----------------------------------------------------------------------------+
1065   | get_uart_configuration.
1066   +----------------------------------------------------------------------------*/
1067 uart_config_nb_t get_uart_configuration(void)
1068 {
1069         return (L4);
1070 }
1071
1072 /*----------------------------------------------------------------------------+
1073   | set_phy_configuration_through_fpga => to EPLD
1074   +----------------------------------------------------------------------------*/
1075 void set_phy_configuration_through_fpga(zmii_config_t config)
1076 {
1077
1078         unsigned long fpga_selection_reg;
1079
1080         fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1081
1082         switch(config)
1083         {
1084         case ZMII_CONFIGURATION_IS_MII:
1085                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1086                 break;
1087         case ZMII_CONFIGURATION_IS_RMII:
1088                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1089                 break;
1090         case ZMII_CONFIGURATION_IS_SMII:
1091                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1092                 break;
1093         case ZMII_CONFIGURATION_UNKNOWN:
1094         default:
1095                 break;
1096         }
1097         out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1098
1099 }
1100
1101 /*----------------------------------------------------------------------------+
1102   | scp_selection_in_fpga.
1103   +----------------------------------------------------------------------------*/
1104 void scp_selection_in_fpga(void)
1105 {
1106         unsigned long fpga_selection_2_reg;
1107
1108         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1109         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1110         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1111 }
1112
1113 /*----------------------------------------------------------------------------+
1114   | iic1_selection_in_fpga.
1115   +----------------------------------------------------------------------------*/
1116 void iic1_selection_in_fpga(void)
1117 {
1118         unsigned long fpga_selection_2_reg;
1119
1120         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1121         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1122         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1123 }
1124
1125 /*----------------------------------------------------------------------------+
1126   | dma_a_b_selection_in_fpga.
1127   +----------------------------------------------------------------------------*/
1128 void dma_a_b_selection_in_fpga(void)
1129 {
1130         unsigned long fpga_selection_2_reg;
1131
1132         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1133         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1134 }
1135
1136 /*----------------------------------------------------------------------------+
1137   | dma_a_b_unselect_in_fpga.
1138   +----------------------------------------------------------------------------*/
1139 void dma_a_b_unselect_in_fpga(void)
1140 {
1141         unsigned long fpga_selection_2_reg;
1142
1143         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1144         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1145 }
1146
1147 /*----------------------------------------------------------------------------+
1148   | dma_c_d_selection_in_fpga.
1149   +----------------------------------------------------------------------------*/
1150 void dma_c_d_selection_in_fpga(void)
1151 {
1152         unsigned long fpga_selection_2_reg;
1153
1154         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1155         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1156 }
1157
1158 /*----------------------------------------------------------------------------+
1159   | dma_c_d_unselect_in_fpga.
1160   +----------------------------------------------------------------------------*/
1161 void dma_c_d_unselect_in_fpga(void)
1162 {
1163         unsigned long fpga_selection_2_reg;
1164
1165         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1166         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1167 }
1168
1169 /*----------------------------------------------------------------------------+
1170   | usb2_device_selection_in_fpga.
1171   +----------------------------------------------------------------------------*/
1172 void usb2_device_selection_in_fpga(void)
1173 {
1174         unsigned long fpga_selection_1_reg;
1175
1176         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1177         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1178 }
1179
1180 /*----------------------------------------------------------------------------+
1181   | usb2_device_reset_through_fpga.
1182   +----------------------------------------------------------------------------*/
1183 void usb2_device_reset_through_fpga(void)
1184 {
1185         /* Perform soft Reset pulse */
1186         unsigned long fpga_reset_reg;
1187         int i;
1188
1189         fpga_reset_reg = in8(FPGA_RESET_REG);
1190         out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1191         for (i=0; i<500; i++)
1192                 udelay(1000);
1193         out8(FPGA_RESET_REG,fpga_reset_reg);
1194 }
1195
1196 /*----------------------------------------------------------------------------+
1197   | usb2_host_selection_in_fpga.
1198   +----------------------------------------------------------------------------*/
1199 void usb2_host_selection_in_fpga(void)
1200 {
1201         unsigned long fpga_selection_1_reg;
1202
1203         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1204         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1205 }
1206
1207 /*----------------------------------------------------------------------------+
1208   | ndfc_selection_in_fpga.
1209   +----------------------------------------------------------------------------*/
1210 void ndfc_selection_in_fpga(void)
1211 {
1212         unsigned long fpga_selection_1_reg;
1213
1214         fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1215         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1216         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1217         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1218 }
1219
1220 /*----------------------------------------------------------------------------+
1221   | uart_selection_in_fpga.
1222   +----------------------------------------------------------------------------*/
1223 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1224 {
1225         /* FPGA register */
1226         unsigned char   fpga_selection_3_reg;
1227
1228         /* Read FPGA Reagister */
1229         fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1230
1231         switch (uart_config)
1232         {
1233         case L1:
1234                 /* ----------------------------------------------------------------------- */
1235                 /* L1 configuration:    UART0 = 8 pins */
1236                 /* ----------------------------------------------------------------------- */
1237                 /* Configure FPGA */
1238                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1239                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1240                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1241
1242                 break;
1243
1244         case L2:
1245                 /* ----------------------------------------------------------------------- */
1246                 /* L2 configuration:    UART0 = 4 pins */
1247                 /*                      UART1 = 4 pins */
1248                 /* ----------------------------------------------------------------------- */
1249                 /* Configure FPGA */
1250                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1251                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1252                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1253
1254                 break;
1255
1256         case L3:
1257                 /* ----------------------------------------------------------------------- */
1258                 /* L3 configuration:    UART0 = 4 pins */
1259                 /*                      UART1 = 2 pins */
1260                 /*                      UART2 = 2 pins */
1261                 /* ----------------------------------------------------------------------- */
1262                 /* Configure FPGA */
1263                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1264                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1265                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1266                 break;
1267
1268         case L4:
1269                 /* Configure FPGA */
1270                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1271                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1272                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1273
1274                 break;
1275
1276         default:
1277                 /* Unsupported UART configuration number */
1278                 for (;;)
1279                         ;
1280                 break;
1281
1282         }
1283 }
1284
1285
1286 /*----------------------------------------------------------------------------+
1287   | init_default_gpio
1288   +----------------------------------------------------------------------------*/
1289 void init_default_gpio(void)
1290 {
1291         int i;
1292
1293         /* Init GPIO0 */
1294         for(i=0; i<GPIO_MAX; i++)
1295         {
1296                 gpio_tab[GPIO0][i].add    = GPIO0_BASE;
1297                 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1298                 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1299         }
1300
1301         /* Init GPIO1 */
1302         for(i=0; i<GPIO_MAX; i++)
1303         {
1304                 gpio_tab[GPIO1][i].add    = GPIO1_BASE;
1305                 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1306                 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1307         }
1308
1309         /* EBC_CS_N(5) - GPIO0_10 */
1310         gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
1311         gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
1312
1313         /* EBC_CS_N(4) - GPIO0_9 */
1314         gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
1315         gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
1316 }
1317
1318 /*----------------------------------------------------------------------------+
1319   | update_uart_ios
1320   +------------------------------------------------------------------------------
1321   |
1322   | Set UART Configuration in PowerPC440EP
1323   |
1324   | +---------------------------------------------------------------------+
1325   | | Configuartion   |   Connector   | Nb of pins | Pins   | Associated  |
1326   | |    Number       |   Port Name   |  available | naming |   CORE      |
1327   | +-----------------+---------------+------------+--------+-------------+
1328   | |     L1          |   Port_A      |     8      | UART   | UART core 0 |
1329   | +-----------------+---------------+------------+--------+-------------+
1330   | |     L2          |   Port_A      |     4      | UART1  | UART core 0 |
1331   | |    (L2D)        |   Port_B      |     4      | UART2  | UART core 1 |
1332   | +-----------------+---------------+------------+--------+-------------+
1333   | |     L3          |   Port_A      |     4      | UART1  | UART core 0 |
1334   | |    (L3D)        |   Port_B      |     2      | UART2  | UART core 1 |
1335   | |                 |   Port_C      |     2      | UART3  | UART core 2 |
1336   | +-----------------+---------------+------------+--------+-------------+
1337   | |                 |   Port_A      |     2      | UART1  | UART core 0 |
1338   | |     L4          |   Port_B      |     2      | UART2  | UART core 1 |
1339   | |    (L4D)        |   Port_C      |     2      | UART3  | UART core 2 |
1340   | |                 |   Port_D      |     2      | UART4  | UART core 3 |
1341   | +-----------------+---------------+------------+--------+-------------+
1342   |
1343   |  Involved GPIOs
1344   |
1345   | +------------------------------------------------------------------------------+
1346   | |  GPIO   |   Aternate 1     | I/O |  Alternate 2    | I/O | Alternate 3 | I/O |
1347   | +---------+------------------+-----+-----------------+-----+-------------+-----+
1348   | | GPIO1_2 | UART0_DCD_N      |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |  O  |
1349   | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |  I  |
1350   | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA              |  NA | UART3_SIN   |  I  |
1351   | | GPIO1_5 | UART0_RTS_N      |  O  | NA              |  NA | UART3_SOUT  |  O  |
1352   | | GPIO1_6 | UART0_DTR_N      |  O  | UART1_SOUT      |  O  | NA          |  NA |
1353   | | GPIO1_7 | UART0_RI_N       |  I  | UART1_SIN       |  I  | NA          |  NA |
1354   | +------------------------------------------------------------------------------+
1355   |
1356   |
1357   +----------------------------------------------------------------------------*/
1358
1359 void update_uart_ios(uart_config_nb_t uart_config)
1360 {
1361         switch (uart_config)
1362         {
1363         case L1:
1364                 /* ----------------------------------------------------------------------- */
1365                 /* L1 configuration:    UART0 = 8 pins */
1366                 /* ----------------------------------------------------------------------- */
1367                 /* Update GPIO Configuration Table */
1368                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1369                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1370
1371                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1372                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1373
1374                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1375                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1376
1377                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1378                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1379
1380                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1381                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1382
1383                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1384                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1385
1386                 break;
1387
1388         case L2:
1389                 /* ----------------------------------------------------------------------- */
1390                 /* L2 configuration:    UART0 = 4 pins */
1391                 /*                      UART1 = 4 pins */
1392                 /* ----------------------------------------------------------------------- */
1393                 /* Update GPIO Configuration Table */
1394                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1395                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1396
1397                 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1398                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1399
1400                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1401                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1402
1403                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1404                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1405
1406                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1407                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1408
1409                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1410                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1411
1412                 break;
1413
1414         case L3:
1415                 /* ----------------------------------------------------------------------- */
1416                 /* L3 configuration:    UART0 = 4 pins */
1417                 /*                      UART1 = 2 pins */
1418                 /*                      UART2 = 2 pins */
1419                 /* ----------------------------------------------------------------------- */
1420                 /* Update GPIO Configuration Table */
1421                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1422                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1423
1424                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1425                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1426
1427                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1428                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1429
1430                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1431                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1432
1433                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1434                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1435
1436                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1437                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1438
1439                 break;
1440
1441         case L4:
1442                 /* ----------------------------------------------------------------------- */
1443                 /* L4 configuration:    UART0 = 2 pins */
1444                 /*                      UART1 = 2 pins */
1445                 /*                      UART2 = 2 pins */
1446                 /*                      UART3 = 2 pins */
1447                 /* ----------------------------------------------------------------------- */
1448                 /* Update GPIO Configuration Table */
1449                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1450                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1451
1452                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1453                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1454
1455                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1456                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1457
1458                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1459                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1460
1461                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1462                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1463
1464                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1465                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1466
1467                 break;
1468
1469         default:
1470                 /* Unsupported UART configuration number */
1471                 printf("ERROR - Unsupported UART configuration number.\n\n");
1472                 for (;;)
1473                         ;
1474                 break;
1475
1476         }
1477
1478         /* Set input Selection Register on Alt_Receive for UART Input Core */
1479         out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1480         out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1481         out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1482 }
1483
1484 /*----------------------------------------------------------------------------+
1485   | update_ndfc_ios(void).
1486   +----------------------------------------------------------------------------*/
1487 void update_ndfc_ios(void)
1488 {
1489         /* Update GPIO Configuration Table */
1490         gpio_tab[GPIO0][6].in_out = GPIO_OUT;       /* EBC_CS_N(1) */
1491         gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1492
1493 #if 0
1494         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(2) */
1495         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1496
1497         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(3) */
1498         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1499 #endif
1500 }
1501
1502 /*----------------------------------------------------------------------------+
1503   | update_zii_ios(void).
1504   +----------------------------------------------------------------------------*/
1505 void update_zii_ios(void)
1506 {
1507         /* Update GPIO Configuration Table */
1508         gpio_tab[GPIO0][12].in_out = GPIO_IN;       /* ZII_p0Rxd(0) */
1509         gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1510
1511         gpio_tab[GPIO0][13].in_out = GPIO_IN;       /* ZII_p0Rxd(1) */
1512         gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1513
1514         gpio_tab[GPIO0][14].in_out = GPIO_IN;       /* ZII_p0Rxd(2) */
1515         gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1516
1517         gpio_tab[GPIO0][15].in_out = GPIO_IN;       /* ZII_p0Rxd(3) */
1518         gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1519
1520         gpio_tab[GPIO0][16].in_out = GPIO_OUT;      /* ZII_p0Txd(0) */
1521         gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1522
1523         gpio_tab[GPIO0][17].in_out = GPIO_OUT;      /* ZII_p0Txd(1) */
1524         gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1525
1526         gpio_tab[GPIO0][18].in_out = GPIO_OUT;      /* ZII_p0Txd(2) */
1527         gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1528
1529         gpio_tab[GPIO0][19].in_out = GPIO_OUT;      /* ZII_p0Txd(3) */
1530         gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1531
1532         gpio_tab[GPIO0][20].in_out = GPIO_IN;       /* ZII_p0Rx_er */
1533         gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1534
1535         gpio_tab[GPIO0][21].in_out = GPIO_IN;       /* ZII_p0Rx_dv */
1536         gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1537
1538         gpio_tab[GPIO0][22].in_out = GPIO_IN;       /* ZII_p0Crs */
1539         gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1540
1541         gpio_tab[GPIO0][23].in_out = GPIO_OUT;      /* ZII_p0Tx_er */
1542         gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1543
1544         gpio_tab[GPIO0][24].in_out = GPIO_OUT;      /* ZII_p0Tx_en */
1545         gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1546
1547         gpio_tab[GPIO0][25].in_out = GPIO_IN;       /* ZII_p0Col */
1548         gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1549
1550 }
1551
1552 /*----------------------------------------------------------------------------+
1553   | update_uic_0_3_irq_ios().
1554   +----------------------------------------------------------------------------*/
1555 void update_uic_0_3_irq_ios(void)
1556 {
1557         gpio_tab[GPIO1][8].in_out = GPIO_IN;        /* UIC_IRQ(0) */
1558         gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1559
1560         gpio_tab[GPIO1][9].in_out = GPIO_IN;        /* UIC_IRQ(1) */
1561         gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1562
1563         gpio_tab[GPIO1][10].in_out = GPIO_IN;       /* UIC_IRQ(2) */
1564         gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1565
1566         gpio_tab[GPIO1][11].in_out = GPIO_IN;       /* UIC_IRQ(3) */
1567         gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1568 }
1569
1570 /*----------------------------------------------------------------------------+
1571   | update_uic_4_9_irq_ios().
1572   +----------------------------------------------------------------------------*/
1573 void update_uic_4_9_irq_ios(void)
1574 {
1575         gpio_tab[GPIO1][12].in_out = GPIO_IN;       /* UIC_IRQ(4) */
1576         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1577
1578         gpio_tab[GPIO1][13].in_out = GPIO_IN;       /* UIC_IRQ(6) */
1579         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1580
1581         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* UIC_IRQ(7) */
1582         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1583
1584         gpio_tab[GPIO1][15].in_out = GPIO_IN;       /* UIC_IRQ(8) */
1585         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1586
1587         gpio_tab[GPIO1][16].in_out = GPIO_IN;       /* UIC_IRQ(9) */
1588         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1589 }
1590
1591 /*----------------------------------------------------------------------------+
1592   | update_dma_a_b_ios().
1593   +----------------------------------------------------------------------------*/
1594 void update_dma_a_b_ios(void)
1595 {
1596         gpio_tab[GPIO1][12].in_out = GPIO_OUT;      /* DMA_ACK(1) */
1597         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1598
1599         gpio_tab[GPIO1][13].in_out = GPIO_BI;       /* DMA_EOT/TC(1) */
1600         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1601
1602         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* DMA_REQ(0) */
1603         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1604
1605         gpio_tab[GPIO1][15].in_out = GPIO_OUT;      /* DMA_ACK(0) */
1606         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1607
1608         gpio_tab[GPIO1][16].in_out = GPIO_BI;       /* DMA_EOT/TC(0) */
1609         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1610 }
1611
1612 /*----------------------------------------------------------------------------+
1613   | update_dma_c_d_ios().
1614   +----------------------------------------------------------------------------*/
1615 void update_dma_c_d_ios(void)
1616 {
1617         gpio_tab[GPIO0][0].in_out = GPIO_IN;        /* DMA_REQ(2) */
1618         gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1619
1620         gpio_tab[GPIO0][1].in_out = GPIO_OUT;       /* DMA_ACK(2) */
1621         gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1622
1623         gpio_tab[GPIO0][2].in_out = GPIO_BI;        /* DMA_EOT/TC(2) */
1624         gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1625
1626         gpio_tab[GPIO0][3].in_out = GPIO_IN;        /* DMA_REQ(3) */
1627         gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1628
1629         gpio_tab[GPIO0][4].in_out = GPIO_OUT;       /* DMA_ACK(3) */
1630         gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1631
1632         gpio_tab[GPIO0][5].in_out = GPIO_BI;        /* DMA_EOT/TC(3) */
1633         gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1634
1635 }
1636
1637 /*----------------------------------------------------------------------------+
1638   | update_ebc_master_ios().
1639   +----------------------------------------------------------------------------*/
1640 void update_ebc_master_ios(void)
1641 {
1642         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* EXT_EBC_REQ */
1643         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1644
1645         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1646         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1647
1648         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* EBC_EXT_ACK */
1649         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1650
1651         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* EBC_EXR_BUSREQ */
1652         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1653 }
1654
1655 /*----------------------------------------------------------------------------+
1656   | update_usb2_device_ios().
1657   +----------------------------------------------------------------------------*/
1658 void update_usb2_device_ios(void)
1659 {
1660         gpio_tab[GPIO0][26].in_out = GPIO_IN;       /* USB2D_RXVALID */
1661         gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1662
1663         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* USB2D_RXERROR */
1664         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1665
1666         gpio_tab[GPIO0][28].in_out = GPIO_OUT;      /* USB2D_TXVALID */
1667         gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1668
1669         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* USB2D_PAD_SUSPNDM */
1670         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1671
1672         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* USB2D_XCVRSELECT */
1673         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1674
1675         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* USB2D_TERMSELECT */
1676         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1677
1678         gpio_tab[GPIO1][0].in_out = GPIO_OUT;       /* USB2D_OPMODE0 */
1679         gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1680
1681         gpio_tab[GPIO1][1].in_out = GPIO_OUT;       /* USB2D_OPMODE1 */
1682         gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1683
1684 }
1685
1686 /*----------------------------------------------------------------------------+
1687   | update_pci_patch_ios().
1688   +----------------------------------------------------------------------------*/
1689 void update_pci_patch_ios(void)
1690 {
1691         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1692         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1693 }
1694
1695 /*----------------------------------------------------------------------------+
1696   |   set_chip_gpio_configuration(unsigned char gpio_core)
1697   |   Put the core impacted by clock modification and sharing in reset.
1698   |   Config the select registers to resolve the sharing depending of the config.
1699   |   Configure the GPIO registers.
1700   |
1701   +----------------------------------------------------------------------------*/
1702 void set_chip_gpio_configuration(unsigned char gpio_core)
1703 {
1704         unsigned char i=0, j=0, reg_offset = 0;
1705         unsigned long gpio_reg, gpio_core_add;
1706
1707         /* GPIO config of the GPIOs 0 to 31 */
1708         for (i=0; i<GPIO_MAX; i++, j++)
1709         {
1710                 if (i == GPIO_MAX/2)
1711                 {
1712                         reg_offset = 4;
1713                         j = i-16;
1714                 }
1715
1716                 gpio_core_add = gpio_tab[gpio_core][i].add;
1717
1718                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1719                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1720                 {
1721                         switch (gpio_tab[gpio_core][i].alt_nb)
1722                         {
1723                         case GPIO_SEL:
1724                                 break;
1725
1726                         case GPIO_ALT1:
1727                                 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1728                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1729                                 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1730                                 break;
1731
1732                         case GPIO_ALT2:
1733                                 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1734                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1735                                 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1736                                 break;
1737
1738                         case GPIO_ALT3:
1739                                 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1740                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1741                                 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1742                                 break;
1743                         }
1744                 }
1745                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1746                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1747                 {
1748
1749                         switch (gpio_tab[gpio_core][i].alt_nb)
1750                         {
1751                         case GPIO_SEL:
1752                                 break;
1753                         case GPIO_ALT1:
1754                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1755                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1756                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1757                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1758                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1759                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1760                                 break;
1761                         case GPIO_ALT2:
1762                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1763                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1764                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1765                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1766                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1767                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1768                                 break;
1769                         case GPIO_ALT3:
1770                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1771                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1772                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1773                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1774                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1775                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1776                                 break;
1777                         }
1778                 }
1779         }
1780 }
1781
1782 /*----------------------------------------------------------------------------+
1783   | force_bup_core_selection.
1784   +----------------------------------------------------------------------------*/
1785 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1786 {
1787         /* Pointer invalid */
1788         if (core_select_P == NULL)
1789         {
1790                 printf("Configuration invalid pointer 1\n");
1791                 for (;;)
1792                         ;
1793         }
1794
1795         /* L4 Selection */
1796         *(core_select_P+UART_CORE0)            = CORE_SELECTED;
1797         *(core_select_P+UART_CORE1)            = CORE_SELECTED;
1798         *(core_select_P+UART_CORE2)            = CORE_SELECTED;
1799         *(core_select_P+UART_CORE3)            = CORE_SELECTED;
1800
1801         /* RMII Selection */
1802         *(core_select_P+RMII_SEL)               = CORE_SELECTED;
1803
1804         /* External Interrupt 0-9 selection */
1805         *(core_select_P+UIC_0_3)                = CORE_SELECTED;
1806         *(core_select_P+UIC_4_9)                = CORE_SELECTED;
1807
1808         *(core_select_P+SCP_CORE)               = CORE_SELECTED;
1809         *(core_select_P+DMA_CHANNEL_CD)         = CORE_SELECTED;
1810         *(core_select_P+PACKET_REJ_FUNC_AVAIL)  = CORE_SELECTED;
1811         *(core_select_P+USB1_DEVICE)            = CORE_SELECTED;
1812
1813         if (is_nand_selected()) {
1814                 *(core_select_P+NAND_FLASH)     = CORE_SELECTED;
1815         }
1816
1817         *config_val_P = CONFIG_IS_VALID;
1818
1819 }
1820
1821 /*----------------------------------------------------------------------------+
1822   | configure_ppc440ep_pins.
1823   +----------------------------------------------------------------------------*/
1824 void configure_ppc440ep_pins(void)
1825 {
1826         uart_config_nb_t uart_configuration;
1827         config_validity_t config_val = CONFIG_IS_INVALID;
1828
1829         /* Create Core Selection Table */
1830         core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1831                 {
1832                         CORE_NOT_SELECTED,      /* IIC_CORE, */
1833                         CORE_NOT_SELECTED,      /* SPC_CORE, */
1834                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_AB, */
1835                         CORE_NOT_SELECTED,      /* UIC_4_9, */
1836                         CORE_NOT_SELECTED,      /* USB2_HOST, */
1837                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_CD, */
1838                         CORE_NOT_SELECTED,      /* USB2_DEVICE, */
1839                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_AVAIL, */
1840                         CORE_NOT_SELECTED,      /* USB1_DEVICE, */
1841                         CORE_NOT_SELECTED,      /* EBC_MASTER, */
1842                         CORE_NOT_SELECTED,      /* NAND_FLASH, */
1843                         CORE_NOT_SELECTED,      /* UART_CORE0, */
1844                         CORE_NOT_SELECTED,      /* UART_CORE1, */
1845                         CORE_NOT_SELECTED,      /* UART_CORE2, */
1846                         CORE_NOT_SELECTED,      /* UART_CORE3, */
1847                         CORE_NOT_SELECTED,      /* MII_SEL, */
1848                         CORE_NOT_SELECTED,      /* RMII_SEL, */
1849                         CORE_NOT_SELECTED,      /* SMII_SEL, */
1850                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_EN */
1851                         CORE_NOT_SELECTED,      /* UIC_0_3 */
1852                         CORE_NOT_SELECTED,      /* USB1_HOST */
1853                         CORE_NOT_SELECTED       /* PCI_PATCH */
1854                 };
1855
1856
1857         /* Table Default Initialisation + FPGA Access */
1858         init_default_gpio();
1859         set_chip_gpio_configuration(GPIO0);
1860         set_chip_gpio_configuration(GPIO1);
1861
1862         /* Update Table */
1863         force_bup_core_selection(ppc440ep_core_selection, &config_val);
1864 #if 0 /* test-only */
1865         /* If we are running PIBS 1, force known configuration */
1866         update_core_selection_table(ppc440ep_core_selection, &config_val);
1867 #endif
1868
1869         /*----------------------------------------------------------------------------+
1870           | SDR + ios table update + fpga initialization
1871           +----------------------------------------------------------------------------*/
1872         unsigned long sdr0_pfc1     = 0;
1873         unsigned long sdr0_usb0     = 0;
1874         unsigned long sdr0_mfr      = 0;
1875
1876         /* PCI Always selected */
1877
1878         /* I2C Selection */
1879         if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1880         {
1881                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1882                 iic1_selection_in_fpga();
1883         }
1884
1885         /* SCP Selection */
1886         if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1887         {
1888                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1889                 scp_selection_in_fpga();
1890         }
1891
1892         /* UIC 0:3 Selection */
1893         if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1894         {
1895                 update_uic_0_3_irq_ios();
1896                 dma_a_b_unselect_in_fpga();
1897         }
1898
1899         /* UIC 4:9 Selection */
1900         if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1901         {
1902                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1903                 update_uic_4_9_irq_ios();
1904         }
1905
1906         /* DMA AB Selection */
1907         if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1908         {
1909                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1910                 update_dma_a_b_ios();
1911                 dma_a_b_selection_in_fpga();
1912         }
1913
1914         /* DMA CD Selection */
1915         if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1916         {
1917                 update_dma_c_d_ios();
1918                 dma_c_d_selection_in_fpga();
1919         }
1920
1921         /* EBC Master Selection */
1922         if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1923         {
1924                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1925                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1926                 update_ebc_master_ios();
1927         }
1928
1929         /* PCI Patch Enable */
1930         if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1931         {
1932                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1933                 update_pci_patch_ios();
1934         }
1935
1936         /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1937         if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1938         {
1939                 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1940                 printf("Invalid configuration => USB2 Host selected\n");
1941                 for (;;)
1942                         ;
1943                 /*usb2_host_selection_in_fpga(); */
1944         }
1945
1946         /* USB2.0 Device Selection */
1947         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1948         {
1949                 update_usb2_device_ios();
1950                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1951                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1952
1953                 mfsdr(sdr_usb0, sdr0_usb0);
1954                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1955                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1956                 mtsdr(sdr_usb0, sdr0_usb0);
1957
1958                 usb2_device_selection_in_fpga();
1959         }
1960
1961         /* USB1.1 Device Selection */
1962         if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1963         {
1964                 mfsdr(sdr_usb0, sdr0_usb0);
1965                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1966                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1967                 mtsdr(sdr_usb0, sdr0_usb0);
1968         }
1969
1970         /* USB1.1 Host Selection */
1971         if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1972         {
1973                 mfsdr(sdr_usb0, sdr0_usb0);
1974                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1975                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1976                 mtsdr(sdr_usb0, sdr0_usb0);
1977         }
1978
1979         /* NAND Flash Selection */
1980         if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1981         {
1982                 update_ndfc_ios();
1983
1984                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
1985                       SDR0_CUST0_NDFC_ENABLE    |
1986                       SDR0_CUST0_NDFC_BW_8_BIT  |
1987                       SDR0_CUST0_NDFC_ARE_MASK  |
1988                       SDR0_CUST0_CHIPSELGAT_EN1 |
1989                       SDR0_CUST0_CHIPSELGAT_EN2);
1990
1991                 ndfc_selection_in_fpga();
1992         }
1993         else
1994         {
1995                 /* Set Mux on EMAC */
1996                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1997         }
1998
1999         /* MII Selection */
2000         if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
2001         {
2002                 update_zii_ios();
2003                 mfsdr(sdr_mfr, sdr0_mfr);
2004                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
2005                 mtsdr(sdr_mfr, sdr0_mfr);
2006
2007                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
2008         }
2009
2010         /* RMII Selection */
2011         if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
2012         {
2013                 update_zii_ios();
2014                 mfsdr(sdr_mfr, sdr0_mfr);
2015                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
2016                 mtsdr(sdr_mfr, sdr0_mfr);
2017
2018                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
2019         }
2020
2021         /* SMII Selection */
2022         if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
2023         {
2024                 update_zii_ios();
2025                 mfsdr(sdr_mfr, sdr0_mfr);
2026                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2027                 mtsdr(sdr_mfr, sdr0_mfr);
2028
2029                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2030         }
2031
2032         /* UART Selection */
2033         uart_configuration = get_uart_configuration();
2034         switch (uart_configuration)
2035         {
2036         case L1:         /* L1 Selection */
2037                 /* UART0 8 pins Only */
2038                 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
2039                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;   /* Chip Pb */
2040                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2041                 break;
2042         case L2:         /* L2 Selection */
2043                 /* UART0 and UART1 4 pins */
2044                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2045                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2046                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2047                 break;
2048         case L3:         /* L3 Selection */
2049                 /* UART0 4 pins, UART1 and UART2 2 pins */
2050                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2051                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2052                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2053                 break;
2054         case L4:         /* L4 Selection */
2055                 /* UART0, UART1, UART2 and UART3 2 pins */
2056                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2057                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2058                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2059                 break;
2060         }
2061         update_uart_ios(uart_configuration);
2062
2063         /* UART Selection in all cases */
2064         uart_selection_in_fpga(uart_configuration);
2065
2066         /* Packet Reject Function Available */
2067         if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2068         {
2069                 /* Set UPR Bit in SDR0_PFC1 Register */
2070                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2071         }
2072
2073         /* Packet Reject Function Enable */
2074         if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2075         {
2076                 mfsdr(sdr_mfr, sdr0_mfr);
2077                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2078                 mtsdr(sdr_mfr, sdr0_mfr);
2079         }
2080
2081         /* Perform effective access to hardware */
2082         mtsdr(sdr_pfc1, sdr0_pfc1);
2083         set_chip_gpio_configuration(GPIO0);
2084         set_chip_gpio_configuration(GPIO1);
2085
2086         /* USB2.0 Device Reset must be done after GPIO setting */
2087         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2088                 usb2_device_reset_through_fpga();
2089
2090 }