board/amcc/bamboo/bamboo.c

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <spd_sdram.h>
  27 #include <ppc440.h>
  28 #include "bamboo.h"
  29
  30 void ext_bus_cntlr_init(void);
  31 void configure_ppc440ep_pins(void);
  32 int is_nand_selected(void);
  33
  34 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  35 #if 0
  36 {          /* GPIO   Alternate1       Alternate2        Alternate3 */
  37     {
  38         /* GPIO Core 0 */
  39         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0  -> EBC_ADDR(7)      DMA_REQ(2) */
  40         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1  -> EBC_ADDR(6)      DMA_ACK(2) */
  41         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2  -> EBC_ADDR(5)      DMA_EOT/TC(2) */
  42         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3  -> EBC_ADDR(4)      DMA_REQ(3) */
  43         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4  -> EBC_ADDR(3)      DMA_ACK(3) */
  44         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  45         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6  -> EBC_CS_N(1) */
  46         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7  -> EBC_CS_N(2) */
  47         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8  -> EBC_CS_N(3) */
  48         { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9  -> EBC_CS_N(4) */
  49         { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  50         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  51         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  52         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  53         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  54         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  55         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  56         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  57         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  58         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  59         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  60         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  61         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  62         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  63         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  64         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  65         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->                  USB2D_RXVALID */
  66         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ      USB2D_RXERROR */
  67         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->                  USB2D_TXVALID */
  68         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA     USB2D_PAD_SUSPNDM */
  69         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK      USB2D_XCVRSELECT */
  70         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
  71     },
  72     {
  73         /* GPIO Core 1 */
  74         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0  -> USB2D_OPMODE0 */
  75         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1  -> USB2D_OPMODE1 */
  76         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2  -> UART0_DCD_N      UART1_DSR_CTS_N   UART2_SOUT */
  77         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3  -> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
  78         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4  -> UART0_8PIN_CTS_N                   UART3_SIN */
  79         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5  -> UART0_RTS_N */
  80         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6  -> UART0_DTR_N      UART1_SOUT */
  81         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7  -> UART0_RI_N       UART1_SIN */
  82         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8  -> UIC_IRQ(0) */
  83         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9  -> UIC_IRQ(1) */
  84         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  85         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  86         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)       DMA_ACK(1) */
  87         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)       DMA_EOT/TC(1) */
  88         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)       DMA_REQ(0) */
  89         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)       DMA_ACK(0) */
  90         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)       DMA_EOT/TC(0) */
  91         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  92         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
  93         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
  94         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
  95         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
  96         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
  97         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \     Can be unselected thru TraceSelect Bit */
  98         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /        in PowerPC440EP Chip */
  99         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
 100         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
 101         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
 102         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
 103         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
 104         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
 105         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
 106     }
 107 };
 108 #endif
 109
 110 /*----------------------------------------------------------------------------+
 111   | EBC Devices Characteristics
 112   |   Peripheral Bank Access Parameters       -   EBC0_BnAP
 113   |   Peripheral Bank Configuration Register  -   EBC0_BnCR
 114   +----------------------------------------------------------------------------*/
 115 /* Small Flash */
 116 #define EBC0_BNAP_SMALL_FLASH                           \
 117         EBC0_BNAP_BME_DISABLED                  |       \
 118         EBC0_BNAP_TWT_ENCODE(6)                 |       \
 119         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 120         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 121         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 122         EBC0_BNAP_WBF_ENCODE(3)                 |       \
 123         EBC0_BNAP_TH_ENCODE(1)                  |       \
 124         EBC0_BNAP_RE_ENABLED                    |       \
 125         EBC0_BNAP_SOR_DELAYED                   |       \
 126         EBC0_BNAP_BEM_WRITEONLY                 |       \
 127         EBC0_BNAP_PEN_DISABLED
 128
 129 #define EBC0_BNCR_SMALL_FLASH_CS0                       \
 130         EBC0_BNCR_BAS_ENCODE(0xFFF00000)        |       \
 131         EBC0_BNCR_BS_1MB                        |       \
 132         EBC0_BNCR_BU_RW                         |       \
 133         EBC0_BNCR_BW_8BIT
 134
 135 #define EBC0_BNCR_SMALL_FLASH_CS4                       \
 136         EBC0_BNCR_BAS_ENCODE(0x87F00000)        |       \
 137         EBC0_BNCR_BS_1MB                        |       \
 138         EBC0_BNCR_BU_RW                         |       \
 139         EBC0_BNCR_BW_8BIT
 140
 141 /* Large Flash or SRAM */
 142 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM                   \
 143         EBC0_BNAP_BME_DISABLED                  |       \
 144         EBC0_BNAP_TWT_ENCODE(8)                 |       \
 145         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 146         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 147         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 148         EBC0_BNAP_WBF_ENCODE(1)                 |       \
 149         EBC0_BNAP_TH_ENCODE(2)                  |       \
 150         EBC0_BNAP_SOR_DELAYED                   |       \
 151         EBC0_BNAP_BEM_RW                        |       \
 152         EBC0_BNAP_PEN_DISABLED
 153
 154 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0               \
 155         EBC0_BNCR_BAS_ENCODE(0xFF800000)        |       \
 156         EBC0_BNCR_BS_8MB                        |       \
 157         EBC0_BNCR_BU_RW                         |       \
 158         EBC0_BNCR_BW_16BIT
 159
 160
 161 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4               \
 162         EBC0_BNCR_BAS_ENCODE(0x87800000)        |       \
 163         EBC0_BNCR_BS_8MB                        |       \
 164         EBC0_BNCR_BU_RW                         |       \
 165         EBC0_BNCR_BW_16BIT
 166
 167 /* NVRAM - FPGA */
 168 #define EBC0_BNAP_NVRAM_FPGA                            \
 169         EBC0_BNAP_BME_DISABLED                  |       \
 170         EBC0_BNAP_TWT_ENCODE(9)                 |       \
 171         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 172         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 173         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 174         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 175         EBC0_BNAP_TH_ENCODE(2)                  |       \
 176         EBC0_BNAP_RE_ENABLED                    |       \
 177         EBC0_BNAP_SOR_DELAYED                   |       \
 178         EBC0_BNAP_BEM_WRITEONLY                 |       \
 179         EBC0_BNAP_PEN_DISABLED
 180
 181 #define EBC0_BNCR_NVRAM_FPGA_CS5                        \
 182         EBC0_BNCR_BAS_ENCODE(0x80000000)        |       \
 183         EBC0_BNCR_BS_1MB                        |       \
 184         EBC0_BNCR_BU_RW                         |       \
 185         EBC0_BNCR_BW_8BIT
 186
 187 /* Nand Flash */
 188 #define EBC0_BNAP_NAND_FLASH                            \
 189         EBC0_BNAP_BME_DISABLED                  |       \
 190         EBC0_BNAP_TWT_ENCODE(3)                 |       \
 191         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 192         EBC0_BNAP_OEN_ENCODE(0)                 |       \
 193         EBC0_BNAP_WBN_ENCODE(0)                 |       \
 194         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 195         EBC0_BNAP_TH_ENCODE(1)                  |       \
 196         EBC0_BNAP_RE_ENABLED                    |       \
 197         EBC0_BNAP_SOR_NOT_DELAYED               |       \
 198         EBC0_BNAP_BEM_RW                        |       \
 199         EBC0_BNAP_PEN_DISABLED
 200
 201
 202 #define EBC0_BNCR_NAND_FLASH_CS0        0xB8400000
 203
 204 /* NAND0 */
 205 #define EBC0_BNCR_NAND_FLASH_CS1                        \
 206         EBC0_BNCR_BAS_ENCODE(0x90000000)        |       \
 207         EBC0_BNCR_BS_1MB                        |       \
 208         EBC0_BNCR_BU_RW                         |       \
 209         EBC0_BNCR_BW_32BIT
 210 /* NAND1 - Bank2 */
 211 #define EBC0_BNCR_NAND_FLASH_CS2                        \
 212         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 213         EBC0_BNCR_BS_1MB                        |       \
 214         EBC0_BNCR_BU_RW                         |       \
 215         EBC0_BNCR_BW_32BIT
 216
 217 /* NAND1 - Bank3 */
 218 #define EBC0_BNCR_NAND_FLASH_CS3                        \
 219         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 220         EBC0_BNCR_BS_1MB                        |       \
 221         EBC0_BNCR_BU_RW                         |       \
 222         EBC0_BNCR_BW_32BIT
 223
 224 int board_early_init_f(void)
 225 {
 226         ext_bus_cntlr_init();
 227
 228         /*--------------------------------------------------------------------
 229          * Setup the interrupt controller polarities, triggers, etc.
 230          *-------------------------------------------------------------------*/
 231         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 232         mtdcr(uic0er, 0x00000000);      /* disable all */
 233         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
 234         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 235         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 236         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 237         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 238
 239         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 240         mtdcr(uic1er, 0x00000000);      /* disable all */
 241         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 242         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 243         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 244         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 245         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 246
 247         /*--------------------------------------------------------------------
 248          * Setup the GPIO pins
 249          *-------------------------------------------------------------------*/
 250         out32(GPIO0_OSRL,  0x00000400);
 251         out32(GPIO0_OSRH,  0x00000000);
 252         out32(GPIO0_TSRL,  0x00000400);
 253         out32(GPIO0_TSRH,  0x00000000);
 254         out32(GPIO0_ISR1L, 0x00000000);
 255         out32(GPIO0_ISR1H, 0x00000000);
 256         out32(GPIO0_ISR2L, 0x00000000);
 257         out32(GPIO0_ISR2H, 0x00000000);
 258         out32(GPIO0_ISR3L, 0x00000000);
 259         out32(GPIO0_ISR3H, 0x00000000);
 260
 261         out32(GPIO1_OSRL,  0x0C380000);
 262         out32(GPIO1_OSRH,  0x00000000);
 263         out32(GPIO1_TSRL,  0x0C380000);
 264         out32(GPIO1_TSRH,  0x00000000);
 265         out32(GPIO1_ISR1L, 0x0FC30000);
 266         out32(GPIO1_ISR1H, 0x00000000);
 267         out32(GPIO1_ISR2L, 0x0C010000);
 268         out32(GPIO1_ISR2H, 0x00000000);
 269         out32(GPIO1_ISR3L, 0x01400000);
 270         out32(GPIO1_ISR3H, 0x00000000);
 271
 272         configure_ppc440ep_pins();
 273
 274         return 0;
 275 }
 276
 277 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 278 #include <linux/mtd/nand.h>
 279 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 280
 281 /*----------------------------------------------------------------------------+
 282   | nand_reset.
 283   |   Reset Nand flash
 284   |   This routine will abort previous cmd
 285   +----------------------------------------------------------------------------*/
 286 int nand_reset(ulong addr)
 287 {
 288         int wait=0, stat=0;
 289
 290         out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
 291         out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
 292
 293         while ((stat != 0xc0) && (wait != 0xffff)) {
 294                 stat = in8(addr + NAND_DATA_REG);
 295                 wait++;
 296         }
 297
 298         if (stat == 0xc0) {
 299                 return 0;
 300         } else {
 301                 printf("NAND Reset timeout.\n");
 302                 return -1;
 303         }
 304 }
 305
 306 void board_nand_set_device(int cs, ulong addr)
 307 {
 308         /* Set NandFlash Core Configuration Register */
 309         out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
 310
 311         switch (cs) {
 312         case 1:
 313                 /* -------
 314                  *  NAND0
 315                  * -------
 316                  * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
 317                  * Set NDF1CR - Enable External CS1 in NAND FLASH controller
 318                  */
 319                 out32(addr + NAND_CR1_REG, 0x80002222);
 320                 break;
 321
 322         case 2:
 323                 /* -------
 324                  *  NAND1
 325                  * -------
 326                  * K9K2G0B : 5 addr cyc, 2 col + 3 Row
 327                  * Set NDF2CR : Enable External CS2 in NAND FLASH controller
 328                  */
 329                 out32(addr + NAND_CR2_REG, 0xC0007777);
 330                 break;
 331         }
 332
 333         /* Perform Reset Command */
 334         if (nand_reset(addr) != 0)
 335                 return;
 336 }
 337
 338 void nand_init(void)
 339 {
 340         board_nand_set_device(1, CFG_NAND_ADDR);
 341
 342         nand_probe(CFG_NAND_ADDR);
 343         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 344                 print_size(nand_dev_desc[0].totlen, "\n");
 345         }
 346
 347 #if 0 /* NAND1 not supported yet */
 348         board_nand_set_device(2, CFG_NAND2_ADDR);
 349
 350         nand_probe(CFG_NAND2_ADDR);
 351         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 352                 print_size(nand_dev_desc[0].totlen, "\n");
 353         }
 354 #endif
 355 }
 356 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
 357
 358 int checkboard(void)
 359 {
 360         sys_info_t sysinfo;
 361         unsigned char *s = getenv("serial#");
 362
 363         get_sys_info(&sysinfo);
 364
 365         printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
 366         if (s != NULL) {
 367                 puts(", serial# ");
 368                 puts(s);
 369         }
 370         putc('\n');
 371
 372         printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 373         printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 374         printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 375         printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 376         printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 377
 378         return (0);
 379 }
 380
 381 /*************************************************************************
 382  *
 383  * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
 384  *
 385  * Fixed memory is composed of :
 386  *      MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
 387  *      13 row add bits, 10 column add bits (but 12 row used only).
 388  *      ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
 389  *      12 row add bits, 10 column add bits.
 390  *      Prepare a subset (only the used ones) of SPD data
 391  *
 392  *      Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
 393  *      the corresponding bank is divided by 2 due to number of Row addresses
 394  *      12 in the ECC module
 395  *
 396  *  Assumes:    64 MB, ECC, non-registered
 397  *              PLB @ 133 MHz
 398  *
 399  ************************************************************************/
 400 void fixed_sdram_init(void)
 401 {
 402         /*
 403          * clear this first, if the DDR is enabled by a debugger
 404          * then you can not make changes.
 405          */
 406         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 407
 408         /*--------------------------------------------------------------------
 409          * Setup for board-specific specific mem
 410          *------------------------------------------------------------------*/
 411         /*
 412          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 413          */
 414         mtsdram(mem_b0cr, 0x00082001);
 415         mtsdram(mem_b1cr, 0x00000000);
 416         mtsdram(mem_b2cr, 0x00000000);
 417         mtsdram(mem_b3cr, 0x00000000);
 418 }
 419
 420 long int initdram (int board_type)
 421 {
 422         long dram_size = 0;
 423
 424         /*
 425          * First init bank0 (onboard sdram) and then configure the DIMM-slots
 426          */
 427         fixed_sdram_init();
 428         dram_size = spd_sdram (0);
 429
 430         return dram_size;
 431 }
 432
 433 #if defined(CFG_DRAM_TEST)
 434 int testdram(void)
 435 {
 436         unsigned long *mem = (unsigned long *)0;
 437         const unsigned long kend = (1024 / sizeof(unsigned long));
 438         unsigned long k, n;
 439
 440         mtmsr(0);
 441
 442         for (k = 0; k < CFG_KBYTES_SDRAM;
 443              ++k, mem += (1024 / sizeof(unsigned long))) {
 444                 if ((k & 1023) == 0) {
 445                         printf("%3d MB\r", k / 1024);
 446                 }
 447
 448                 memset(mem, 0xaaaaaaaa, 1024);
 449                 for (n = 0; n < kend; ++n) {
 450                         if (mem[n] != 0xaaaaaaaa) {
 451                                 printf("SDRAM test fails at: %08x\n",
 452                                        (uint) & mem[n]);
 453                                 return 1;
 454                         }
 455                 }
 456
 457                 memset(mem, 0x55555555, 1024);
 458                 for (n = 0; n < kend; ++n) {
 459                         if (mem[n] != 0x55555555) {
 460                                 printf("SDRAM test fails at: %08x\n",
 461                                        (uint) & mem[n]);
 462                                 return 1;
 463                         }
 464                 }
 465         }
 466         printf("SDRAM test passes\n");
 467         return 0;
 468 }
 469 #endif
 470
 471 /*************************************************************************
 472  *  pci_pre_init
 473  *
 474  *  This routine is called just prior to registering the hose and gives
 475  *  the board the opportunity to check things. Returning a value of zero
 476  *  indicates that things are bad & PCI initialization should be aborted.
 477  *
 478  *      Different boards may wish to customize the pci controller structure
 479  *      (add regions, override default access routines, etc) or perform
 480  *      certain pre-initialization actions.
 481  *
 482  ************************************************************************/
 483 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 484 int pci_pre_init(struct pci_controller *hose)
 485 {
 486         unsigned long strap;
 487         unsigned long addr;
 488
 489         /*--------------------------------------------------------------------------+
 490          *      Bamboo is always configured as the host & requires the
 491          *      PCI arbiter to be enabled.
 492          *--------------------------------------------------------------------------*/
 493         mfsdr(sdr_sdstp1, strap);
 494         if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 495                 printf("PCI: SDR0_STRP1[PAE] not set.\n");
 496                 printf("PCI: Configuration aborted.\n");
 497                 return 0;
 498         }
 499
 500         /*-------------------------------------------------------------------------+
 501           | Set priority for all PLB3 devices to 0.
 502           | Set PLB3 arbiter to fair mode.
 503           +-------------------------------------------------------------------------*/
 504         mfsdr(sdr_amp1, addr);
 505         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 506         addr = mfdcr(plb3_acr);
 507         mtdcr(plb3_acr, addr | 0x80000000);
 508
 509         /*-------------------------------------------------------------------------+
 510           | Set priority for all PLB4 devices to 0.
 511           +-------------------------------------------------------------------------*/
 512         mfsdr(sdr_amp0, addr);
 513         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 514         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 515         mtdcr(plb4_acr, addr);
 516
 517         /*-------------------------------------------------------------------------+
 518           | Set Nebula PLB4 arbiter to fair mode.
 519           +-------------------------------------------------------------------------*/
 520         /* Segment0 */
 521         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 522         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 523         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 524         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 525         mtdcr(plb0_acr, addr);
 526
 527         /* Segment1 */
 528         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 529         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 530         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 531         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 532         mtdcr(plb1_acr, addr);
 533
 534         return 1;
 535 }
 536 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 537
 538 /*************************************************************************
 539  *  pci_target_init
 540  *
 541  *      The bootstrap configuration provides default settings for the pci
 542  *      inbound map (PIM). But the bootstrap config choices are limited and
 543  *      may not be sufficient for a given board.
 544  *
 545  ************************************************************************/
 546 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 547 void pci_target_init(struct pci_controller *hose)
 548 {
 549         /*--------------------------------------------------------------------------+
 550          * Set up Direct MMIO registers
 551          *--------------------------------------------------------------------------*/
 552         /*--------------------------------------------------------------------------+
 553           | PowerPC440 EP PCI Master configuration.
 554           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 555           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 556           |   Use byte reversed out routines to handle endianess.
 557           | Make this region non-prefetchable.
 558           +--------------------------------------------------------------------------*/
 559         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 560         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 561         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 562         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 563         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 564
 565         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 566         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 567         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 568         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 569         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 570
 571         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 572         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 573         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 574         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 575
 576         /*--------------------------------------------------------------------------+
 577          * Set up Configuration registers
 578          *--------------------------------------------------------------------------*/
 579
 580         /* Program the board's subsystem id/vendor id */
 581         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 582                               CFG_PCI_SUBSYS_VENDORID);
 583         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 584
 585         /* Configure command register as bus master */
 586         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 587
 588         /* 240nS PCI clock */
 589         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 590
 591         /* No error reporting */
 592         pci_write_config_word(0, PCI_ERREN, 0);
 593
 594         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 595
 596 }
 597 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 598
 599 /*************************************************************************
 600  *  pci_master_init
 601  *
 602  ************************************************************************/
 603 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 604 void pci_master_init(struct pci_controller *hose)
 605 {
 606         unsigned short temp_short;
 607
 608         /*--------------------------------------------------------------------------+
 609           | Write the PowerPC440 EP PCI Configuration regs.
 610           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 611           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 612           +--------------------------------------------------------------------------*/
 613         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 614         pci_write_config_word(0, PCI_COMMAND,
 615                               temp_short | PCI_COMMAND_MASTER |
 616                               PCI_COMMAND_MEMORY);
 617 }
 618 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 619
 620 /*************************************************************************
 621  *  is_pci_host
 622  *
 623  *      This routine is called to determine if a pci scan should be
 624  *      performed. With various hardware environments (especially cPCI and
 625  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 626  *      bit in the strap register, or generic host/adapter assumptions.
 627  *
 628  *      Rather than hard-code a bad assumption in the general 440 code, the
 629  *      440 pci code requires the board to decide at runtime.
 630  *
 631  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 632  *
 633  *
 634  ************************************************************************/
 635 #if defined(CONFIG_PCI)
 636 int is_pci_host(struct pci_controller *hose)
 637 {
 638         /* Bamboo is always configured as host. */
 639         return (1);
 640 }
 641 #endif                          /* defined(CONFIG_PCI) */
 642
 643 /*----------------------------------------------------------------------------+
 644   | is_powerpc440ep_pass1.
 645   +----------------------------------------------------------------------------*/
 646 int is_powerpc440ep_pass1(void)
 647 {
 648         unsigned long pvr;
 649
 650         pvr = get_pvr();
 651
 652         if (pvr == PVR_POWERPC_440EP_PASS1)
 653                 return TRUE;
 654         else if (pvr == PVR_POWERPC_440EP_PASS2)
 655                 return FALSE;
 656         else {
 657                 printf("brdutil error 3\n");
 658                 for (;;)
 659                         ;
 660         }
 661
 662         return(FALSE);
 663 }
 664
 665 /*----------------------------------------------------------------------------+
 666   | is_nand_selected.
 667   +----------------------------------------------------------------------------*/
 668 int is_nand_selected(void)
 669 {
 670 #ifdef CONFIG_BAMBOO_NAND
 671         return TRUE;
 672 #else
 673         return FALSE;
 674 #endif
 675 }
 676
 677 /*----------------------------------------------------------------------------+
 678   | config_on_ebc_cs4_is_small_flash => from EPLD
 679   +----------------------------------------------------------------------------*/
 680 unsigned char config_on_ebc_cs4_is_small_flash(void)
 681 {
 682         /* Not implemented yet => returns constant value */
 683         return TRUE;
 684 }
 685
 686 /*----------------------------------------------------------------------------+
 687   | Ext_bus_cntlr_init.
 688   | Initialize the external bus controller
 689   +----------------------------------------------------------------------------*/
 690 void ext_bus_cntlr_init(void)
 691 {
 692         unsigned long sdr0_pstrp0, sdr0_sdstp1;
 693         unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
 694         int           computed_boot_device = BOOT_DEVICE_UNKNOWN;
 695         unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
 696         unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
 697         unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
 698         unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
 699         unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
 700
 701
 702         /*-------------------------------------------------------------------------+
 703           |
 704           |  PART 1 : Initialize EBC Bank 5
 705           |  ==============================
 706           | Bank5 is always associated to the NVRAM/EPLD.
 707           | It has to be initialized prior to other banks settings computation since
 708           | some board registers values may be needed
 709           |
 710           +-------------------------------------------------------------------------*/
 711         /* NVRAM - FPGA */
 712         mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
 713         mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
 714
 715         /*-------------------------------------------------------------------------+
 716           |
 717           |  PART 2 : Determine which boot device was selected
 718           |  =========================================
 719           |
 720           |  Read Pin Strap Register in PPC440EP
 721           |  In case of boot from IIC, read Serial Device Strap Register1
 722           |
 723           |  Result can either be :
 724           |   - Boot from EBC 8bits    => SMALL FLASH
 725           |   - Boot from EBC 16bits   => Large Flash or SRAM
 726           |   - Boot from NAND Flash
 727           |   - Boot from PCI
 728           |
 729           +-------------------------------------------------------------------------*/
 730         /* Read Pin Strap Register in PPC440EP */
 731         mfsdr(sdr_pstrp0, sdr0_pstrp0);
 732         bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
 733
 734         /*-------------------------------------------------------------------------+
 735           |  PPC440EP Pass1
 736           +-------------------------------------------------------------------------*/
 737         if (is_powerpc440ep_pass1() == TRUE) {
 738                 switch(bootstrap_settings) {
 739                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 740                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 741                         /* Boot from Small Flash */
 742                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 743                         break;
 744                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 745                         /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
 746                         /* Boot from PCI */
 747                         computed_boot_device = BOOT_FROM_PCI;
 748                         break;
 749
 750                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 751                         /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
 752                         /* Boot from Nand Flash */
 753                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 754                         break;
 755
 756                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 757                         /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
 758                         /* Boot from Small Flash */
 759                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 760                         break;
 761
 762                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 763                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 764                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 765                         /* Read Serial Device Strap Register1 in PPC440EP */
 766                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 767                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 768                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 769
 770                         switch(boot_selection) {
 771                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 772                                 switch(ebc_boot_size) {
 773                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 774                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 775                                         break;
 776                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 777                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 778                                         break;
 779                                 }
 780                                 break;
 781
 782                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 783                                 computed_boot_device = BOOT_FROM_PCI;
 784                                 break;
 785
 786                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 787                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 788                                 break;
 789                         }
 790                         break;
 791                 }
 792         }
 793
 794         /*-------------------------------------------------------------------------+
 795           |  PPC440EP Pass2
 796           +-------------------------------------------------------------------------*/
 797         else {
 798                 switch(bootstrap_settings) {
 799                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 800                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 801                         /* Boot from Small Flash */
 802                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 803                         break;
 804                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 805                         /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
 806                         /* Boot from PCI */
 807                         computed_boot_device = BOOT_FROM_PCI;
 808                         break;
 809
 810                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 811                         /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
 812                         /* Boot from Nand Flash */
 813                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 814                         break;
 815
 816                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 817                         /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
 818                         /* Boot from Large Flash or SRAM */
 819                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 820                         break;
 821
 822                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
 823                         /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
 824                         /* Boot from Large Flash or SRAM */
 825                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 826                         break;
 827
 828                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
 829                         /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
 830                         /* Boot from PCI */
 831                         computed_boot_device = BOOT_FROM_PCI;
 832                         break;
 833
 834                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 835                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 836                         /* Default Strap Settings 5-7 */
 837                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 838                         /* Read Serial Device Strap Register1 in PPC440EP */
 839                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 840                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 841                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 842
 843                         switch(boot_selection) {
 844                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 845                                 switch(ebc_boot_size) {
 846                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 847                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 848                                         break;
 849                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 850                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 851                                         break;
 852                                 }
 853                                 break;
 854
 855                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 856                                 computed_boot_device = BOOT_FROM_PCI;
 857                                 break;
 858
 859                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 860                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 861                                 break;
 862                         }
 863                         break;
 864                 }
 865         }
 866
 867         /*-------------------------------------------------------------------------+
 868           |
 869           |  PART 3 : Compute EBC settings depending on selected boot device
 870           |  ======   ======================================================
 871           |
 872           | Resulting EBC init will be among following configurations :
 873           |
 874           |  - Boot from EBC 8bits => boot from SMALL FLASH selected
 875           |            EBC-CS0     = Small Flash
 876           |            EBC-CS1,2,3 = NAND Flash or
 877           |                         Exp.Slot depending on Soft Config
 878           |            EBC-CS4     = SRAM/Large Flash or
 879           |                         Large Flash/SRAM depending on jumpers
 880           |            EBC-CS5     = NVRAM / EPLD
 881           |
 882           |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
 883           |            EBC-CS0     = SRAM/Large Flash or
 884           |                          Large Flash/SRAM depending on jumpers
 885           |            EBC-CS1,2,3 = NAND Flash or
 886           |                          Exp.Slot depending on Software Configuration
 887           |            EBC-CS4     = Small Flash
 888           |            EBC-CS5     = NVRAM / EPLD
 889           |
 890           |  - Boot from NAND Flash
 891           |            EBC-CS0     = NAND Flash0
 892           |            EBC-CS1,2,3 = NAND Flash1
 893           |            EBC-CS4     = SRAM/Large Flash or
 894           |                          Large Flash/SRAM depending on jumpers
 895           |            EBC-CS5     = NVRAM / EPLD
 896           |
 897           |    - Boot from PCI
 898           |            EBC-CS0     = ...
 899           |            EBC-CS1,2,3 = NAND Flash or
 900           |                          Exp.Slot depending on Software Configuration
 901           |            EBC-CS4     = SRAM/Large Flash or
 902           |                          Large Flash/SRAM or
 903           |                          Small Flash depending on jumpers
 904           |            EBC-CS5     = NVRAM / EPLD
 905           |
 906           +-------------------------------------------------------------------------*/
 907
 908         switch(computed_boot_device) {
 909                 /*------------------------------------------------------------------------- */
 910         case BOOT_FROM_SMALL_FLASH:
 911                 /*------------------------------------------------------------------------- */
 912                 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
 913                 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
 914                 if ((is_nand_selected()) == TRUE) {
 915                         /* NAND Flash */
 916                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 917                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 918                         ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
 919                         ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
 920                         ebc0_cs3_bnap_value = 0;
 921                         ebc0_cs3_bncr_value = 0;
 922                 } else {
 923                         /* Expansion Slot */
 924                         ebc0_cs1_bnap_value = 0;
 925                         ebc0_cs1_bncr_value = 0;
 926                         ebc0_cs2_bnap_value = 0;
 927                         ebc0_cs2_bncr_value = 0;
 928                         ebc0_cs3_bnap_value = 0;
 929                         ebc0_cs3_bncr_value = 0;
 930                 }
 931                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 932                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 933
 934                 break;
 935
 936                 /*------------------------------------------------------------------------- */
 937         case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 938                 /*------------------------------------------------------------------------- */
 939                 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 940                 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
 941                 if ((is_nand_selected()) == TRUE) {
 942                         /* NAND Flash */
 943                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 944                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 945                         ebc0_cs2_bnap_value = 0;
 946                         ebc0_cs2_bncr_value = 0;
 947                         ebc0_cs3_bnap_value = 0;
 948                         ebc0_cs3_bncr_value = 0;
 949                 } else {
 950                         /* Expansion Slot */
 951                         ebc0_cs1_bnap_value = 0;
 952                         ebc0_cs1_bncr_value = 0;
 953                         ebc0_cs2_bnap_value = 0;
 954                         ebc0_cs2_bncr_value = 0;
 955                         ebc0_cs3_bnap_value = 0;
 956                         ebc0_cs3_bncr_value = 0;
 957                 }
 958                 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 959                 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 960
 961                 break;
 962
 963                 /*------------------------------------------------------------------------- */
 964         case BOOT_FROM_NAND_FLASH0:
 965                 /*------------------------------------------------------------------------- */
 966                 ebc0_cs0_bnap_value = 0;
 967                 ebc0_cs0_bncr_value = 0;
 968
 969                 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 970                 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 971                 ebc0_cs2_bnap_value = 0;
 972                 ebc0_cs2_bncr_value = 0;
 973                 ebc0_cs3_bnap_value = 0;
 974                 ebc0_cs3_bncr_value = 0;
 975
 976                 /* Large Flash or SRAM */
 977                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 978                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 979
 980                 break;
 981
 982                 /*------------------------------------------------------------------------- */
 983         case BOOT_FROM_PCI:
 984                 /*------------------------------------------------------------------------- */
 985                 ebc0_cs0_bnap_value = 0;
 986                 ebc0_cs0_bncr_value = 0;
 987
 988                 if ((is_nand_selected()) == TRUE) {
 989                         /* NAND Flash */
 990                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 991                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 992                         ebc0_cs2_bnap_value = 0;
 993                         ebc0_cs2_bncr_value = 0;
 994                         ebc0_cs3_bnap_value = 0;
 995                         ebc0_cs3_bncr_value = 0;
 996                 } else {
 997                         /* Expansion Slot */
 998                         ebc0_cs1_bnap_value = 0;
 999                         ebc0_cs1_bncr_value = 0;
1000                         ebc0_cs2_bnap_value = 0;
1001                         ebc0_cs2_bncr_value = 0;
1002                         ebc0_cs3_bnap_value = 0;
1003                         ebc0_cs3_bncr_value = 0;
1004                 }
1005
1006                 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
1007                         /* Small Flash */
1008                         ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
1009                         ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
1010                 } else {
1011                         /* Large Flash or SRAM */
1012                         ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
1013                         ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1014                 }
1015
1016                 break;
1017
1018                 /*------------------------------------------------------------------------- */
1019         case BOOT_DEVICE_UNKNOWN:
1020                 /*------------------------------------------------------------------------- */
1021                 /* Error */
1022                 break;
1023
1024         }
1025
1026
1027         /*-------------------------------------------------------------------------+
1028           | Initialize EBC CONFIG
1029           +-------------------------------------------------------------------------*/
1030         mtdcr(ebccfga, xbcfg);
1031         mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN        |
1032               EBC0_CFG_PTD_ENABLED        |
1033               EBC0_CFG_RTC_2048PERCLK     |
1034               EBC0_CFG_EMPL_LOW           |
1035               EBC0_CFG_EMPH_LOW           |
1036               EBC0_CFG_CSTC_DRIVEN        |
1037               EBC0_CFG_BPF_ONEDW          |
1038               EBC0_CFG_EMS_8BIT           |
1039               EBC0_CFG_PME_DISABLED       |
1040               EBC0_CFG_PMT_ENCODE(0)      );
1041
1042         /*-------------------------------------------------------------------------+
1043           | Initialize EBC Bank 0-4
1044           +-------------------------------------------------------------------------*/
1045         /* EBC Bank0 */
1046         mtebc(pb0ap, ebc0_cs0_bnap_value);
1047         mtebc(pb0cr, ebc0_cs0_bncr_value);
1048         /* EBC Bank1 */
1049         mtebc(pb1ap, ebc0_cs1_bnap_value);
1050         mtebc(pb1cr, ebc0_cs1_bncr_value);
1051         /* EBC Bank2 */
1052         mtebc(pb2ap, ebc0_cs2_bnap_value);
1053         mtebc(pb2cr, ebc0_cs2_bncr_value);
1054         /* EBC Bank3 */
1055         mtebc(pb3ap, ebc0_cs3_bnap_value);
1056         mtebc(pb3cr, ebc0_cs3_bncr_value);
1057         /* EBC Bank4 */
1058         mtebc(pb4ap, ebc0_cs4_bnap_value);
1059         mtebc(pb4cr, ebc0_cs4_bncr_value);
1060
1061         return;
1062 }
1063
1064
1065 /*----------------------------------------------------------------------------+
1066   | get_uart_configuration.
1067   +----------------------------------------------------------------------------*/
1068 uart_config_nb_t get_uart_configuration(void)
1069 {
1070         return (L4);
1071 }
1072
1073 /*----------------------------------------------------------------------------+
1074   | set_phy_configuration_through_fpga => to EPLD
1075   +----------------------------------------------------------------------------*/
1076 void set_phy_configuration_through_fpga(zmii_config_t config)
1077 {
1078
1079         unsigned long fpga_selection_reg;
1080
1081         fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1082
1083         switch(config)
1084         {
1085         case ZMII_CONFIGURATION_IS_MII:
1086                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1087                 break;
1088         case ZMII_CONFIGURATION_IS_RMII:
1089                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1090                 break;
1091         case ZMII_CONFIGURATION_IS_SMII:
1092                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1093                 break;
1094         case ZMII_CONFIGURATION_UNKNOWN:
1095         default:
1096                 break;
1097         }
1098         out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1099
1100 }
1101
1102 /*----------------------------------------------------------------------------+
1103   | scp_selection_in_fpga.
1104   +----------------------------------------------------------------------------*/
1105 void scp_selection_in_fpga(void)
1106 {
1107         unsigned long fpga_selection_2_reg;
1108
1109         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1110         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1111         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1112 }
1113
1114 /*----------------------------------------------------------------------------+
1115   | iic1_selection_in_fpga.
1116   +----------------------------------------------------------------------------*/
1117 void iic1_selection_in_fpga(void)
1118 {
1119         unsigned long fpga_selection_2_reg;
1120
1121         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1122         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1123         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1124 }
1125
1126 /*----------------------------------------------------------------------------+
1127   | dma_a_b_selection_in_fpga.
1128   +----------------------------------------------------------------------------*/
1129 void dma_a_b_selection_in_fpga(void)
1130 {
1131         unsigned long fpga_selection_2_reg;
1132
1133         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1134         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1135 }
1136
1137 /*----------------------------------------------------------------------------+
1138   | dma_a_b_unselect_in_fpga.
1139   +----------------------------------------------------------------------------*/
1140 void dma_a_b_unselect_in_fpga(void)
1141 {
1142         unsigned long fpga_selection_2_reg;
1143
1144         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1145         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1146 }
1147
1148 /*----------------------------------------------------------------------------+
1149   | dma_c_d_selection_in_fpga.
1150   +----------------------------------------------------------------------------*/
1151 void dma_c_d_selection_in_fpga(void)
1152 {
1153         unsigned long fpga_selection_2_reg;
1154
1155         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1156         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1157 }
1158
1159 /*----------------------------------------------------------------------------+
1160   | dma_c_d_unselect_in_fpga.
1161   +----------------------------------------------------------------------------*/
1162 void dma_c_d_unselect_in_fpga(void)
1163 {
1164         unsigned long fpga_selection_2_reg;
1165
1166         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1167         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1168 }
1169
1170 /*----------------------------------------------------------------------------+
1171   | usb2_device_selection_in_fpga.
1172   +----------------------------------------------------------------------------*/
1173 void usb2_device_selection_in_fpga(void)
1174 {
1175         unsigned long fpga_selection_1_reg;
1176
1177         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1178         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1179 }
1180
1181 /*----------------------------------------------------------------------------+
1182   | usb2_device_reset_through_fpga.
1183   +----------------------------------------------------------------------------*/
1184 void usb2_device_reset_through_fpga(void)
1185 {
1186         /* Perform soft Reset pulse */
1187         unsigned long fpga_reset_reg;
1188         int i;
1189
1190         fpga_reset_reg = in8(FPGA_RESET_REG);
1191         out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1192         for (i=0; i<500; i++)
1193                 udelay(1000);
1194         out8(FPGA_RESET_REG,fpga_reset_reg);
1195 }
1196
1197 /*----------------------------------------------------------------------------+
1198   | usb2_host_selection_in_fpga.
1199   +----------------------------------------------------------------------------*/
1200 void usb2_host_selection_in_fpga(void)
1201 {
1202         unsigned long fpga_selection_1_reg;
1203
1204         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1205         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1206 }
1207
1208 /*----------------------------------------------------------------------------+
1209   | ndfc_selection_in_fpga.
1210   +----------------------------------------------------------------------------*/
1211 void ndfc_selection_in_fpga(void)
1212 {
1213         unsigned long fpga_selection_1_reg;
1214
1215         fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1216         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1217         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1218         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1219 }
1220
1221 /*----------------------------------------------------------------------------+
1222   | uart_selection_in_fpga.
1223   +----------------------------------------------------------------------------*/
1224 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1225 {
1226         /* FPGA register */
1227         unsigned char   fpga_selection_3_reg;
1228
1229         /* Read FPGA Reagister */
1230         fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1231
1232         switch (uart_config)
1233         {
1234         case L1:
1235                 /* ----------------------------------------------------------------------- */
1236                 /* L1 configuration:    UART0 = 8 pins */
1237                 /* ----------------------------------------------------------------------- */
1238                 /* Configure FPGA */
1239                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1240                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1241                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1242
1243                 break;
1244
1245         case L2:
1246                 /* ----------------------------------------------------------------------- */
1247                 /* L2 configuration:    UART0 = 4 pins */
1248                 /*                      UART1 = 4 pins */
1249                 /* ----------------------------------------------------------------------- */
1250                 /* Configure FPGA */
1251                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1252                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1253                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1254
1255                 break;
1256
1257         case L3:
1258                 /* ----------------------------------------------------------------------- */
1259                 /* L3 configuration:    UART0 = 4 pins */
1260                 /*                      UART1 = 2 pins */
1261                 /*                      UART2 = 2 pins */
1262                 /* ----------------------------------------------------------------------- */
1263                 /* Configure FPGA */
1264                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1265                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1266                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1267                 break;
1268
1269         case L4:
1270                 /* Configure FPGA */
1271                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1272                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1273                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1274
1275                 break;
1276
1277         default:
1278                 /* Unsupported UART configuration number */
1279                 for (;;)
1280                         ;
1281                 break;
1282
1283         }
1284 }
1285
1286
1287 /*----------------------------------------------------------------------------+
1288   | init_default_gpio
1289   +----------------------------------------------------------------------------*/
1290 void init_default_gpio(void)
1291 {
1292         int i;
1293
1294         /* Init GPIO0 */
1295         for(i=0; i<GPIO_MAX; i++)
1296         {
1297                 gpio_tab[GPIO0][i].add    = GPIO0_BASE;
1298                 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1299                 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1300         }
1301
1302         /* Init GPIO1 */
1303         for(i=0; i<GPIO_MAX; i++)
1304         {
1305                 gpio_tab[GPIO1][i].add    = GPIO1_BASE;
1306                 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1307                 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1308         }
1309
1310         /* EBC_CS_N(5) - GPIO0_10 */
1311         gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
1312         gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
1313
1314         /* EBC_CS_N(4) - GPIO0_9 */
1315         gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
1316         gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
1317 }
1318
1319 /*----------------------------------------------------------------------------+
1320   | update_uart_ios
1321   +------------------------------------------------------------------------------
1322   |
1323   | Set UART Configuration in PowerPC440EP
1324   |
1325   | +---------------------------------------------------------------------+
1326   | | Configuartion   |   Connector   | Nb of pins | Pins   | Associated  |
1327   | |    Number       |   Port Name   |  available | naming |   CORE      |
1328   | +-----------------+---------------+------------+--------+-------------+
1329   | |     L1          |   Port_A      |     8      | UART   | UART core 0 |
1330   | +-----------------+---------------+------------+--------+-------------+
1331   | |     L2          |   Port_A      |     4      | UART1  | UART core 0 |
1332   | |    (L2D)        |   Port_B      |     4      | UART2  | UART core 1 |
1333   | +-----------------+---------------+------------+--------+-------------+
1334   | |     L3          |   Port_A      |     4      | UART1  | UART core 0 |
1335   | |    (L3D)        |   Port_B      |     2      | UART2  | UART core 1 |
1336   | |                 |   Port_C      |     2      | UART3  | UART core 2 |
1337   | +-----------------+---------------+------------+--------+-------------+
1338   | |                 |   Port_A      |     2      | UART1  | UART core 0 |
1339   | |     L4          |   Port_B      |     2      | UART2  | UART core 1 |
1340   | |    (L4D)        |   Port_C      |     2      | UART3  | UART core 2 |
1341   | |                 |   Port_D      |     2      | UART4  | UART core 3 |
1342   | +-----------------+---------------+------------+--------+-------------+
1343   |
1344   |  Involved GPIOs
1345   |
1346   | +------------------------------------------------------------------------------+
1347   | |  GPIO   |   Aternate 1     | I/O |  Alternate 2    | I/O | Alternate 3 | I/O |
1348   | +---------+------------------+-----+-----------------+-----+-------------+-----+
1349   | | GPIO1_2 | UART0_DCD_N      |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |  O  |
1350   | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |  I  |
1351   | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA              |  NA | UART3_SIN   |  I  |
1352   | | GPIO1_5 | UART0_RTS_N      |  O  | NA              |  NA | UART3_SOUT  |  O  |
1353   | | GPIO1_6 | UART0_DTR_N      |  O  | UART1_SOUT      |  O  | NA          |  NA |
1354   | | GPIO1_7 | UART0_RI_N       |  I  | UART1_SIN       |  I  | NA          |  NA |
1355   | +------------------------------------------------------------------------------+
1356   |
1357   |
1358   +----------------------------------------------------------------------------*/
1359
1360 void update_uart_ios(uart_config_nb_t uart_config)
1361 {
1362         switch (uart_config)
1363         {
1364         case L1:
1365                 /* ----------------------------------------------------------------------- */
1366                 /* L1 configuration:    UART0 = 8 pins */
1367                 /* ----------------------------------------------------------------------- */
1368                 /* Update GPIO Configuration Table */
1369                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1370                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1371
1372                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1373                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1374
1375                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1376                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1377
1378                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1379                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1380
1381                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1382                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1383
1384                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1385                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1386
1387                 break;
1388
1389         case L2:
1390                 /* ----------------------------------------------------------------------- */
1391                 /* L2 configuration:    UART0 = 4 pins */
1392                 /*                      UART1 = 4 pins */
1393                 /* ----------------------------------------------------------------------- */
1394                 /* Update GPIO Configuration Table */
1395                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1396                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1397
1398                 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1399                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1400
1401                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1402                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1403
1404                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1405                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1406
1407                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1408                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1409
1410                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1411                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1412
1413                 break;
1414
1415         case L3:
1416                 /* ----------------------------------------------------------------------- */
1417                 /* L3 configuration:    UART0 = 4 pins */
1418                 /*                      UART1 = 2 pins */
1419                 /*                      UART2 = 2 pins */
1420                 /* ----------------------------------------------------------------------- */
1421                 /* Update GPIO Configuration Table */
1422                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1423                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1424
1425                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1426                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1427
1428                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1429                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1430
1431                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1432                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1433
1434                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1435                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1436
1437                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1438                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1439
1440                 break;
1441
1442         case L4:
1443                 /* ----------------------------------------------------------------------- */
1444                 /* L4 configuration:    UART0 = 2 pins */
1445                 /*                      UART1 = 2 pins */
1446                 /*                      UART2 = 2 pins */
1447                 /*                      UART3 = 2 pins */
1448                 /* ----------------------------------------------------------------------- */
1449                 /* Update GPIO Configuration Table */
1450                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1451                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1452
1453                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1454                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1455
1456                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1457                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1458
1459                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1460                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1461
1462                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1463                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1464
1465                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1466                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1467
1468                 break;
1469
1470         default:
1471                 /* Unsupported UART configuration number */
1472                 printf("ERROR - Unsupported UART configuration number.\n\n");
1473                 for (;;)
1474                         ;
1475                 break;
1476
1477         }
1478
1479         /* Set input Selection Register on Alt_Receive for UART Input Core */
1480         out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1481         out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1482         out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1483 }
1484
1485 /*----------------------------------------------------------------------------+
1486   | update_ndfc_ios(void).
1487   +----------------------------------------------------------------------------*/
1488 void update_ndfc_ios(void)
1489 {
1490         /* Update GPIO Configuration Table */
1491         gpio_tab[GPIO0][6].in_out = GPIO_OUT;       /* EBC_CS_N(1) */
1492         gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1493
1494 #if 0
1495         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(2) */
1496         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1497
1498         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(3) */
1499         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1500 #endif
1501 }
1502
1503 /*----------------------------------------------------------------------------+
1504   | update_zii_ios(void).
1505   +----------------------------------------------------------------------------*/
1506 void update_zii_ios(void)
1507 {
1508         /* Update GPIO Configuration Table */
1509         gpio_tab[GPIO0][12].in_out = GPIO_IN;       /* ZII_p0Rxd(0) */
1510         gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1511
1512         gpio_tab[GPIO0][13].in_out = GPIO_IN;       /* ZII_p0Rxd(1) */
1513         gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1514
1515         gpio_tab[GPIO0][14].in_out = GPIO_IN;       /* ZII_p0Rxd(2) */
1516         gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1517
1518         gpio_tab[GPIO0][15].in_out = GPIO_IN;       /* ZII_p0Rxd(3) */
1519         gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1520
1521         gpio_tab[GPIO0][16].in_out = GPIO_OUT;      /* ZII_p0Txd(0) */
1522         gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1523
1524         gpio_tab[GPIO0][17].in_out = GPIO_OUT;      /* ZII_p0Txd(1) */
1525         gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1526
1527         gpio_tab[GPIO0][18].in_out = GPIO_OUT;      /* ZII_p0Txd(2) */
1528         gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1529
1530         gpio_tab[GPIO0][19].in_out = GPIO_OUT;      /* ZII_p0Txd(3) */
1531         gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1532
1533         gpio_tab[GPIO0][20].in_out = GPIO_IN;       /* ZII_p0Rx_er */
1534         gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1535
1536         gpio_tab[GPIO0][21].in_out = GPIO_IN;       /* ZII_p0Rx_dv */
1537         gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1538
1539         gpio_tab[GPIO0][22].in_out = GPIO_IN;       /* ZII_p0Crs */
1540         gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1541
1542         gpio_tab[GPIO0][23].in_out = GPIO_OUT;      /* ZII_p0Tx_er */
1543         gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1544
1545         gpio_tab[GPIO0][24].in_out = GPIO_OUT;      /* ZII_p0Tx_en */
1546         gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1547
1548         gpio_tab[GPIO0][25].in_out = GPIO_IN;       /* ZII_p0Col */
1549         gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1550
1551 }
1552
1553 /*----------------------------------------------------------------------------+
1554   | update_uic_0_3_irq_ios().
1555   +----------------------------------------------------------------------------*/
1556 void update_uic_0_3_irq_ios(void)
1557 {
1558         gpio_tab[GPIO1][8].in_out = GPIO_IN;        /* UIC_IRQ(0) */
1559         gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1560
1561         gpio_tab[GPIO1][9].in_out = GPIO_IN;        /* UIC_IRQ(1) */
1562         gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1563
1564         gpio_tab[GPIO1][10].in_out = GPIO_IN;       /* UIC_IRQ(2) */
1565         gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1566
1567         gpio_tab[GPIO1][11].in_out = GPIO_IN;       /* UIC_IRQ(3) */
1568         gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1569 }
1570
1571 /*----------------------------------------------------------------------------+
1572   | update_uic_4_9_irq_ios().
1573   +----------------------------------------------------------------------------*/
1574 void update_uic_4_9_irq_ios(void)
1575 {
1576         gpio_tab[GPIO1][12].in_out = GPIO_IN;       /* UIC_IRQ(4) */
1577         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1578
1579         gpio_tab[GPIO1][13].in_out = GPIO_IN;       /* UIC_IRQ(6) */
1580         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1581
1582         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* UIC_IRQ(7) */
1583         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1584
1585         gpio_tab[GPIO1][15].in_out = GPIO_IN;       /* UIC_IRQ(8) */
1586         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1587
1588         gpio_tab[GPIO1][16].in_out = GPIO_IN;       /* UIC_IRQ(9) */
1589         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1590 }
1591
1592 /*----------------------------------------------------------------------------+
1593   | update_dma_a_b_ios().
1594   +----------------------------------------------------------------------------*/
1595 void update_dma_a_b_ios(void)
1596 {
1597         gpio_tab[GPIO1][12].in_out = GPIO_OUT;      /* DMA_ACK(1) */
1598         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1599
1600         gpio_tab[GPIO1][13].in_out = GPIO_BI;       /* DMA_EOT/TC(1) */
1601         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1602
1603         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* DMA_REQ(0) */
1604         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1605
1606         gpio_tab[GPIO1][15].in_out = GPIO_OUT;      /* DMA_ACK(0) */
1607         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1608
1609         gpio_tab[GPIO1][16].in_out = GPIO_BI;       /* DMA_EOT/TC(0) */
1610         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1611 }
1612
1613 /*----------------------------------------------------------------------------+
1614   | update_dma_c_d_ios().
1615   +----------------------------------------------------------------------------*/
1616 void update_dma_c_d_ios(void)
1617 {
1618         gpio_tab[GPIO0][0].in_out = GPIO_IN;        /* DMA_REQ(2) */
1619         gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1620
1621         gpio_tab[GPIO0][1].in_out = GPIO_OUT;       /* DMA_ACK(2) */
1622         gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1623
1624         gpio_tab[GPIO0][2].in_out = GPIO_BI;        /* DMA_EOT/TC(2) */
1625         gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1626
1627         gpio_tab[GPIO0][3].in_out = GPIO_IN;        /* DMA_REQ(3) */
1628         gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1629
1630         gpio_tab[GPIO0][4].in_out = GPIO_OUT;       /* DMA_ACK(3) */
1631         gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1632
1633         gpio_tab[GPIO0][5].in_out = GPIO_BI;        /* DMA_EOT/TC(3) */
1634         gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1635
1636 }
1637
1638 /*----------------------------------------------------------------------------+
1639   | update_ebc_master_ios().
1640   +----------------------------------------------------------------------------*/
1641 void update_ebc_master_ios(void)
1642 {
1643         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* EXT_EBC_REQ */
1644         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1645
1646         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1647         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1648
1649         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* EBC_EXT_ACK */
1650         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1651
1652         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* EBC_EXR_BUSREQ */
1653         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1654 }
1655
1656 /*----------------------------------------------------------------------------+
1657   | update_usb2_device_ios().
1658   +----------------------------------------------------------------------------*/
1659 void update_usb2_device_ios(void)
1660 {
1661         gpio_tab[GPIO0][26].in_out = GPIO_IN;       /* USB2D_RXVALID */
1662         gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1663
1664         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* USB2D_RXERROR */
1665         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1666
1667         gpio_tab[GPIO0][28].in_out = GPIO_OUT;      /* USB2D_TXVALID */
1668         gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1669
1670         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* USB2D_PAD_SUSPNDM */
1671         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1672
1673         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* USB2D_XCVRSELECT */
1674         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1675
1676         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* USB2D_TERMSELECT */
1677         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1678
1679         gpio_tab[GPIO1][0].in_out = GPIO_OUT;       /* USB2D_OPMODE0 */
1680         gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1681
1682         gpio_tab[GPIO1][1].in_out = GPIO_OUT;       /* USB2D_OPMODE1 */
1683         gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1684
1685 }
1686
1687 /*----------------------------------------------------------------------------+
1688   | update_pci_patch_ios().
1689   +----------------------------------------------------------------------------*/
1690 void update_pci_patch_ios(void)
1691 {
1692         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1693         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1694 }
1695
1696 /*----------------------------------------------------------------------------+
1697   |   set_chip_gpio_configuration(unsigned char gpio_core)
1698   |   Put the core impacted by clock modification and sharing in reset.
1699   |   Config the select registers to resolve the sharing depending of the config.
1700   |   Configure the GPIO registers.
1701   |
1702   +----------------------------------------------------------------------------*/
1703 void set_chip_gpio_configuration(unsigned char gpio_core)
1704 {
1705         unsigned char i=0, j=0, reg_offset = 0;
1706         unsigned long gpio_reg, gpio_core_add;
1707
1708         /* GPIO config of the GPIOs 0 to 31 */
1709         for (i=0; i<GPIO_MAX; i++, j++)
1710         {
1711                 if (i == GPIO_MAX/2)
1712                 {
1713                         reg_offset = 4;
1714                         j = i-16;
1715                 }
1716
1717                 gpio_core_add = gpio_tab[gpio_core][i].add;
1718
1719                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1720                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1721                 {
1722                         switch (gpio_tab[gpio_core][i].alt_nb)
1723                         {
1724                         case GPIO_SEL:
1725                                 break;
1726
1727                         case GPIO_ALT1:
1728                                 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1729                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1730                                 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1731                                 break;
1732
1733                         case GPIO_ALT2:
1734                                 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1735                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1736                                 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1737                                 break;
1738
1739                         case GPIO_ALT3:
1740                                 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1741                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1742                                 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1743                                 break;
1744                         }
1745                 }
1746                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1747                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1748                 {
1749
1750                         switch (gpio_tab[gpio_core][i].alt_nb)
1751                         {
1752                         case GPIO_SEL:
1753                                 break;
1754                         case GPIO_ALT1:
1755                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1756                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1757                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1758                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1759                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1760                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1761                                 break;
1762                         case GPIO_ALT2:
1763                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1764                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1765                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1766                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1767                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1768                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1769                                 break;
1770                         case GPIO_ALT3:
1771                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1772                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1773                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1774                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1775                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1776                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1777                                 break;
1778                         }
1779                 }
1780         }
1781 }
1782
1783 /*----------------------------------------------------------------------------+
1784   | force_bup_core_selection.
1785   +----------------------------------------------------------------------------*/
1786 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1787 {
1788         /* Pointer invalid */
1789         if (core_select_P == NULL)
1790         {
1791                 printf("Configuration invalid pointer 1\n");
1792                 for (;;)
1793                         ;
1794         }
1795
1796         /* L4 Selection */
1797         *(core_select_P+UART_CORE0)            = CORE_SELECTED;
1798         *(core_select_P+UART_CORE1)            = CORE_SELECTED;
1799         *(core_select_P+UART_CORE2)            = CORE_SELECTED;
1800         *(core_select_P+UART_CORE3)            = CORE_SELECTED;
1801
1802         /* RMII Selection */
1803         *(core_select_P+RMII_SEL)               = CORE_SELECTED;
1804
1805         /* External Interrupt 0-9 selection */
1806         *(core_select_P+UIC_0_3)                = CORE_SELECTED;
1807         *(core_select_P+UIC_4_9)                = CORE_SELECTED;
1808
1809         *(core_select_P+SCP_CORE)               = CORE_SELECTED;
1810         *(core_select_P+DMA_CHANNEL_CD)         = CORE_SELECTED;
1811         *(core_select_P+PACKET_REJ_FUNC_AVAIL)  = CORE_SELECTED;
1812         *(core_select_P+USB1_DEVICE)            = CORE_SELECTED;
1813
1814         if (is_nand_selected()) {
1815                 *(core_select_P+NAND_FLASH)     = CORE_SELECTED;
1816         }
1817
1818         *config_val_P = CONFIG_IS_VALID;
1819
1820 }
1821
1822 /*----------------------------------------------------------------------------+
1823   | configure_ppc440ep_pins.
1824   +----------------------------------------------------------------------------*/
1825 void configure_ppc440ep_pins(void)
1826 {
1827         uart_config_nb_t uart_configuration;
1828         config_validity_t config_val = CONFIG_IS_INVALID;
1829
1830         /* Create Core Selection Table */
1831         core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1832                 {
1833                         CORE_NOT_SELECTED,      /* IIC_CORE, */
1834                         CORE_NOT_SELECTED,      /* SPC_CORE, */
1835                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_AB, */
1836                         CORE_NOT_SELECTED,      /* UIC_4_9, */
1837                         CORE_NOT_SELECTED,      /* USB2_HOST, */
1838                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_CD, */
1839                         CORE_NOT_SELECTED,      /* USB2_DEVICE, */
1840                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_AVAIL, */
1841                         CORE_NOT_SELECTED,      /* USB1_DEVICE, */
1842                         CORE_NOT_SELECTED,      /* EBC_MASTER, */
1843                         CORE_NOT_SELECTED,      /* NAND_FLASH, */
1844                         CORE_NOT_SELECTED,      /* UART_CORE0, */
1845                         CORE_NOT_SELECTED,      /* UART_CORE1, */
1846                         CORE_NOT_SELECTED,      /* UART_CORE2, */
1847                         CORE_NOT_SELECTED,      /* UART_CORE3, */
1848                         CORE_NOT_SELECTED,      /* MII_SEL, */
1849                         CORE_NOT_SELECTED,      /* RMII_SEL, */
1850                         CORE_NOT_SELECTED,      /* SMII_SEL, */
1851                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_EN */
1852                         CORE_NOT_SELECTED,      /* UIC_0_3 */
1853                         CORE_NOT_SELECTED,      /* USB1_HOST */
1854                         CORE_NOT_SELECTED       /* PCI_PATCH */
1855                 };
1856
1857
1858         /* Table Default Initialisation + FPGA Access */
1859         init_default_gpio();
1860         set_chip_gpio_configuration(GPIO0);
1861         set_chip_gpio_configuration(GPIO1);
1862
1863         /* Update Table */
1864         force_bup_core_selection(ppc440ep_core_selection, &config_val);
1865 #if 0 /* test-only */
1866         /* If we are running PIBS 1, force known configuration */
1867         update_core_selection_table(ppc440ep_core_selection, &config_val);
1868 #endif
1869
1870         /*----------------------------------------------------------------------------+
1871           | SDR + ios table update + fpga initialization
1872           +----------------------------------------------------------------------------*/
1873         unsigned long sdr0_pfc1     = 0;
1874         unsigned long sdr0_usb0     = 0;
1875         unsigned long sdr0_mfr      = 0;
1876
1877         /* PCI Always selected */
1878
1879         /* I2C Selection */
1880         if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1881         {
1882                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1883                 iic1_selection_in_fpga();
1884         }
1885
1886         /* SCP Selection */
1887         if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1888         {
1889                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1890                 scp_selection_in_fpga();
1891         }
1892
1893         /* UIC 0:3 Selection */
1894         if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1895         {
1896                 update_uic_0_3_irq_ios();
1897                 dma_a_b_unselect_in_fpga();
1898         }
1899
1900         /* UIC 4:9 Selection */
1901         if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1902         {
1903                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1904                 update_uic_4_9_irq_ios();
1905         }
1906
1907         /* DMA AB Selection */
1908         if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1909         {
1910                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1911                 update_dma_a_b_ios();
1912                 dma_a_b_selection_in_fpga();
1913         }
1914
1915         /* DMA CD Selection */
1916         if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1917         {
1918                 update_dma_c_d_ios();
1919                 dma_c_d_selection_in_fpga();
1920         }
1921
1922         /* EBC Master Selection */
1923         if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1924         {
1925                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1926                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1927                 update_ebc_master_ios();
1928         }
1929
1930         /* PCI Patch Enable */
1931         if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1932         {
1933                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1934                 update_pci_patch_ios();
1935         }
1936
1937         /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1938         if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1939         {
1940                 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1941                 printf("Invalid configuration => USB2 Host selected\n");
1942                 for (;;)
1943                         ;
1944                 /*usb2_host_selection_in_fpga(); */
1945         }
1946
1947         /* USB2.0 Device Selection */
1948         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1949         {
1950                 update_usb2_device_ios();
1951                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1952                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1953
1954                 mfsdr(sdr_usb0, sdr0_usb0);
1955                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1956                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1957                 mtsdr(sdr_usb0, sdr0_usb0);
1958
1959                 usb2_device_selection_in_fpga();
1960         }
1961
1962         /* USB1.1 Device Selection */
1963         if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1964         {
1965                 mfsdr(sdr_usb0, sdr0_usb0);
1966                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1967                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1968                 mtsdr(sdr_usb0, sdr0_usb0);
1969         }
1970
1971         /* USB1.1 Host Selection */
1972         if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1973         {
1974                 mfsdr(sdr_usb0, sdr0_usb0);
1975                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1976                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1977                 mtsdr(sdr_usb0, sdr0_usb0);
1978         }
1979
1980         /* NAND Flash Selection */
1981         if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1982         {
1983                 update_ndfc_ios();
1984
1985                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
1986                       SDR0_CUST0_NDFC_ENABLE    |
1987                       SDR0_CUST0_NDFC_BW_8_BIT  |
1988                       SDR0_CUST0_NDFC_ARE_MASK  |
1989                       SDR0_CUST0_CHIPSELGAT_EN1 |
1990                       SDR0_CUST0_CHIPSELGAT_EN2);
1991
1992                 ndfc_selection_in_fpga();
1993         }
1994         else
1995         {
1996                 /* Set Mux on EMAC */
1997                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1998         }
1999
2000         /* MII Selection */
2001         if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
2002         {
2003                 update_zii_ios();
2004                 mfsdr(sdr_mfr, sdr0_mfr);
2005                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
2006                 mtsdr(sdr_mfr, sdr0_mfr);
2007
2008                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
2009         }
2010
2011         /* RMII Selection */
2012         if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
2013         {
2014                 update_zii_ios();
2015                 mfsdr(sdr_mfr, sdr0_mfr);
2016                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
2017                 mtsdr(sdr_mfr, sdr0_mfr);
2018
2019                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
2020         }
2021
2022         /* SMII Selection */
2023         if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
2024         {
2025                 update_zii_ios();
2026                 mfsdr(sdr_mfr, sdr0_mfr);
2027                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2028                 mtsdr(sdr_mfr, sdr0_mfr);
2029
2030                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2031         }
2032
2033         /* UART Selection */
2034         uart_configuration = get_uart_configuration();
2035         switch (uart_configuration)
2036         {
2037         case L1:         /* L1 Selection */
2038                 /* UART0 8 pins Only */
2039                 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
2040                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;   /* Chip Pb */
2041                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2042                 break;
2043         case L2:         /* L2 Selection */
2044                 /* UART0 and UART1 4 pins */
2045                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2046                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2047                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2048                 break;
2049         case L3:         /* L3 Selection */
2050                 /* UART0 4 pins, UART1 and UART2 2 pins */
2051                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2052                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2053                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2054                 break;
2055         case L4:         /* L4 Selection */
2056                 /* UART0, UART1, UART2 and UART3 2 pins */
2057                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2058                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2059                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2060                 break;
2061         }
2062         update_uart_ios(uart_configuration);
2063
2064         /* UART Selection in all cases */
2065         uart_selection_in_fpga(uart_configuration);
2066
2067         /* Packet Reject Function Available */
2068         if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2069         {
2070                 /* Set UPR Bit in SDR0_PFC1 Register */
2071                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2072         }
2073
2074         /* Packet Reject Function Enable */
2075         if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2076         {
2077                 mfsdr(sdr_mfr, sdr0_mfr);
2078                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2079                 mtsdr(sdr_mfr, sdr0_mfr);
2080         }
2081
2082         /* Perform effective access to hardware */
2083         mtsdr(sdr_pfc1, sdr0_pfc1);
2084         set_chip_gpio_configuration(GPIO0);
2085         set_chip_gpio_configuration(GPIO1);
2086
2087         /* USB2.0 Device Reset must be done after GPIO setting */
2088         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2089                 usb2_device_reset_through_fpga();
2090
2091 }